TWI329350B - Capacitor attachment method - Google Patents

Capacitor attachment method Download PDF

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Publication number
TWI329350B
TWI329350B TW096106746A TW96106746A TWI329350B TW I329350 B TWI329350 B TW I329350B TW 096106746 A TW096106746 A TW 096106746A TW 96106746 A TW96106746 A TW 96106746A TW I329350 B TWI329350 B TW I329350B
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Taiwan
Prior art keywords
substrate
capacitor
capacitors
flux
attaching
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TW096106746A
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English (en)
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TW200746359A (en
Inventor
Wai Yew Lo
Chee Seng Foong
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Freescale Semiconductor Inc
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/20—Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating
    • B23K1/203—Fluxing, i.e. applying flux onto surfaces
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3489—Composition of fluxes; Methods of application thereof; Other methods of activating the contact surfaces
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/161—Cap
    • H01L2924/1615—Shape
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    • H01L2924/19101—Disposition of discrete passive components
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
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    • H05K2203/04—Soldering or other types of metallurgic bonding
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

1329350 九、發明說明： 【發明所屬之技術領域】 係關 本發明係關於積體電路（1(：)之封裝且更明確而言 於一種將一電容器附加至一基板的方法。 。 【先前技術】
焊錫膏(焊劑媒體中高級焊料合金粉末顆粒之特定摻么 膏體）通常用於將一電容器附加至一基板。圖】說明包括: -電容器附加至一基板形成一半導體封裝之習知方法1〇。 在第-步㈣中，將焊錫膏分配至_基板上之㈣位置上 及在步驟Μ ’❹料錫膏將―電容⑽加至該基板。在 步驟16將㈣分配至基板上之控制崩潰晶片連接（C4)襯墊 上’及在步驟18將-凸塊積體電路(IC)晶粒置放於具焊劑 ::襯塾上。在步驟2〇執行一回焊操作。回焊操作炫融焊 Μ ’從而在電容ϋ與基板之間形成焊接點。在步驟 將-底部填充劑分配至基板與凸塊Ic晶粒之間的間隙中， 進而形成封裝之半導體設備。 然而’在用於將電容器安裝至基板表面上之當前谭料附 加了法中遇到許多問題。此等問題包括焊球形成、豎碑及 。里焊料此等問中題之每_者均會導致產生不合袼的半 、焊球形成為—焊接缺陷，其特徵為存在沿焊接點之周邊 緣所捕集之微小焊球。圖2中展示—焊球形成缺陷之實 例。在圖2中，艮- . 展不一具有第一端端接點32及第二端端接 點34的電容器3〇。 电今30之该弟一端端接點32及該第二 118740.doc 1329350 端端接點34分別經由各別第一焊接點42及第二焊接點料附 加至基板40上之第一電容器襯墊36及第二電容器襯墊38。 如圖可見，焊球46形成於該第—焊接點42之一表面上。許 多此等焊球46之存在常常導致電容器短路。 旦碑係組件之一端起離於一基板且該組件之相對端保持 結合至該基板的現象。圖3中展示一豎碑缺陷之實例。圖3 展示具有第一端端接點52及第二端端接點54的電容器 50。遠電容器50之該第一端端接點52經由一由焊接材料62 浴成之接點60結合至基板58上之第一電容器襯墊％。如圖 可見，電谷器50之第二端端接點54升高且自該基板“上之 第二電容器襯塾64分離。圖3中所示之暨碑缺陷可由沈積 於第一電容器襯墊56及第二電容器襯墊64上之不等量的焊 接材料62引起。 現參看圖4,現將描述過量焊料之實例。圖4展示一具有 第端端接點72及第一端端接點74的電容器70。電容器7〇 之該第一端端接點72及該第二端端接點以分別經由各別第 一焊接點82及第二焊接點84附加至基板⑽上之第一電容器 襯墊76及第二電容器㈣78β然而，歸因於過量焊料之存 在，第一焊接點82及第二焊接點84具有凸面輪廓卯及 92(由圖4中之實線界定），而不再是具有所要之凹面輪㈣ 及88(由圖4中之虛線界定）。過量焊料非吾人所樂見因為 過多焊料可能導致橋接缺陷’此將引起電氣短路。 除由於焊料附加問題而造成半導體單元不合格所帶來的 損失外’將焊錫膏用於電容器附加過程中時亦引發材料、 U8740.doc 1329350 人工及機器的高成本。所有 本。 此專情況增加了總體製造成 鑒於上述内容，需要且備— 一備種將一電容器附加至一 A虹 而無需使用焊錫膏之方法。 基板 【發明内容】 下文結合所附圖式陳述之實 万式思、欲作為對本發明之 當前較佳實施例的描述，而並 不知月之 椹古#斗從九 表不本發明可賴以實踐之 僅有形式。應瞭解，可由意欲 G 3在本發明之精神綠 内之不同實施例來實現相同哎笨 ^ ^ J ^等效功能。在圖式中，相π
編號始終用於指示相同元件。 J 本發明提供一種將一電容器附 ..^ , 王巷板之方法。該方 法基本上包括僅將焊劑塗覆至基板上之金（Au)或鐘金 器襯塾、將該電容器置放於具焊劑之電容器襯塾上，及執 行-回谭操作。電容器端接點較佳為錫（sn)或鐘锡的。 本發明亦提供一種形成一封裝半導體設備之方法，主要 步驟基本上包括僅提供-基板、將谭劑塗覆至該基板上之 -控制崩潰晶片連接(C4)襯塾及各別金或鍍金電容器襯 塾、將-或多個電容器置放於各別電容器襯墊上及將—或 多個積體電路（IC)晶粒置放於基板上之C4襯墊上，及對該 等電容器、該等1C晶粒及基板執行—回焊操作。較佳電 谷盗端接點由錫或鍛錫製成。 本發明進一步提供一種形成一多晶片模組（MCM)之方 法，該方法包括步驟：提供一基板、將焊劑塗覆至該基板 上之各別金（Au)或鍍金電容器襯墊及各別C4襯墊、將具有 I18740.doc 1329350 錫或鍍錫端接點之複數個電容器置放於該等各別電容器襯 墊上及將複數個集體電路（ic)晶粒置放於該等各別C4襯塾 上’及對該等電容器 '該等1C晶粒及基板執行一回焊操作 使得在基板電容器襯墊與各別電容器端接點之間形成金錫 (Au-Sn)金屬間互連件。將底部填充劑分配至基板與各別 1C晶粒之間的複數個間隙中。最後，用複數個蓋中之各別 者密封電容器及1C晶粒，進而形成多晶片模組。 【實施方式】 現參看圖5A至圖5F及圖6 ’描述一根據本發明形成一封 裝半導體設備之方法。 圖5A展示一上面形成有金屬化層ι〇2之基板1〇〇。該金屬 化層102包括一或多個第一電容器襯墊1〇4及第二電容器襯 墊及複數個控制崩潰晶片連接（C4)襯墊（未圖示）。用金 屬電鍍該等第一電容器襯墊104及第二電容器襯墊丨〇6。經 由噴嘴110將焊劑108塗覆至基板1〇〇上之第一電容器襯墊 104及第二電容器襯墊106。在圖6中（圖6為用於形成一封 裝半導體設備之過程150之流程圖），步驟152表示提供基 板100及步驟154表示將焊劑1 〇8塗覆至基板！ 00上的各別電 容器襯墊104及106。 基板1 〇〇較佳為一陶瓷基板，諸如多層陶瓷（MLC)。此 等基板技術上已知且可市購。使用已知電鍍方法在基板 100上形成金屬化層102。金屬化層1〇2可包含銅（Cu)、錫 (Sn)、金（Au)、鎳（Νι)、錫鉛（sn-Pb)焊料或熟習此項技術 者已知之其他適當金屬或合金。較佳用（Au)電鍍該等第— H8740.doc 1329350 電谷器襯墊104及第二電容器襯墊1〇6。在一實施例中，用 Au將金屬化層1〇2及第一及第二電容器襯墊電鍍至約〇丨微 米（μπι)之厚度。然而，熟習此項技術者應瞭解本發明不限 於一特定類型之基板100,不限於用於形成金屬化層102之 金屬或合金，不限於金屬化層1〇2之厚度，或第一電容器 襯塾104及第二電容器襯墊1〇6之厚度。
儘官在圖5Α中未圖示，但焊劑1〇8亦塗覆至基板1〇〇上之 C4襯墊上。圖6中之步驟156表示焊劑1〇8塗覆至以襯墊。 卜知丨1〇8移除來自第一電容器襯塾丄〇4及第二電容器襯塾 106及C4襯墊之氧化物來促進金屬間鍵結之形成。焊劑1〇8 較佳為樹脂型焊劑，諸如樹脂（R)焊劑或樹脂微活性（rma) 焊劑（按焊劑要求之相關ΙΡίΜ·δτ〇_〇〇4標準）。如自圖5A 可見，在此特定實施例中，藉由喷塗而將焊劑！ 〇8塗覆至 第一電容器襯墊104及第二電容器襯墊1〇6。然而，熟習此 項技術者應瞭解本發明不限於此焊接塗覆方法。舉例而 。亦可藉由打點來將焊劑1 〇8塗覆至第一電容器襯墊丨〇4 及第二電容器襯墊106及C4襯墊。另一替代方法為將電容 器浸潰至一焊劑儲集器中且將具有焊劑之電容器轉移至基 板，其中焊劑電容器端接點接觸電容器襯墊1〇4及ι〇6中之 各別者。本發明不同於先前技術方法（圖〇是因為未將焊錫 膏塗覆至電容器襯墊1〇4及1〇6。 ,看圖财圖6,在步驟158，將具有各別第—端端接 點:14及第二端端接點i 16之一或多個電容器⑴置放於各 别第-電容器襯墊104及第二電容器襯墊⑽上。更明確而 Π 8740.doc 言，每一電容器112經置放而跨 。 rt3 ^ _ 艰對第一電谷态襯墊104 與第二電谷器襯墊1〇6，使得第— 容器襯塾⑽且第-端端接5 Μ接點114接觸第-電 丨。“ 第-“接點116接觸第二電容器襯塾 電容器112為晶片上電容器’諸如多層陶竟電容号 (MLCC)。此等電容器112技術上已知且可市購。第一端端 接點Π4及第二端端接點116提供用於電容器μ中之各別 導電元件之電氣端接點。第-端端接點H4及第二端端接 點116可藉由將電容器112之每一端浸潰至厚膜膏體（諸 如’銀（Ag)墨水）中’隨後固化且用金屬及合金（例如，錄 (Ni)及錫（Sn))中之一或多者電鍍電容器ιη之末端來形 成。因此，在一實施例中，第一端端接點丨14及第二端端 接點116包含具有第二Sn電鍍層之鍍鎳銀。在另一實施例 中，電谷器端接點114、116為僅具有錫電鍍層之銀端接 點。可以手動方式或自動方式將電容器112置放於基板1〇〇 上。在圖5B中所示之實施例中，使用一標準取置機之置放 頭118來將電容器112置放於基板100上。在後續處理步驟 期間，由塗覆於第一電容器襯墊1〇4及第二電容器襯墊1〇6 之焊劑108之黏著品質將電容器112固持在適當位置中。 現參看圖5C及圖6，在步驟160，將一或多個積體電路 (1C)晶粒120置放於各別C4襯墊上。所示之實施例中之IC 晶粒120為底面124上具有凸塊連接部122之覆晶晶粒。IC 晶粒1 20置放於基板1 00上使得ic晶粒12〇之凸塊連接部122 接觸基板100上之C4襯墊中之各別者。可藉由自動取置或
Il8740.doc 1329350 手動置放來將1C晶粒120置放於基板1〇〇上。在所示之實施 例中，使用一標準取置機之置放頭126來將IC晶粒12〇置放 於基板100上。 1C晶粒120可為任何類型之電路，諸如數位信號處理器 (DSP)或特定功能電路。Ic晶粒12〇不限於諸如之特 定技術，或不源於任何特定晶圓技術。另外，本發明可接 納各種尺寸之1C晶粒120 ;例如，IC晶粒12〇之尺寸可為約 10¾米（mm)xlO mm。凸塊連接部122係由諸如金' 銅或金 屬合金之導電金屬製成且使用一已知的晶圓凸塊成長製程 形成於1C晶粒120上。此等覆晶凸塊晶粒12〇為熟習此項技 術者所已知且因此不必為全面瞭解本發明而作進一步的解 釋。 現參看圖5D及圖6，在步驟162，藉由將基板1〇〇經過一 回焊爐而對基板100、電容器112及1(：晶粒12〇執行一回焊 操作回焊爐較佳為輸送化的。可使用回焊附加之已知方 =(諸如，紅外線輻射（IR)回焊、氣相回焊及熱氣對流回 焊）來執打回焊操作。較佳在高於約3〇〇〇c之溫度下回焊基 板100、電容器112及1C晶粒120。在一實施例中，在約 360°C之溫度下回焊基板1〇〇 '電容器112及1(：晶粒12〇。 回焊爐中之熱量熔融第一電容器襯墊1〇4及第二電容器 襯墊106及凸塊連接部122。炫融之第一電容㈣㈣^ 第二電容器襯墊1()6潤濕電容器112上之各別第—端端接點 114及第二端端接點116 ’㈣溶融之凸塊連接部⑵潤濕 基板100上之C4襯墊。 118740.doc 12 1329350 現參看圖5E，在冷卻基板100時，金屬間互連件ι28形成 於基板100與各別電容器112之間，同時控制崩潰晶片連接 (C4)互連件130形成於基板1〇〇與各別IC晶粒12〇之間。金 屬間互連件128較佳為包含約20重量百分比（wt%)iAu與約 80 wt%之Sn的金錫（Au-Sn)金屬間互連件。現參看圖7，其 展示一金錫（Au-Sn)系統之相位圖。如自圖7可見，—具有 約20 wt%之Au與80 wt%之Sn的組合物之穩sAu_Sn金屬間 互連件形成於在約280。(：與約30(TC之間的溫度下。然而， 如熟習此項技術者所瞭解的，上文所描述之製程溫度及組 合物僅為例示性的。熟習此項技術者應瞭解本發明不限於 回焊製程之此溫度、金屬間互連件128之組合物或形成金 屬間互連件128之溫度。製程溫度及組合物而是視形成及 電鍍第一電容器襯墊104及第二電容器襯墊1〇6所利用之金 屬或合金的類型而定。 再次參看圖5E，將底部填充劑丨32分配至基板i 〇〇與各別 1C晶粒120之間的複數個間隙134中。在圖6中，步驟164表 示將底部填充劑1 32分配至間隙丨34中。底部填充劑132藉 由減小由基板100與1C晶粒12〇之間的熱膨脹係數（(：丁£)錯 配所引起的C4互連件Π0上之應變來為C4互連件13〇提供 機械支樓《底部填充劑132可包含眾所熟知之可市購底部 填充材料（諸如，環氧樹脂）。在一實施例中，藉由使用一 針件沿各別1C晶粒120之邊緣分配底部填充劑材料來對1(： 晶粒120進行底部填充。在此實施例中，由毛細作用向内 柚取底部填充劑132直至基板1〇〇與各別IC晶粒12〇之間的 U8740.doc 1329350 間隙134被填滿。隨後固化底部填充劑132。然而應瞭解， 本發明不限於底部填充劑！ 32之組合物或不限於上文所描 述之底部填充方法。在替代性實施例中，可使用熟習此項 技術者已知之其他底部填充方法來對IC晶粒12〇進行底部 填充。 現參看圖5F及圖6,在步驟166，用複數個蓋136或罩之 各別者來密封電容器112及1C晶粒120，蓋或罩增強了熱路
控耗散且提供使電容器及晶粒不受外部磨損的保護。更明
確而έ ’蓋136中之每一者置放於一或多個電容器U2&IC 晶粒120中之各別者上方且隨後用蓋附加材料14〇附加至基 板1〇〇以形成複數個密封多晶月模組138。蓋136可由陶瓷 或金屬製成。在使用陶瓷蓋136的情況下，蓋附加材料14〇 可為環氧樹脂或聚矽氧，或當蓋136由金屬製成時，蓋附 加材料140可為焊接材料。在步驟168，複數個導電球144
可附加至基板100之底面〗46。導電球]44可為控制崩潰晶 片載體連接（C5)焊球且其使用已知的焊球附加方法附加至 基板100。 仏s圖5D至圖5F展不三（3)個附加至基板1〇〇之IC晶粒 120 ’但應瞭解’視基板1〇〇之尺寸、ic晶粒之尺寸及 所得半導體封裝設備的所需功能性而定，可將更多或更少 的1C晶粒120附加至基板1〇〇。 不同於諸如圖1中所指述之習知電容器附加方法，本發 明不需要使料料。本發明是直接將電容器置放於基板 之具烊劑之電容器㈣上，2因此在電容器與基板之間形 118740.doc U29350 成五屬間互連件。！I由不再使用焊錫膏，而達成材料、人 力及機斋成本之顯著節約，進而減小了總體封裝成本。此 外’肖除了在使用焊錫膏時遭遇之問題（諸如，焊球形 成、豎碑及過量焊料）。 已出於說明及描述目的呈現對本發明之較佳實施例之描 述但其並非為排斥性的或將本發明限制為所揭示之形式 的。熟習此項技術者應瞭解，可對上文所描述之實施例作 出改變而不脫離其廣泛發明性概念。因此應瞭解，本發明 不限於所揭示之特定實施例，而是涵蓋屬於由所附申請專 利範圍所界定之本發明之精神及範疇内的修改體。 【圖式簡單說明】 圖1為描繪形成一封裝半導體設備之習知方法的流程 圖； 圖2為形成於一電容器與一基板之間的一焊接點表面上 之焊球的放大橫截面圖； 圖3為一端起離於基板且相對端結合至基板之電容器之 放大橫截面圖； 圖4為一電容器與一基板之間的各別焊接點中過量焊料 的放大橫截面圖； 圖5 A為根據本發明之一實施例之塗覆至一基板上之電容 器襯墊之焊劑的放大橫截面圖； 圖5B為置放於圖5A之具焊劑之電容器襯墊上的電容器 之放大橫截面圖； 圖5C為置放於圖5B之基板上的積體電路（ic)晶粒之放大 118740.doc 1329350 橫截面圖； 圖5D為對圖5C之基板、電容器及ΐ(：晶粒執行之。 作的放大橫截面圖； ’’ 圖5E為分配至圖5£)之基板與Ic晶粒之各別者之間的間 隙中之底部填充劑之放大橫截面圖； 圖5F為根據本發明之一實施例所形成之多晶片模組 (MCM)的放大橫截面圖；
圖ό為描繪根據本發明之一實施例形成一封裴半導體設 備之方法的流程圖；及 圖7為一金錫（Au-Sn)系統之相位圖。 【主要元件符號說明】 30 電容器 32 第一端端接點 34 第一端端接點 36 第一電容器襯墊 38 第二電容器襯塾 40 基板 42 第一焊接點 44 第二焊接點 46 焊球 50 電容器 52 第一端端接點 54 第二端端接點 56 第一電容器襯墊 H8740.doc -16- 1329350 58 基板 60 接點 62 焊接材料 64 第二電容器襯墊 70 電容器 72 第一端端接點 74 第二端端接點 76 第一電容器襯墊 78 第二電容器襯墊 80 基板 82 第一焊接點 84 第二焊接點 86 凹面輪廓 88 凹面輪廊 90 凸面輪廟 92 凸面輪廓 100 基板 102 金屬化層 104 第一電容器襯墊 106 第二電容器襯墊 108 焊劑 110 噴嘴 112 電容器 114 第一端端接點 118740.doc 1329350 116 第二端端接點 118 置放頭 120 1C晶粒 122 凸塊連接部 124 晶粒底面 126 置放頭 128 金屬間互連件
130 控制崩潰晶片連接（C4)互連件 132 底部填充劑 134 間隙 136 蓋 138 密封多晶片模組 140 蓋附加材料 144 導電球 146 基板底面
118740.doc -18-

Claims (1)

  1. 十、申請專利範圍： 】· 一種將—電容器附加至一美你夕士， 以下步驟組成·· ▲板之方法，該方法基本上由 將谭劑塗覆於該基板上之各別電容器觀塾； =!f置放於該等具焊劑之電容器襯塾上；及 ·谷器及S亥基板執行—回焊操作。 2.如請求項1之將—電容器附加至_ 金（㈣電鏟該等基板電容器槪塾/ ’其中用 I IS求項2之將一電容器附加至-基板之方法，其中用 錫（Sn)電鍍該等電容器之端接點。 4.求項3之將—電容器附加至-基板之方法，其中金 =雷t)金屬間互連件形成於該等電容器端接點與該等 基板電谷器襯塾之間。 5_ :請求項4之將一電容器附加至一基板之方法，… # Au-Sn金屬間互連件包含 、" 約80 wt%un。 '里百为比（m〇/〇)之Au與 6. Π項金I將—電容器附加至-基板之方法，其中該 n金屬間互連件形成於-在約2贼與約3〇(rc之門 的溫度下❶ 、^υυυ之間 7. 之將一電容器附加至-基板之方法，其中在 8二 〇之溫度下回烊該電容器及該基板。 .焊二::之將—電容器附加至-基板之方法，其中該 Μ包含樹脂焊劑及樹脂微活性焊劑中之 9·如請求項1之將—電容器附加至一基板之方法。，其中該 118740.doc 焊劑係藉由喷塗及打點中之一者來塗覆β 1〇·:請求項!之將一電容器附加至_基板之方法，其中該 焊劑移除來自該基板上之該等電容器概塾之氧化物。ν u. ^請求項10之將-電容器附加至_基板之方法，其中該 焊劑將該電容器固持在適當位置中。 " 12·—種形成-封裝半導體設備之方法，該方法基本上由以 下步驟組成： 提供一基板； 將一焊劑塗覆於該基板上之各別電容器襯墊； 將一或多個電容器置放於該等各別電容器襯墊上，其 中忒等電谷器之端接點接觸該等基板電容器襯墊之各 者； 將一或多個積體電路（IC)晶粒置放於該基板上之各別 控制朋潰晶片連接（C4)襯塾上；及 對該或該等電容器、該或該等1C晶粒及該基板執行一 回焊操作。 13·如請求項12之形成一封裝半導體設備之方法，其中金錫 (Au-Sn)金屬間互連件形成於該等基板電容器襯墊與該或 該等各別電容器之該等端接點之間。 14_如請求項12之形成一封裝半導體設備之方法，其進一步 基本上由以下步驟組成：將該焊劑塗覆於該基板上之該 等各別C4襯墊。 15.如請求項12之形成一封裝半導體設備之方法，其進—步 基本上由以下步驟組成：將一底部填充劑分配至該基板 118740.doc 16. 17 18 19 20 士、&或忒等各別IC晶粒之間的一或多個間隙中。 月求項15之形成一封装半導體設備之方法，苴進一步 ^ | ’、 以下步驟組成：密封該或該等電容器及該或該 等1C晶粒。 求員16之形成一封裝半導體設備之方法，其中用一 或夕個盖中之各別者來密封該或該等1C晶粒及該或該等 電容器。 •如°月求項16之形成一封裝半導體設備之方法，其進一步 基本上由以下步驟組成：將複數個導電球附加至該基板 之一底面。 如味求項12之形成一封裝半導體設備之方法，其中在一 高於約3GGt之溫度下回焊該或該等電容器及該或該等IC 晶粒。 •一種形成一多晶片模組之方法，該方法包含以下步驟： 提供一具有鍍金電容器襯墊之基板； 將一焊劑塗覆至該基板上之各別電容器襯墊及各別控 制崩潰晶片連接（C4)襯墊； 將複數個電合器置放於該等各別具焊劑之電容器襯墊 上’其中該等電容器具有鍍錫端接點； 將複數個積體電路（IC)晶粒置放於該等各別具焊劑之 C4襯墊上； 對該基板、該等電容器及該等IC晶粒執行一回焊操作 使得金錫（Au-Sn)金屬間互連件形成於該等基板電容器襯 墊與該等各別電容器之端接點末端之間； H8740.doc 1329350
    將一底部填充劑分配至該基板與該等各別ic晶粒之間 的複數個間隙中；及 用複數個蓋中之各別者密封該等電容器及該等1C晶 粒5進而形成§亥多晶片模組。 118740.doc
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