TWI414049B - 半導體裝置之製造方法 - Google Patents
半導體裝置之製造方法 Download PDFInfo
- Publication number
- TWI414049B TWI414049B TW099116411A TW99116411A TWI414049B TW I414049 B TWI414049 B TW I414049B TW 099116411 A TW099116411 A TW 099116411A TW 99116411 A TW99116411 A TW 99116411A TW I414049 B TWI414049 B TW I414049B
- Authority
- TW
- Taiwan
- Prior art keywords
- solder
- semiconductor wafer
- connection
- electrodes
- semiconductor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/165—Material
- H01L2224/16501—Material at the bonding interface
- H01L2224/16503—Material at the bonding interface comprising an intermetallic compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/165—Material
- H01L2224/16505—Material outside the bonding interface, e.g. in the bulk of the bump connector
- H01L2224/16507—Material outside the bonding interface, e.g. in the bulk of the bump connector comprising an intermetallic compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01032—Germanium [Ge]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01049—Indium [In]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Description
本發明係關於半導體裝置之製造技術,尤其係關於使用貫通半導體晶片間之電極而進行上下間之半導體晶片、配線基板之電力連接之積層方法,以及使用其之半導體裝置、電器設備。另,係關於亦適用於將搭載有半導體晶片之配線基板積層之半導體裝置、電子零件之有效技術。
近年來之行動電話或數位相機等電子機器中,電子機器之高功能化、小型輕量化具重要性,作為用以實現此之電子零件,需要高功能、小型、薄型之電子零件。因此,因搭載有電子零件之半導體晶片之大規模積體電路(LSI)微型化而高密度化及作為封裝構造,正進展利用SiP(System in Package)技術而高密度化。
但為使LSI更微型化,必須更新LSI製造線,需要巨額之設備投資。另,因微型化引起之漏電流等問題亦變得顯著,亦會產生性能提高度與理論值有所偏差之情形。
SiP之構造係於稱作中介(Interposer)基板等之中間基板搭載複數之LSI並進行樹脂密封者,晶片電極、中介基板電極間多使用Au線以引線接合進行連接。引線接合因電線圍繞之自由度較高而對電力連接有效。作為可減小安裝面積之方法,搭載於中介基板正上方之晶片使晶片之主動元件面朝向中介基板側,藉由Au凸塊、焊錫凸塊、ACF(Anisotropic conductive film,各向異性導電膜)等進行倒裝晶片連接亦增加。
因此,為使該SiP構造之電子零件更加高密度化、小型化,需要晶片、基板之薄型化、電極之小節距化等,但因主要包含有機基板之中間基板之製造界限、Au線等之電線細線化界限、微細範圍之引線接合可靠性等而變得困難。再者,面對移動設備之電子零件中,對低消耗電力化之要求正變得嚴格。SiP構造中,由於從各晶片一次經由中間基板而連接,而有配線長度較長,高速傳送較困難,且消耗電力亦較大之問題。
根據以上,相對逐漸進展之高功能化、小型化,進而對低耗散電力之要求,尚無法對上述由LSI微型化之高密度化、由SiP技術之高密度化之對策作出充分解答。
因此,三維LSI作為上述問題之1個解決方法正引起注目。該三維LSI係使用貫通晶片之電極,進行上下間之晶片、基板之電力連接者,由於可減短配線長度,因此對高速傳送、低消耗電力化有效。另,安裝面積亦變小,對小型化有利。因此提案有用以積層連接上下間之各種方式(專利文獻1~3)。
專利文獻1中記載有半導體晶片之堆疊方法。於決定複數晶片搭載範圍之半導體基板之各晶片搭載位置堆疊晶片。其後,以密封材密封所堆疊之晶片,其後,於晶片搭載區域外側所決定之位置切斷半導體基板,分離成複數之半導體裝置。
專利文獻2中記載有基板積層方法。係提供一種積層基板時抑制基板之彎曲,可容易處理基板之基板積層方法,係連接基板間後,從背面磨削直至使貫通電極露出而進行薄型化之方法。
專利文獻3中記載有降低接合溫度之連接方法。此係於導體層經由含銅-銦合金之中間層,使用含銦之導體進行連接者,可利用Sn-3.5Ag等焊錫合金凸塊將接合溫度較低地設定。
[專利文獻1]日本特開2005-51150號公報
[專利文獻2]日本特開2008-135553號公報
[專利文獻3]日本特開2007-234841號公報
但如前述之三維LSI中,隨著晶片、基板因高密度化而薄型化,易產生彎曲,處理變得困難。且使該等彎曲之某零件彼此正確對位而連接亦變得困難。
另,若連接時變高溫,則有因連接構件間之材料物性之差異,彎曲量之差變大之情形。因此,連接時之溫度非為高溫較佳。例如使用Sn-Ag系焊錫等熔點為220℃左右之材料時,以材料之凝結溫度(熔點)限制連接部,由於冷卻至室溫之材料收縮量之差異,應力會殘留於連接部,相對長期之連接部可靠性需要降低該殘留應力量。因此以低溫連接較有效。特別於基板/晶片間之連接,由於基板之半導體晶片間之熱膨脹係數差較大而連接部之殘留應力變大,因此連接部若可在基板之玻璃轉移溫度以下固化,則可大幅降低殘留應力。
因此提案有使用如上述專利文獻3所示之銦等金屬進行連接之方式。
但為提供積層晶片、基板之高密度半導體封裝,需要每次積層連接晶片等時進行加熱之步驟,連接部被加熱熔融數次。因此,最初連接之部份在之後被加熱,有發生熔融而分離之可能性。因此於最初連接之部份有必要預先作成即使在之後被加熱亦不會產生問題之連接部。
另,尤其於積層連接薄晶片之步驟中,需要以低負荷進行,以不會對晶片產生破壞。
由上,本發明係為實現將薄晶片、基板積層,可以高功能高速傳送之高可靠半導體封裝(半導體裝置),其目的係提供一種可以低溫、低負荷確實連接,且即使於積層製程、其後之安裝製程等中進行加熱,連接部亦可保持形狀之連接製程、連接構造。
本發明之前述及其他目的與新穎特徵由本說明書所描述及附加圖式而變得更明瞭。
如下簡單說明本說明書所揭示之發明中之代表性者之概要。
(1)一種將半導體晶片或搭載有半導體晶片之配線基板予以積層之半導體裝置,其特徵在於:積層之半導體晶片或配線基板之電極間之連接構造具備以Cu為主成份之一對電極,及夾於電極間之由Sn-In系合金所成之焊錫層,於焊錫層中分散有Sn-Cu-Ni化合物。
(2)一種將半導體晶片或搭載有半導體晶片之配線基板予以積層之半導體裝置之製造方法,其特徵在於:具有於積層之半導體晶片或配線基板表面形成以Cu為主成份之電極之步驟;對電極間供給分散Ni粒子之由Sn-In系合金所成之焊錫之步驟;及加熱電極間,於焊錫中分散Sn-Cu-Ni化合物之步驟。
(3)一種將半導體晶片或搭載有半導體晶片之配線基板予以積層之半導體裝置,其特徵在於:積層之半導體晶片或配線基板之電極間之連接構造具備以Cu為主成份之一對電極,及夾於電極間之由Sn-In系合金所成之焊錫層,焊錫層中分散有具有2種粒徑分佈之Sn-Cu-Ni化合物。
(4)一種將半導體晶片或搭載有半導體晶片之配線基板予以積層之半導體裝置之製造方法,其特徵在於:具有於積層之半導體晶片或配線基板表面形成以Cu為主成份之電極之步驟;對電極間供給分散有具有2種粒徑分佈之Ni粒子之由Sn-In系合金所成之焊錫之步驟;及加熱電極間,於焊錫中分散Sn-Cu-Ni化合物之步驟。
(5)一種將半導體晶片或搭載有半導體晶片之配線基板予以積層之半導體裝置製造所使用之焊錫,其特徵在於:含有焊錫粉末與粒子,焊錫粉末係包含Sn-In、Sn-Bi、Sn-Bi-In之一種,或進而添加Ag、Ge、Cu、Al、Fe、Pt、P之至少一種以上者,粒子係使用Ni、Al、Fe、Ge、Ag、Pt,以單體含有該等粒子,或組合複數材料而含有者。
(6)半導體晶片或配線基板之積層構造中,為使該積層構造於再加熱時可耐受熱,於電極間之連接部之高度為50 μm,更好連接部之高度為30 μm。另,該連接部中,析出之化合物較好與在上下電極之界面產生之化合物層相接之構造。
如下簡單說明本說明書所揭示之發明中由代表性者而得之效果。
由於利用Sn-In系合金進行連接,於Sn-In合金為Sn-52質量%In時熔點可低溫化至120℃,因此可以低溫連接,可降低因彎曲產生之問題,可提高連接良率。
以下,基於附圖詳細說明本發明之實施形態。再者,用以說明實施形態之全圖中,同一部份原則上附加同一符號,省略其重複說明。
(實施形態1)
使用圖1說明本發明之實施形態1之第1連接構造。本實施形態中,以將半導體晶片或搭載有半導體晶片之配線基板積層之半導體裝置為例,針對積層之半導體晶片或配線基板之電極間之連接構造進行說明。
圖1所示之第1連接構造1由積層之下側半導體晶片或配線基板之電極2;積層之上側半導體晶片或配線基板之電極3;及夾於該一對電極2、3間之焊錫層5所構成。該第1連接構造1中,於一對電極2、3之界面析出Sn-Cu-Ni化合物4,並於焊錫層5內部分散Sn-Cu-Ni化合物6。
電極2、3包含Cu或以Cu為主成份之材料。此時之電極2與電極3間之間隔(連接部之高度)d1為50 μm以下,較佳為30 μm以下。焊錫層5包含Sn-In系合金之焊錫。另,較佳為形成於焊錫層5內部之Sn-Cu-Ni化合物6與形成於某一電極界面之Sn-Cu-Ni化合物4相接,進而更佳為與形成於兩方之電極界面之Sn-Cu-Ni化合物4相接。
圖2係顯示用以實現圖1所示第1連接構造1之前階段構造之圖。圖2係顯示於由Cu所成之電極2、3間,供給分散有Ni粒子之由Sn-In系合金所成之焊錫膏,具體為供給使Sn-In焊錫粉末7與Ni粒子8與有機成份9混合之焊錫膏10之狀態,藉由對其加熱而從Sn-In焊錫粉末7供給Sn,從Ni粒子8供給Ni,如圖1所示,於由Cu所成之電極2、3界面析出有Sn-Cu-Ni化合物4。另,焊錫膏10之內部,以所添加之Ni粒子8為核心,藉由來自電極2、3之Cu與Sn-In焊錫粉末7中之Sn反應,析出Sn-Cu-Ni化合物6,變化成如圖1所示之構造。
有機成份9除有機溶劑外,為提高焊之濕潤性,亦可含有酸、有機酸等活性助焊劑成份。該等焊錫膏10若可以連接後之製程洗淨,則亦可含有活性強的鹵素成份。但為對應無洗淨製程,重要的是助焊劑殘留不會有腐蝕性,低鹵素、無鹵素者亦係重要。另,加熱後之助焊劑殘留成為問題時,有機溶劑易揮發,成為固形成份少之有機成份9。為提高連接後之強度,若使用含加熱時硬化之樹脂成份之有機成份9,則可以樹脂覆蓋連接構造周圍,可提高連接強度。
對電極2、3供給焊錫膏10之方法可以分配器供給、印刷方式、浸漬方式等進行。於形成薄焊錫層5,少量供給焊劑量有困難時,可增多焊劑膏10中之有機成份9之比例,可某程度地調整加熱後殘留之焊錫量。
圖3係顯示其他例作為用以實現圖1所示第1連接構造1之前階段之構造。圖3係於焊錫膏10中,含有以Sn-In層12被覆Ni核心11之焊錫粒子。此外藉由含有Sn-In焊錫粉末7、有機成份9,將該等加熱,而自電極2、3供給Cu,使Ni核心11之周圍化合物化,如圖1所示,Sn-Cu-Ni化合物6於Sn-In系合金之焊錫層5中析出。作為圖3所示方式之優點,由於預先被覆Ni核心11,因此可降低原本濕潤性不佳之Ni濕潤性問題。
另,圖2及圖3中,於電極2、3間供給焊錫膏10,一次加熱而形成圖1之連接構造1,但對一對電極2、3中一方之電極供給焊錫膏並加熱,其後與另一方電極對位並加熱,藉此亦可形成圖1之連接構造。此時,與另一方電極接合時之焊錫粘附性成為問題,但利用噴射、旋轉塗層、分配器等方法另外添加助焊劑成份亦可解決。
關於Sn-In焊錫粉末7、Ni粒子8之大小,由於對焊錫層5厚度之限制,Sn-In焊劑粉末為30 μm以下,較佳為15 μm以下,Ni粒子8為20 μm以下。
圖4係顯示形成有具有2種粒徑分佈之Sn-Cu-Ni化合物之第2連接構造13,作為本發明之實施形態1之其他連接構造。即,第2連接構造13係於由Cu所成之電極2、3之界面形成Sn-Cu-Ni化合物4,於Sn-In系合金之焊錫層5中形成有大粒徑之Sn-Cu-Ni化合物14,及小粒徑之Sn-Cu-Ni化合物15之構造。
圖5係顯示用以實現該第2連接構造13之前階段構造之圖。圖5係顯示加熱前之情況,係使具有2種粒徑分佈之Ni粒子分散之由Sn-In系合金所成之焊錫膏16供給於電極2、3間之狀態,具體言之,係含有5~20 μm之Ni粒子17與0.1~5 μm之Ni粒子18者,其他係以Sn-In焊錫粉末7、有機成份9構成。大粒徑之Ni粒子17係與Cu、Sn化合物化而增大體積,成為圖4中之Sn-Cu-Ni化合物14,即使利用其後之加熱亦有助於使連接構造13穩定化者。另一方面,微細Ni粒子18係加熱後變成圖4中之小粒徑Sn-Cu-Ni化合物15,因表面積比例變多而有助於提高反應性者。另,作為其他效果,以粒徑大之Ni粒子17形成之大粒徑Sn-Cu-Ni化合物14例如以熱壓接連接製程等使壓頭下降時,可有效地穩定決定連接部之高度d2。
以上說明之第1連接構造1及第2連接構造13中,關於焊錫膏之成份,除Sn-In焊錫粉末外可使用Sn-Bi、Sn-Bi-In,進而對該等添加Ag、Ge、Cu、Al、Fe、Pt、P之至少一種以上之焊錫粉末。至於Ni粒子以外,為Al、Fe、Ge、Ag、Pt,該等粒子亦可以單體含於焊錫膏中,組合複數材料含有亦有效。但對上述焊錫粉末成份溶入上述粒子成份合金化後即使粉末化亦無效。或者反應後成為金屬化有機成份而添加亦無效。即,重要的是以金屬粒子添加於焊錫膏中,以該等為核心進行反應,使Sn-Cu-Ni化合物於連接構造中析出。
圖6係顯示第3連接構造22作為本發明之實施形態1之其他連接構造。圖7係顯示用以實現該第3連接構造22之前階段之構造。第3連接構造22係使用圖7所示之添加有突起之某形狀之Ni19之焊錫膏20者,加熱後如圖6所示,突起之某形狀之Sn-Cu-Ni化合物21成為卡於在電極2、3界面形成之Sn-Cu-Ni化合物4之狀態,可增大其後之再加熱時焊錫層5移動之防止效果。
(實施形態2)
作為本發明之實施形態2,使用圖8至圖12,針對使用前述實施形態1之連接構造之半導體裝置之製造方法進行說明。該半導體裝置之規格係於中間基板上基層4層半導體晶片,於中間基板之背面具有安裝有用以在主機板上安裝之焊錫凸塊之構造者。
圖8係顯示Si晶圓與半導體晶片之配置圖。圖9係顯示使用圖8之Si晶圓之半導體晶片之形成方法之圖。圖10及圖11係顯示圖9所示之半導體晶片之積層連接方法及半導體裝置之構造之圖。圖12係顯示將圖9至圖11所示之半導體晶片積層連接時之連接構造之詳細變化之圖。
為製造該半導體裝置,首先如圖8(1)所示,於Si晶圓31上形成電路。此係切斷成各半導體晶片32(於各半導體晶片32之邊界線41切斷)前之狀態,如圖8(2)所示,於在各個半導體晶片32之配置於晶片區域周邊之貫通電極具有焊錫凸塊33。
於圖9顯示具有該焊錫凸塊33之半導體晶片32之形成方法。(1)使用形成有主動元件面34之Si晶圓31,(2)於Si晶圓31之主動元件面34形成凹部35,對該凹部35內填充導電構件36後,(3)使用金屬遮罩38利用印刷將混合有Sn-In焊錫粉末與Ni粒子與有機成份之焊錫膏37供給於各貫通電極上並加熱,(4)形成焊錫凸塊33。其後,(5)藉由對圖8之Si晶圓31之形成有焊錫凸塊33的主動元件面34之背面進行研磨,使凹部35內之導電構件36露出於背面而成為背面之電極40。藉此,使Si晶圓31之上下面貫通。填充於凹部35內之導電構件36係使用Cu。接著,(6)利用切割將各半導體晶片32之邊界線41切斷,得到單片半導體晶片32。
於圖10及圖11顯示半導體晶片32完成後之步驟。(1)將形成有焊錫膏33之半導體晶片32搭載於熱壓接裝置之台座42上,(2)對位搭載第2層半導體晶片32並加熱,藉此(3)使第1層半導體晶片32與第2層半導體晶片32之上下間電極積層連接。(4)重複實施如此貫通電極間之積層連接,將4層半導體晶片積層(44),(5)顛倒如此積層連接之半導體晶片44並與有機基板45之電極46對位,利用加熱使之連接。其後,(6)於有機基板45之背面安裝外部端子用焊錫球47,將有機基板45切割成各單片,半導體裝置48完成。
此處,於圖12顯示積層連接半導體晶片時之連接構造之詳細變化。圖12中,以前述實施形態1中使用圖1與圖2說明之第1連接構造為例而顯示。
圖12(1)係顯示使用金屬遮罩38以印刷將混合有Sn-In焊錫粉末7與Ni粒子8與有機成份9之焊錫膏37,供給至形成於Si晶圓31之凹部35中所填充之由含Cu的導電構件36所成之貫通電極上之狀態。
接著,圖12(2)係顯示取下金屬遮罩38,加熱至Sn-In焊錫粉末7之熔點120℃以上之溫度,例如加熱至145℃之狀況。藉此,在由Cu所成之貫通電極(導電構件36)與Sn-In系合金之焊錫層5之界面可發現Sn-Cu-Ni化合物4,且於焊錫層5內部亦分散有以添加之Ni粒子8為核心生長之Sn-Cu-Ni化合物6。該等成為焊錫凸塊33之成份。
接著,相對於形成有該構造之焊錫凸塊33之半導體晶片,於該半導體晶片之焊錫凸塊33上部連接其他半導體晶片之由Cu所成之貫通電極時,如圖12(3)所示,係成為於Sn-In系合金之焊錫層5中分散有Sn-Cu-Ni化合物6之構造。又,在與由Cu所成之貫通電極之界面可發現Sn-Cu-Ni化合物4。
針對藉由具有如此連接構造而可積層連接之理由進行說明。首先,於Sn-In系合金之焊錫層5中分散之Sn-Cu-Ni化合物6之熔點較高,因此該Sn-Cu-Ni化合物6於之後再加熱步驟中亦不會熔融。且使由焊錫層5之連接高度變薄,而讓該連接高度中Sn-Cu-Ni化合物6所占比例高之部份局部地形成,藉此即使焊錫層5之部份再熔融,連接部亦不會破斷。因此可積層連接。
但更有效為將全體以樹脂密封,謀求提高連接材所產生之強度而可更確實防止破斷。
該構造可使用倒裝晶片焊機等接合設備,以熱壓接步驟實現。熱壓接步驟中,利用加壓可更縮短被連接部間之距離,因此所形成之Sn-Cu-Ni化合物可在到達電極之上下面之前擠入。可形成比熔融時更穩定之連接部。即使是回焊爐等不進行加壓之設備亦可使焊錫量最適化,藉此可形成熔融時穩定之連接部。
根據如上步驟,可得到積層有半導體晶片32之半導體裝置48。該半導體裝置48之特徵係由於使用Sn-In系合金焊錫層5而可以低溫接合,可降低殘留於連接部之應力。尤其係有機基板(FR4、FR5)中,玻璃轉移溫度分別在120℃、150℃左右,焊錫在玻璃轉移溫度以下固化,因此與熔點220℃左右之Sn-Ag系、熔點280℃左右之Sn-Au系相比殘留應力變少,係連接部形成之良率提高且長期可靠性優良之構造。
(實施形態3)
作為本發明之實施形態3,使用圖13及圖14,針對使用前述實施形態1之連接構造之其他半導體裝置之製造方法進行說明。前述實施形態2中於Si晶圓上一同進行焊錫凸塊之形成,使用經切片成為單片之半導體晶片32者,使該半導體晶片32之主動元件面34朝上進行積層,最後集中連接於有機基板45。但不限於該方法。
本實施形態之半導體裝置之製造方法中,作為半導體晶片之積層連接方法及半導體裝置之構造,例如於圖13及圖14係顯示使半導體晶片32之主動元件面34朝下與有機基板45連接之例。
首先,(1)使半導體晶片32之主動元件面34朝向有機基板45側,與有機基板45上之電極46對位,進行熱壓接。該有機基板45係不僅與1個半導體晶片對應,亦與複數之半導體晶片對應之有機基板,係最終切割分離成各區域者。接著(2)使之加熱,於有機基板45上連接第1層半導體晶片32。然後(3)為提高連接部之可靠性,於半導體晶片32與有機基板45之間隙注入底部填充樹脂49,使之硬化。接著(4)將有機基板45再次返回至熱壓接裝置之台座42上,使第2層半導體晶片32對位並進行熱壓接。重複此操作,(5)於有機基板45上積層4層半導體晶片32。接著(6)於有機基板45上對必要之部份全體注入、密封模製樹脂43,(7)安裝外部端子用之焊錫球47,(8)切斷成各半導體裝置50。
此處,關於保護連接部周圍之底部填充樹脂49,圖13及圖14之例中,只保護與有機基板45相接之半導體晶片32之連接部。此係認為於第1層半導體晶片32中,由於有機基板45與半導體晶片32之熱膨脹係數差而增大應力,但考慮到第1層之後由於例如第2層與第3層中成為Si彼此之連接故而熱膨脹係數差變小,不太需要連接部之保護,但亦可分別使用底部填充樹脂。或者亦可作成真空氛圍,一同密封底部填充樹脂。另,此時亦可藉由在熱壓接製程前以分配器等供給樹脂並熱壓著,藉此使該樹脂硬化般使用先前塗布樹脂。
(實施形態4)
作為本發明之實施形態4,係使用圖15,針對將前述實施形態1之連接構造用於其他連接形態之例進行說明。圖15係顯示將具有Cu桿柱51之半導體晶片52與有機基板53連接之方法之例。
首先,(1)對有機基板53上之由Cu所成之電極54,供給混合有Sn-Bi焊錫粉末與Ni粒子與有機成份之焊錫膏55。接著(2)使形成有Cu桿柱51之半導體晶片52對位,利用熱壓接步驟而連接,(3)得到目的之連接構造體56。此時,由於使用含有Sn-Bi焊錫粉末之焊錫膏55,因此使連接溫度設為170℃可確保確實之濕潤性。又,雖該連接構造體56於之後步驟中,經過使其他半導體晶片與有機基板53間之焊線連接、於有機基板53背面附著外部端子用焊錫球、及對主機板之安裝等步驟,但藉由以Ni粒子為核心而生成之Sn-Cu-Ni化合物於連接部中析出,於之後步驟中不會產生剝離等問題。
根據以上可知,藉由採用前述實施形態1之連接構造,係可低溫加熱且可降低應力,並且可承受積層連接。
以上,基於實施形態具體說明由本案發明者完成之發明,但本發明不限於前述實施形態,當然在不脫離其主旨之範圍內可進行各種變更。
例如作為使用前述實施形態1之連接構造之其他連接形態,亦可適用於CoC連接等之半導體晶片/半導體晶片間之連接、封裝構造之積層連接、PoP連接等,對可靠性提高有效。
其中,於圖16顯示封裝構造之積層連接之例。圖16中係顯示將半導體封裝63積層連接成3層之構造。各半導體封裝63係於基板61上搭載半導體晶片62,以模製樹脂66密封。各半導體封裝63間係使用前述實施形態1之連接構造65,且經由各半導體封裝63之通孔電極64而電性連接。並且,於最下層之半導體封裝63之背面安裝有外部端子用焊錫球67。如此連接形態中亦可得到與前述實施形態相同之效果。
本說明書之實施形態所記載之發明由於利用Sn-In系合金而連接,因此Sn-In系合金中,於Sn-52質量%In時熔點可低溫化至120℃,因此可以低溫連接,因彎曲引起之問題得以減低,可提高連接良率。
又,本說明書之實施形態所記載之發明由於電極間之連接部中之焊錫固化溫度經低溫化,因此可降低連接部之殘留用力,可提高連接部之可靠性。尤其係有機基板之玻璃轉移溫度為高耐熱者係150℃左右,由於通常之FR4等級之有機基板中為120℃左右,因此可在玻璃轉移溫度以下之溫度固化,可大幅降低殘留應力。
再者,本說明書之實施形態所記載之發明,電極材料係以Cu為主成份,且對焊錫中預先添加Ni粒子,因此Sn-Cu-Ni化合物析出於焊錫層中,因此即使在連接後,進而接著進行半導體晶片等之積層連接、焊錫凸塊附著、對主機板之安裝等之加熱製程中,連接部再熔融亦不會有連接部破斷等問題,而可加以積層。
另,本說明書之實施形態所記載之發明在將具有2種以上粒徑分佈之Ni粒子添加於焊錫中時,顯示微細粒徑(~5 μm以下)之Ni粒子促進反應之效果,若粒徑大之Ni粒子(5~20 μm)與焊錫成份、電極成份反應而增大體積之化合物夾於電極間,則可利用於調整連接部之高度。再者,藉由該化合物夾於電極間之構造,即使連接部再熔融亦可強固地防止連接部破斷。
另,本說明書之實施形態所記載之發明係使焊錫材料熔融而連接,因此可以低負荷連接,對薄半導體晶片亦適用。
另,本說明書之實施形態所記載之發明之其他本發明之效果,於先前之倒裝晶片連接中,大多利用貴金屬Au在Sn中容易溶解之性質,使用焊錫在連接時高熔點化之Au焊錫製程等,即使不使用Au,與Cu-Sn之生成速度相比,Cu-Ni-Sn化合物之生成速度快,因此可進行不使用Au之脫Au連接。此可以說是低成本化之有效製程。
本發明係關於半導體裝置之製造技術,尤其係可廣泛利用於半導體晶片、或將搭載有半導體晶片之配線基板積層之半導體裝置、或電器設備、電子零件等。
1...連接構造(第1)
2...電極
3...電極
4...Sn-Cu-Ni化合物(界面)
5...焊錫層
6...Sn-Cu-Ni化合物(焊錫中)
7...Sn-In焊錫粉末
8...Ni粒子
9...有機成份
10...焊錫膏
11...Ni核心
12...Sn-In層
13...連接構造(第2)
14...Sn-Cu-Ni化合物(大粒徑)
15...Sn-Cu-Ni化合物(小粒徑)
16...焊錫膏(添加具有2種粒徑分佈之Ni粒子)
17...Ni粒子(粒徑5~20 μm)
18...Ni粒子(粒徑0.1~5 μm)
19...Ni(有突起之形狀)
20...焊錫膏(含突起之Ni粒子)
21...Sn-Cu-Ni化合物(有突起之形狀)
22...連接構造(第3)
31...Si晶圓
32...半導體晶片
33...焊錫凸塊
34...主動元件面(Si晶圓)
35...凹部
36...導電構件
37...焊錫膏(混合Sn-In焊錫粉末與Ni粒子與有機成份)
38...金屬遮罩
40...電極(背面)
41...邊界線
42...熱壓接裝置之台座
43...模製樹脂
44...積層連接之半導體晶片
45...有機基板
46...電極
47...焊錫球(外部端子用)
48...半導體裝置
49...底部填充樹脂
50...半導體裝置
51...Cu桿柱
52...半導體晶片
53...有機基板
54...電極
55...焊錫膏(混合Sn-Bi焊錫粉末與Ni粒子與有機成份)
56...連接構造體
61...基板
62...半導體晶片
63...半導體封裝
64...通孔電極
65...連接構造
66...模製樹脂
67...焊錫球
圖1係顯示本發明之實施形態1之第1連接構造之圖。
圖2係顯示用以實現圖1所示第1連接構造之前階段之構造之圖。
圖3係作為用以實現圖1所示第1連接構造之前階段構造,顯示其他例之圖。
圖4係顯示本發明之實施形態1之第2連接構造之圖。
圖5係顯示用以實現圖4所示第2連接構造之前階段構造之圖。
圖6係顯示本發明之實施形態1之第3連接構造之圖。
圖7係顯示用以實現圖6所示第3連接構造之前階段構造之圖。
圖8(1)、(2)係本發明之實施形態2之半導體裝置之製造方法中,顯示Si晶圓與半導體晶片之配置之圖。
圖9(1)~(6)係顯示使用圖8之Si晶圓之半導體晶片之形成方法之圖。
圖10(1)~(5)係顯示圖9所示之半導體晶片之積層連接方法及半導體裝置之構造之圖。
圖11(6)係接續圖10顯示半導體晶片之積層連接方法及半導體裝置之構造之圖。
圖12(1)~(3)係顯示將圖9至圖11所示之半導體晶片積層連接時之連接構造之詳細變化之圖。
圖13(1)~(5)係本發明之實施形態3之半導體裝置之製造方法中,顯示半導體晶片之積層連接方法及半導體裝置之構造之圖。
圖14(6)~(8)係接續圖13顯示半導體晶片之積層連接方法及半導體裝置之構造之圖。
圖15(1)~(3)係作為本發明之實施形態4,顯示將具有Cu桿柱之半導體晶片與有機基板連接之方法之圖。
圖16係作為使用本發明之實施形態1之連接構造之其他連接形態,顯示將半導體封裝積層連接成3層構造之圖。
1‧‧‧連接構造(第1)
2‧‧‧電極
3‧‧‧電極
4‧‧‧Sn-Cu-Ni化合物(界面)
5‧‧‧焊錫層
6‧‧‧Sn-Cu-Ni化合物(焊錫中)
Claims (3)
- 一種半導體裝置之製造方法,特徵在於包含下述步驟,即:(a)準備包括包含Cu之電極之半導體晶片、及包括包含Cu之電極之配線基板之步驟;(b)經由以Sn、In為主要元素之焊錫粉末與Ni粒子混合之焊錫膏,將前述半導體晶片搭載至前述配線基板上之步驟,在此,前述焊錫膏係供給至前述半導體晶片之前述電極與前述配線基板之前述電極之間;及(c)藉由加熱前述焊錫膏而於前述焊錫膏內析出Sn-Cu-Ni化合物之步驟。
- 如請求項1之半導體裝置之製造方法,其中前述Sn-Cu-Ni化合物係與前述半導體晶片之前述電極及前述配線基板之前述電極中之一方接觸。
- 如請求項1之半導體裝置之製造方法,其中前述Sn-Cu-Ni化合物係與前述半導體晶片之前述電極及前述配線基板之前述電極中之雙方接觸。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009167716A JP5465942B2 (ja) | 2009-07-16 | 2009-07-16 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201104817A TW201104817A (en) | 2011-02-01 |
TWI414049B true TWI414049B (zh) | 2013-11-01 |
Family
ID=43464697
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW099116411A TWI414049B (zh) | 2009-07-16 | 2010-05-21 | 半導體裝置之製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8633103B2 (zh) |
JP (1) | JP5465942B2 (zh) |
CN (2) | CN104022092A (zh) |
TW (1) | TWI414049B (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8810035B2 (en) * | 2010-10-22 | 2014-08-19 | Panasonic Corporation | Semiconductor bonding structure body and manufacturing method of semiconductor bonding structure body |
US9324905B2 (en) | 2011-03-15 | 2016-04-26 | Micron Technology, Inc. | Solid state optoelectronic device with preformed metal support substrate |
JP5613100B2 (ja) * | 2011-04-21 | 2014-10-22 | パナソニック株式会社 | 半導体装置の製造方法 |
US9373595B2 (en) | 2011-09-16 | 2016-06-21 | Panasonic Intellectual Property Management Co., Ltd. | Mounting structure and manufacturing method for same |
US8497579B1 (en) * | 2012-02-16 | 2013-07-30 | Chipbond Technology Corporation | Semiconductor packaging method and structure thereof |
CN102637747A (zh) * | 2012-04-05 | 2012-08-15 | 祁门县硅鼎电子元件厂 | 镀涂环保材料的双铜质电极整流管芯片及镀涂工艺 |
DE102013103081A1 (de) * | 2013-03-26 | 2014-10-02 | Osram Opto Semiconductors Gmbh | Verfahren zum Verbinden von Fügepartnern und Anordnung von Fügepartnern |
JP2015122445A (ja) * | 2013-12-24 | 2015-07-02 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
CN104282582B (zh) * | 2014-09-17 | 2017-02-01 | 中南大学 | 一种Ni‑P基板的封装方法 |
US10886250B2 (en) * | 2015-07-10 | 2021-01-05 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
TWI822659B (zh) | 2016-10-27 | 2023-11-21 | 美商艾德亞半導體科技有限責任公司 | 用於低溫接合的結構和方法 |
JP6621068B2 (ja) * | 2016-12-08 | 2019-12-18 | パナソニックIpマネジメント株式会社 | 実装構造体 |
CN116313834B (zh) * | 2023-05-24 | 2023-09-12 | 江西兆驰半导体有限公司 | 晶圆级封装方法及晶圆级封装结构 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040188503A1 (en) * | 2003-03-31 | 2004-09-30 | Fay Hua | Solders with surfactant-refined grain sizes, solder bumps made thereof, and methods of making same |
TWI243082B (en) * | 2001-04-18 | 2005-11-11 | Hitachi Ltd | Electronic device |
JP2007019360A (ja) * | 2005-07-11 | 2007-01-25 | Fuji Electric Holdings Co Ltd | 電子部品の実装方法 |
JP2007152418A (ja) * | 2005-12-08 | 2007-06-21 | Mitsui Mining & Smelting Co Ltd | 高温はんだおよびその製造方法 |
TW200828548A (en) * | 2006-10-05 | 2008-07-01 | Flipchip Int Llc | Wafer-level interconnect for high mechanical reliability applications |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5038996A (en) * | 1988-10-12 | 1991-08-13 | International Business Machines Corporation | Bonding of metallic surfaces |
CA2030865C (en) * | 1989-11-30 | 1993-01-12 | Kenichi Fuse | Method of forming a solder layer on pads of a circuit board and method of mounting an electronic part on a circuit board |
US5296649A (en) * | 1991-03-26 | 1994-03-22 | The Furukawa Electric Co., Ltd. | Solder-coated printed circuit board and method of manufacturing the same |
US5428249A (en) * | 1992-07-15 | 1995-06-27 | Canon Kabushiki Kaisha | Photovoltaic device with improved collector electrode |
JP4897133B2 (ja) * | 1999-12-09 | 2012-03-14 | ソニー株式会社 | 半導体発光素子、その製造方法および配設基板 |
TWI230104B (en) * | 2000-06-12 | 2005-04-01 | Hitachi Ltd | Electronic device |
AU2002216373A1 (en) * | 2000-12-21 | 2002-07-01 | Hitachi Ltd. | Solder foil and semiconductor device and electronic device |
TW508987B (en) * | 2001-07-27 | 2002-11-01 | Phoenix Prec Technology Corp | Method of forming electroplated solder on organic printed circuit board |
JP3597810B2 (ja) | 2001-10-10 | 2004-12-08 | 富士通株式会社 | はんだペーストおよび接続構造 |
TW558821B (en) * | 2002-05-29 | 2003-10-21 | Via Tech Inc | Under bump buffer metallurgy structure |
US6744142B2 (en) | 2002-06-19 | 2004-06-01 | National Central University | Flip chip interconnection structure and process of making the same |
JP2005051150A (ja) | 2003-07-31 | 2005-02-24 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP4882229B2 (ja) * | 2004-09-08 | 2012-02-22 | 株式会社デンソー | 半導体装置およびその製造方法 |
JP4254757B2 (ja) * | 2005-07-22 | 2009-04-15 | 富士通株式会社 | 導電材料及び導電性ペースト及び基板 |
US7749336B2 (en) * | 2005-08-30 | 2010-07-06 | Indium Corporation Of America | Technique for increasing the compliance of tin-indium solders |
JP2007234841A (ja) | 2006-02-28 | 2007-09-13 | Kyocera Corp | 配線基板、実装部品、電子装置、配線基板の製造方法および電子装置の製造方法 |
CN101432095B (zh) * | 2006-04-28 | 2013-01-16 | 株式会社电装 | 泡沫焊锡和电子器件 |
US8143722B2 (en) | 2006-10-05 | 2012-03-27 | Flipchip International, Llc | Wafer-level interconnect for high mechanical reliability applications |
JP2008135553A (ja) | 2006-11-28 | 2008-06-12 | Fujitsu Ltd | 基板積層方法及び基板が積層された半導体装置 |
-
2009
- 2009-07-16 JP JP2009167716A patent/JP5465942B2/ja not_active Expired - Fee Related
-
2010
- 2010-05-21 TW TW099116411A patent/TWI414049B/zh not_active IP Right Cessation
- 2010-06-13 CN CN201410264924.2A patent/CN104022092A/zh active Pending
- 2010-06-13 US US12/814,472 patent/US8633103B2/en active Active
- 2010-06-13 CN CN2010102060615A patent/CN101958298A/zh active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI243082B (en) * | 2001-04-18 | 2005-11-11 | Hitachi Ltd | Electronic device |
US20040188503A1 (en) * | 2003-03-31 | 2004-09-30 | Fay Hua | Solders with surfactant-refined grain sizes, solder bumps made thereof, and methods of making same |
JP2007019360A (ja) * | 2005-07-11 | 2007-01-25 | Fuji Electric Holdings Co Ltd | 電子部品の実装方法 |
JP2007152418A (ja) * | 2005-12-08 | 2007-06-21 | Mitsui Mining & Smelting Co Ltd | 高温はんだおよびその製造方法 |
TW200828548A (en) * | 2006-10-05 | 2008-07-01 | Flipchip Int Llc | Wafer-level interconnect for high mechanical reliability applications |
Also Published As
Publication number | Publication date |
---|---|
JP2011023574A (ja) | 2011-02-03 |
TW201104817A (en) | 2011-02-01 |
US8633103B2 (en) | 2014-01-21 |
CN101958298A (zh) | 2011-01-26 |
US20110012263A1 (en) | 2011-01-20 |
CN104022092A (zh) | 2014-09-03 |
JP5465942B2 (ja) | 2014-04-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI414049B (zh) | 半導體裝置之製造方法 | |
JP6013705B2 (ja) | 部分パット上にバンプを有するフリップチップ相互接続構造を形成する半導体デバイスおよびその方法 | |
US9337165B2 (en) | Method for manufacturing a fan-out WLP with package | |
TWI567864B (zh) | 在基板上形成高繞線密度互連位置的半導體裝置及方法 | |
US7242081B1 (en) | Stacked package structure | |
US8759972B2 (en) | Semiconductor device and method of forming composite bump-on-lead interconnection | |
JP5952523B2 (ja) | 半導体素子およびフリップチップ相互接続構造を形成する方法 | |
CN104637826B (zh) | 半导体装置的制造方法 | |
JP2012119649A (ja) | バンプオンリード相互接続を形成する半導体素子および方法 | |
US20080157353A1 (en) | Control of Standoff Height Between Packages with a Solder-Embedded Tape | |
KR102574011B1 (ko) | 반도체 소자의 실장 구조 및 반도체 소자와 기판의 조합 | |
US20100190294A1 (en) | Methods for controlling wafer and package warpage during assembly of very thin die | |
JP2009152253A (ja) | 半導体装置およびその製造方法 | |
JP5035134B2 (ja) | 電子部品実装装置及びその製造方法 | |
KR20120058118A (ko) | 적층 패키지의 제조 방법, 및 이에 의하여 제조된 적층 패키지의 실장 방법 | |
CN104218003A (zh) | 具有缓冲材料和加强层的半导体器件 | |
US20100167466A1 (en) | Semiconductor package substrate with metal bumps | |
JP6398499B2 (ja) | 電子装置及び電子装置の製造方法 | |
TW201225209A (en) | Semiconductor device and method of confining conductive bump material with solder mask patch | |
USRE44500E1 (en) | Semiconductor device and method of forming composite bump-on-lead interconnection | |
KR101053746B1 (ko) | 반도체 시스템 및 그 제조 방법 | |
JP2004259886A (ja) | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 | |
JP2012099693A (ja) | 半導体装置の製造方法 | |
JP2008071792A (ja) | 半導体装置の製造方法 | |
JP4963890B2 (ja) | 樹脂封止回路装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |