JP2012119649A - バンプオンリード相互接続を形成する半導体素子および方法 - Google Patents
バンプオンリード相互接続を形成する半導体素子および方法 Download PDFInfo
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- JP2012119649A JP2012119649A JP2011010289A JP2011010289A JP2012119649A JP 2012119649 A JP2012119649 A JP 2012119649A JP 2011010289 A JP2011010289 A JP 2011010289A JP 2011010289 A JP2011010289 A JP 2011010289A JP 2012119649 A JP2012119649 A JP 2012119649A
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- interconnect
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- semiconductor die
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Abstract
【解決手段】半導体ダイの表面上に形成された複数の複合バンプを有する、半導体ダイを提供するステップであって、前記複合バンプは、可融性部分および非可融性部分を有する、ステップと、基板を提供するステップと、エスケープルーティング密度を増加させるための平面図から、伝導性トレースと平行な縁を有する相互接続部位を伴って前記基板上に複数の伝導性トレースを形成するステップであって、前記複合バンプは、前記相互接続部位よりも幅広い、ステップと、前記可融性部分が前記相互接続部位の頂面および側面を覆うように、前記複合バンプの前記可融性部分を前記相互接続部位に接着するステップと、前記半導体ダイと基板との間で前記複合バンプの周囲に封入材を堆積させるステップとを含む、半導体素子を作製する方法。
【選択図】図4
Description
複数の相互接続構造が、基板上で半導体ダイと相互接続部位との間に形成される。相互接続構造は、相互接続部位に接着される。封入材が、半導体ダイと基板との間に堆積させられる。
(項目1)
半導体ダイの表面上に形成された複数の複合バンプを有する、半導体ダイを提供するステップであって、上記複合バンプは、可融性部分および非可融性部分を有する、ステップと、
基板を提供するステップと、
エスケープルーティング密度を増加させるための平面図から、伝導性トレースと平行な縁を有する相互接続部位を伴って上記基板上に複数の伝導性トレースを形成するステップであって、上記複合バンプは、上記相互接続部位よりも幅広い、ステップと、
上記可融性部分が上記相互接続部位の頂面および側面を覆うように、上記複合バンプの上記可融性部分を上記相互接続部位に接着するステップと、
上記半導体ダイと基板との間で上記複合バンプの周囲に封入材を堆積させるステップと
を含む、半導体素子を作製する方法。
(項目2)
上記複合バンプの上記非可融性部分は、金、銅、ニッケル、鉛はんだ、または鉛スズ合金を含む、上記項目のいずれかに記載の方法。
(項目3)
上記複合バンプの上記可融性部分は、スズ、無鉛合金、スズ銀合金、スズ・銀・銅合金、スズ・銀・インジウム合金、共晶はんだ、または銀、銅、あるいは鉛を伴う他のスズ合金を含む、上記項目のいずれかに記載の方法。
(項目4)
上記相互接続部位は、上記伝導性トレースの幅より1.2倍小さい幅を有する、上記項目のいずれかに記載の方法。
(項目5)
上記相互接続部位から離れた上記基板の領域上にマスキング層を形成するステップをさらに含む、上記項目のいずれかに記載の方法。
(項目6)
上記複合バンプは、先細である、上記項目のいずれかに記載の方法。
(項目7)
半導体ダイを提供するステップと、
基板を提供するステップと、
エスケープルーティング密度を増加させるための平面図から、伝導性トレースと平行な縁を有する相互接続部位を伴って上記基板上に複数の伝導性トレースを形成するステップと、
上記基板上で上記半導体ダイと上記相互接続部位との間に複数の相互接続構造を形成するステップと、
上記相互接続構造が上記相互接続部位の頂面および側面を覆うように、上記半導体ダイと基板との間に相互接続構造を形成するステップと、
上記相互接続構造が上記相互接続部位の頂面および側面を覆うように、上記相互接続構を上記相互接続部位に接着するステップと、
上記半導体ダイと基板との間に封入材を堆積させるステップと
を含む、半導体素子を作製する方法。
(項目8)
上記相互接続部位は、上記伝導性トレースの幅より1.2倍小さい幅を有する、上記項目のいずれかに記載の方法。
(項目9)
上記相互接続構造は、可融性部分と、非可融性部分とを含む、上記項目のいずれかに記載の方法。
(項目10)
上記相互接続構造の上記非可融性部分は、金、銅、ニッケル、鉛はんだ、または鉛スズ合金を含む、上記項目のいずれかに記載の方法。
(項目11)
上記相互接続構造の上記可融性部分は、スズ、無鉛合金、スズ銀合金、スズ・銀・銅合金、スズ・銀・インジウム合金、共晶はんだ、または銀、銅、あるいは鉛を伴う他のスズ合金を含む、上記項目のいずれかに記載の方法。
(項目12)
上記相互接続構造は、伝導柱と、上記伝導柱上に形成されるバンプとを含む、上記項目のいずれかに記載の方法。
(項目13)
上記相互接続構造は、バンプを含む、上記項目のいずれかに記載の方法。
(項目14)
半導体ダイを提供するステップと、
基板を提供するステップと、
エスケープルーティング密度を増加させるための平面図から、伝導性トレースと平行な縁を有する相互接続部位を伴って上記基板上に複数の伝導性トレースを形成するステップと、
上記基板上で上記半導体ダイと上記相互接続部位との間に複数の相互接続構造を形成するステップと、
上記相互接続構造が上記相互接続部位の頂面および側面を覆うように、上記相互接続構を上記相互接続部位に接着するステップと
を含む、半導体素子を作製する方法。
(項目15)
上記相互接続部位は、上記伝導性トレースの幅より1.2倍小さい幅を有する、上記項目のいずれかに記載の方法。
(項目16)
上記半導体ダイと基板との間に封入材を堆積させるステップをさらに含む、上記項目のいずれかに記載の方法。
(項目17)
上記相互接続構造は、可融性部分と、非可融性部分とを含む、上記項目のいずれかに記載の方法。
(項目18)
上記相互接続構造の上記非可融性部分は、金、銅、ニッケル、鉛はんだ、または鉛スズ合金を含む、上記項目のいずれかに記載の方法。
(項目19)
上記相互接続構造の上記可融性部分は、スズ、無鉛合金、スズ銀合金、スズ・銀・銅合金、スズ・銀・インジウム合金、共晶はんだ、または銀、銅、あるいは鉛を伴う他のスズ合金を含む、上記項目のいずれかに記載の方法。
(項目20)
上記相互接続構造は、伝導柱と、上記伝導柱上に形成されるバンプとを含む、上記項目のいずれかに記載の方法。
(項目21)
半導体ダイと、
基板と、
エスケープルーティング密度を増加させるための平面図から、伝導性トレースと平行な縁を有する相互接続部位を伴って上記基板上に形成される、複数の伝導性トレースと、
上記基板上で上記半導体ダイと相互接続部位との間に形成される、複数の相互接続構造であって、上記相互接続部位に接着される、相互接続構造と、
上記半導体ダイと基板との間に堆積させられる、封入材と
を備える、半導体素子。
(項目22)
上記相互接続構造の上記非可融性部分は、金、銅、ニッケル、鉛はんだ、または鉛スズ合金を含む、上記項目のいずれかに記載の半導体素子。
(項目23)
上記相互接続構造の上記可融性部分は、スズ、無鉛合金、スズ銀合金、スズ・銀・銅合金、スズ・銀・インジウム合金、共晶はんだ、または銀、銅、あるいは鉛を伴う他のスズ合金を含む、上記項目のいずれかに記載の半導体素子。
(項目24)
上記相互接続部位は、上記伝導性トレースの幅より1.2倍小さい幅を有する、上記項目のいずれかに記載の半導体素子。
(項目25)
上記相互接続構造は、伝導柱と、上記伝導柱上に形成されるバンプとを含む、上記項目のいずれかに記載の半導体素子。
半導体素子は、半導体ダイの表面上に形成された複数の複合バンプを伴う半導体ダイを有する。複合バンプは、伝導柱および伝導柱上に形成されるバンプ等の、可融性部分および非可融性部分を有することができる。複合バンプはまた、先細にすることもできる。伝導性トレースは、エスケープルーティング密度を増加させるための平面図から、伝導性トレースと平行な縁を有する相互接続部位を伴って基板上に形成される。相互接続部位は、伝導性トレースの幅より1.2倍小さい幅を有することができる。複合バンプは、相互接続部位よりも幅広い。複合バンプの可融性部分は、可融性部分が相互接続部位の頂面および側面を覆うように、相互接続部位に接着される。封入材が、半導体ダイと基板との間で複合バンプの周囲に堆積させられる。
バンプ材料234の柔軟性により、バンプ材料は、伝導性トレース256の頂面および側面の周囲で変形または押出し、BOLと呼ばれる。具体的には、圧力の印加は、約200グラムの垂直荷重と同等の力Fの下で、約25μmより大きい塑性変形をバンプ材料234に受けさせ、図17bに示されるように、伝導性トレースの頂面および側面を覆わせる。バンプ材料234はまた、バンプ材料を伝導性トレースと物理的接触させ、次いで、リフロー温度下でバンプ材料をリフローすることによって、伝導性トレース256に冶金接続することもできる。
伝導性ビア310は、図21aに示されるように、開口部312および伝導性側壁314を伴って伝導性トレース306を通して形成される。伝導性トレース306は、ルーティング密度を増加させるための、図6−15で説明されるようなエスケープトレースおよび相互接続部位と同様である。
マスキングパッチ402は、マスキング層392と同じ材料であり、同じ処理ステップ中に塗布することができるか、または異なる処理ステップ中に異なる材料となり得る。マスキングパッチ402は、集積バンプパッド398のアレイ内のトレースまたはパッドの部分の選択的酸化、めっき、または他の処理によって形成することができる。マスキングパッチ402は、集積バンプパッド398にバンプ材料流動を閉じ込め、隣接構造への伝導性バンプ材料の浸出を防止する。
Claims (25)
- 半導体ダイの表面上に形成された複数の複合バンプを有する、半導体ダイを提供するステップであって、前記複合バンプは、可融性部分および非可融性部分を有する、ステップと、
基板を提供するステップと、
エスケープルーティング密度を増加させるための平面図から、伝導性トレースと平行な縁を有する相互接続部位を伴って前記基板上に複数の伝導性トレースを形成するステップであって、前記複合バンプは、前記相互接続部位よりも幅広い、ステップと、
前記可融性部分が前記相互接続部位の頂面および側面を覆うように、前記複合バンプの前記可融性部分を前記相互接続部位に接着するステップと、
前記半導体ダイと基板との間で前記複合バンプの周囲に封入材を堆積させるステップと
を含む、半導体素子を作製する方法。 - 前記複合バンプの前記非可融性部分は、金、銅、ニッケル、鉛はんだ、または鉛スズ合金を含む、請求項1に記載の方法。
- 前記複合バンプの前記可融性部分は、スズ、無鉛合金、スズ銀合金、スズ・銀・銅合金、スズ・銀・インジウム合金、共晶はんだ、または銀、銅、あるいは鉛を伴う他のスズ合金を含む、請求項1に記載の方法。
- 前記相互接続部位は、前記伝導性トレースの幅より1.2倍小さい幅を有する、請求項1に記載の方法。
- 前記相互接続部位から離れた前記基板の領域上にマスキング層を形成するステップをさらに含む、請求項1に記載の方法。
- 前記複合バンプは、先細である、請求項1に記載の方法。
- 半導体ダイを提供するステップと、
基板を提供するステップと、
エスケープルーティング密度を増加させるための平面図から、伝導性トレースと平行な縁を有する相互接続部位を伴って前記基板上に複数の伝導性トレースを形成するステップと、
前記基板上で前記半導体ダイと前記相互接続部位との間に複数の相互接続構造を形成するステップと、
前記相互接続構造が前記相互接続部位の頂面および側面を覆うように、前記半導体ダイと基板との間に相互接続構造を形成するステップと、
前記相互接続構造が前記相互接続部位の頂面および側面を覆うように、前記相互接続構を前記相互接続部位に接着するステップと、
前記半導体ダイと基板との間に封入材を堆積させるステップと
を含む、半導体素子を作製する方法。 - 前記相互接続部位は、前記伝導性トレースの幅より1.2倍小さい幅を有する、請求項7に記載の方法。
- 前記相互接続構造は、可融性部分と、非可融性部分とを含む、請求項7に記載の方法。
- 前記相互接続構造の前記非可融性部分は、金、銅、ニッケル、鉛はんだ、または鉛スズ合金を含む、請求項8に記載の方法。
- 前記相互接続構造の前記可融性部分は、スズ、無鉛合金、スズ銀合金、スズ・銀・銅合金、スズ・銀・インジウム合金、共晶はんだ、または銀、銅、あるいは鉛を伴う他のスズ合金を含む、請求項7に記載の方法。
- 前記相互接続構造は、伝導柱と、前記伝導柱上に形成されるバンプとを含む、請求項7に記載の方法。
- 前記相互接続構造は、バンプを含む、請求項7に記載の方法。
- 半導体ダイを提供するステップと、
基板を提供するステップと、
エスケープルーティング密度を増加させるための平面図から、伝導性トレースと平行な縁を有する相互接続部位を伴って前記基板上に複数の伝導性トレースを形成するステップと、
前記基板上で前記半導体ダイと前記相互接続部位との間に複数の相互接続構造を形成するステップと、
前記相互接続構造が前記相互接続部位の頂面および側面を覆うように、前記相互接続構を前記相互接続部位に接着するステップと
を含む、半導体素子を作製する方法。 - 前記相互接続部位は、前記伝導性トレースの幅より1.2倍小さい幅を有する、請求項14に記載の方法。
- 前記半導体ダイと基板との間に封入材を堆積させるステップをさらに含む、請求項14に記載の方法。
- 前記相互接続構造は、可融性部分と、非可融性部分とを含む、請求項14に記載の方法。
- 前記相互接続構造の前記非可融性部分は、金、銅、ニッケル、鉛はんだ、または鉛スズ合金を含む、請求項17に記載の方法。
- 前記相互接続構造の前記可融性部分は、スズ、無鉛合金、スズ銀合金、スズ・銀・銅合金、スズ・銀・インジウム合金、共晶はんだ、または銀、銅、あるいは鉛を伴う他のスズ合金を含む、請求項17に記載の方法。
- 前記相互接続構造は、伝導柱と、前記伝導柱上に形成されるバンプとを含む、請求項14に記載の方法。
- 半導体ダイと、
基板と、
エスケープルーティング密度を増加させるための平面図から、伝導性トレースと平行な縁を有する相互接続部位を伴って前記基板上に形成される、複数の伝導性トレースと、
前記基板上で前記半導体ダイと相互接続部位との間に形成される、複数の相互接続構造であって、前記相互接続部位に接着される、相互接続構造と、
前記半導体ダイと基板との間に堆積させられる、封入材と
を備える、半導体素子。 - 前記相互接続構造の前記非可融性部分は、金、銅、ニッケル、鉛はんだ、または鉛スズ合金を含む、請求項21に記載の半導体素子。
- 前記相互接続構造の前記可融性部分は、スズ、無鉛合金、スズ銀合金、スズ・銀・銅合金、スズ・銀・インジウム合金、共晶はんだ、または銀、銅、あるいは鉛を伴う他のスズ合金を含む、請求項21に記載の半導体素子。
- 前記相互接続部位は、前記伝導性トレースの幅より1.2倍小さい幅を有する、請求項21に記載の半導体素子。
- 前記相互接続構造は、伝導柱と、前記伝導柱上に形成されるバンプとを含む、請求項21に記載の半導体素子。
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US8574959B2 (en) | 2013-11-05 |
CN102487020A (zh) | 2012-06-06 |
TWI518812B (zh) | 2016-01-21 |
CN102487020B (zh) | 2016-08-31 |
TW201232681A (en) | 2012-08-01 |
US20110074024A1 (en) | 2011-03-31 |
US20150311172A1 (en) | 2015-10-29 |
US20140008792A1 (en) | 2014-01-09 |
US20130277826A9 (en) | 2013-10-24 |
US9064858B2 (en) | 2015-06-23 |
KR101807311B1 (ko) | 2017-12-08 |
KR20120061713A (ko) | 2012-06-13 |
US9385101B2 (en) | 2016-07-05 |
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