WO2003071842A1 - Method of mounting a semiconductor die on a substrate without using a solder mask - Google Patents

Method of mounting a semiconductor die on a substrate without using a solder mask Download PDF

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Publication number
WO2003071842A1
WO2003071842A1 PCT/US2001/049443 US0149443W WO03071842A1 WO 2003071842 A1 WO2003071842 A1 WO 2003071842A1 US 0149443 W US0149443 W US 0149443W WO 03071842 A1 WO03071842 A1 WO 03071842A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
surface area
pad
trace
solderability
Prior art date
Application number
PCT/US2001/049443
Other languages
French (fr)
Inventor
Burton J. Carpenter
Nhat D. Vo
Christopher T. Clark
William M. Stone
Trent S. Uehling
David B. Clegg
Original Assignee
Motorola, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola, Inc. filed Critical Motorola, Inc.
Priority to PCT/US2001/049443 priority Critical patent/WO2003071842A1/en
Priority to AU2002234063A priority patent/AU2002234063A1/en
Publication of WO2003071842A1 publication Critical patent/WO2003071842A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/05001—Internal layers
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
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    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2924/01029—Copper [Cu]
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    • H01L2924/01079—Gold [Au]
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    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/0949—Pad close to a hole, not surrounding the hole
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2081—Compound repelling a metal, e.g. solder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0315—Oxidising metal

Definitions

  • This invention relates generally to semiconductor devices, and more particularly, to an apparatus and method for contacting a semiconductor die to a substrate.
  • bumps are fabricated on pad areas of a semiconductor die in order to interconnect the die to a package or to a substrate.
  • the substrate is used to interface the electrical circuits of the semiconductor die to a printed circuit board.
  • FIG. 1 illustrates a prior art semiconductor die 10 with a solder bump 16 and a substrate 20 prior to making an electrical connection.
  • solder bump 16 there are various ways to form solder bump 16 on semiconductor die 10.
  • a pad 12 is first formed on die 10.
  • a copper stud 14 may then be formed on pad 12 for supporting a solder bump 16.
  • a corresponding pad location is provided on substrate 20.
  • a copper trace 22 is formed on substrate 20 that will cross the pad location.
  • a pad area is defined.
  • the pad may be prepared by forming a nickel layer 26 on the copper trace 22.
  • a relatively thin gold layer 24 is then formed on the nickel layer 26.
  • a soldermask 28 is formed around the pad area to contain the solder when it is melted so that the liquid solder stays on the pad area and does not wick along the copper trace. Also, the soldermask controls the shape of the bump that helps to maintain a minimum standoff height between the semiconductor die 10 and the substrate 20.
  • FIG. 2 illustrates the semiconductor die 10 and the pad area of substrate 20 of FIG. 1 after making the electrical connection.
  • semiconductor die 10 is positioned so that when solder bump 16 is melted, or reflowed, the melted solder will wet the gold layer 24 to form an electrical connection.
  • the shape of the soldermask, the volume of the solder bump, the size of the pad, etc. are important considerations for making a reliable electrical connection that has the minimum standoff height Note that gold layer 24 has been diffused into the solder bump and therefore is not shown in FIG. 2.
  • An integrated circuit manufactured using "flip chip” technology may have hundreds of these solder bumps.
  • soldermask opening can be reduced in size is limited by the ability of the soldermask material and process used to resolve at the necessary pad opening size.
  • FIG. 1 illustrates a prior art semiconductor die with a solder bump and substrate pad area prior to making an electrical connection.
  • FIG. 2 illustrates the semiconductor die and substrate pad area of FIG. 1 after making the electrical connection.
  • FIG. 3 illustrates a semiconductor die with a solder bump and substrate pad area prior to making an electrical connection in accordance with the present invention.
  • FIG. 4 illustrates the semiconductor die and substrate of FIG. 3 after the electrical connection is made.
  • FIG. 5 illustrates a top-down view of a portion of a substrate in accordance with the present invention.
  • FIG. 6 illustrates a cross-sectional view of the portion of the substrate of FIG. 5.
  • the present invention provides a solder bump structure and a method for forming a bump structure that includes a conductive trace formed on a substrate having a first surface area, the first surface area being of a first solderability.
  • a conductive pad is formed on the first surface area of the conductive trace.
  • the conductive pad has a second surface area, the second surface area being of a second solderability.
  • the second solderability is greater than the first solderability. Because of the different solderabilities, the solder bump on the semiconductor die can be reflowed and connected to the second surface area without using an additional layer to contain the solder on the second surface area.
  • FIG. 3 illustrates a semiconductor die 40 with a eutectic solder bump 46 prior to making an electrical connection with a pad area 56 on substrate 50 in accordance with the present invention.
  • a pad 42 is formed on semiconductor die 40.
  • a copper stud 44 may then be formed on pad 42 for supporting a solder bump 46.
  • the solder bump 46 has a diameter of approximately 50 microns.
  • the method used to form solder bump 46 is not important for purposes of describing the present invention and will not be described further.
  • a dielectric portion of substrate 50 is a conventional substrate formed from an organic material.
  • substrate 50 may formed from an inorganic material, such as for example, silicon.
  • a pad location is provided on substrate 50 corresponding to the placement of solder bump 46.
  • a copper trace 52 is formed on substrate 50. The copper trace is routed on substrate 50 to transmit electrical signals between the integrated circuits on semiconductor die 40 and a printed circuit board (not shown). In some embodiments, the copper trace may actually be a via formed under the pad area. At a designated location on copper trace 52, the pad area is defined for contacting and electrically connecting with solder bump 46.
  • the pad area is prepared by first forming a nickel layer 54 on the copper trace 52.
  • a gold layer 56 is then formed on the nickel layer 54. Note that in the illustrated embodiment gold is the material used for layer 56. However, in other embodiments, the gold may be replaced with another oxide resistant wettable metal.
  • the layer 56 may be a mask that is removed when the oxidation of copper trace 52 is complete.
  • the gold of gold layer 56 has a greater "solderability" than the copper of copper trace 52.
  • solderability sometimes known as "wettability”
  • the solderability is defined as the relative ease in which the metal can be soldered.
  • gold is known to be easier to solder than copper, therefore, gold has a greater solderability than copper when using the lead-tin solders common in semiconductor manufacturing.
  • copper is known to more easily form oxides on its surface than gold. The oxides further decrease the solderability of copper, thus requiring the use of a solder flux to help form reliable solder joints.
  • the need for a soldermask is eliminated by using conductive layers that have different solderabilities.
  • the presence of an oxide layer on the surface of, for example, copper trace 52 further increases the difference in solderability between the gold and copper.
  • the oxide layer may simply be a native oxide or an oxide layer deposited or grown on the surface of copper trace 52. Therefore, the solder is less likely to wet the surface of the copper having the oxide, thus effectively forming a dam that inhibits the solder from wicking along trace 52.
  • solder pads By eliminating the need to use a soldermask, smaller solder pads can be used. Also, the smaller pads can be formed on a smaller pitch. In addition, a smaller pitch allows more densely routed traces across the substrate.
  • the solder bumps are about 50 microns in diameter, and a pitch between two adjacent traces is about 100 microns, where "pitch" is defined as the distance between the centers of two substantially parallel traces. Also, eliminating the soldermask layer helps maintain a greater standoff height (labeled "A" in FIG. 4) between the semiconductor die 40 and substrate 50 as compared to the prior art of FIG. 1 and FIG. 2.
  • FIG. 4 illustrates the semiconductor die 40 and substrate 50 of FIG. 3 after the solder bump is melted, or reflowed, and electrical connection is made between semiconductor die 40 and substrate 50.
  • gold pad 56 is diffused into the solder bump and disappears as a separate, distinct layer.
  • FIG. 4 illustrates that the difference in solderability between the gold and the native oxides on the copper inhibits solder wicking down copper trace 52, thus providing a reflowed solder bump with adequate standoff height labeled "A".
  • FIG. 5 illustrates a top-down view of a portion of substrate 50 in accordance with one embodiment of the present invention.
  • the gold pad 56 is formed on one end of copper trace 52.
  • pad 56 has a generally rectangular shape and a surface area partly defined by the width of copper trace 52. In other embodiments, the shape of pad 56 can be different. Also, for illustration purposes, only one trace 52 is shown, in other embodiments, many traces may be routed substantially parallel to trace 52.
  • another gold pad 62 connected to a via 64. Via 64 is used to provide electrical connection from one metal layer of substrate 50 to another metal layer of substrate 50. Substrate 50 may have many metal layers.
  • Gold pad 62 is formed in a manner similar to gold pad 56.
  • a soldermask layer 60 may be formed over substrate 50 in an area around the die attach area. Copper trace 52 is shown continuing under soldermask layer 60 as dashed lines.
  • an epoxy is used to physically attach the die to the substrate (not shown). The epoxy will cover the bump structures and provide strength and enhance reliability of the connections. When the epoxy is applied to substrate 50, it will cover substrate 50 around the die up to the edge of soldermask layer 60.
  • FIG. 6 illustrates a cross-sectional view of the portion of the substrate of FIG. 5 on a line along the center of copper trace 52.
  • a semiconductor die (not shown) will be positioned over substrate 50 so that the solder bumps on the die will align with the corresponding pad locations on substrate 50. Depending on the size of the die and the location of the bumps on the die, an edge of the die will be somewhere between pad 56 and soldermask layer 60.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

A pad area of a substrate (50) includes a conductive trace (52) formed on the substrate (50) having a first surface area, the first surface area being of a first solderability. A conductive pad (56) is formed on the first surface area of the conductive trace (52). The conductive pad (56) has a second surface area, the second surface area being of a second solderability. The second solderability is greater than the first solderability. Because of the different solderabilities, a solder bump (46) on the semiconductor die (40) can be reflowed and connected to the second surface area without using a soldermask (28) to contain the melted solder on the second surface area.

Description

01 49443
METHOD OF MOUNTING A SEMICONDUCTOR DIE ON A SUBSTRATE WITHOUT USING A SOLDER MASK
Field of the Invention
This invention relates generally to semiconductor devices, and more particularly, to an apparatus and method for contacting a semiconductor die to a substrate.
Background of the Invention
In some semiconductor manufacturing processes, such as for example, "flip chip", bumps are fabricated on pad areas of a semiconductor die in order to interconnect the die to a package or to a substrate. The substrate is used to interface the electrical circuits of the semiconductor die to a printed circuit board.
FIG. 1 illustrates a prior art semiconductor die 10 with a solder bump 16 and a substrate 20 prior to making an electrical connection. There are various ways to form solder bump 16 on semiconductor die 10. In general, a pad 12 is first formed on die 10. A copper stud 14 may then be formed on pad 12 for supporting a solder bump 16. A corresponding pad location is provided on substrate 20. A copper trace 22 is formed on substrate 20 that will cross the pad location. At the designated location on copper trace 22, a pad area is defined. The pad may be prepared by forming a nickel layer 26 on the copper trace 22. A relatively thin gold layer 24 is then formed on the nickel layer 26. A soldermask 28 is formed around the pad area to contain the solder when it is melted so that the liquid solder stays on the pad area and does not wick along the copper trace. Also, the soldermask controls the shape of the bump that helps to maintain a minimum standoff height between the semiconductor die 10 and the substrate 20.
FIG. 2 illustrates the semiconductor die 10 and the pad area of substrate 20 of FIG. 1 after making the electrical connection. To electrically connect semiconductor die 10 to substrate 20, semiconductor die 10 is positioned so that when solder bump 16 is melted, or reflowed, the melted solder will wet the gold layer 24 to form an electrical connection. The shape of the soldermask, the volume of the solder bump, the size of the pad, etc. are important considerations for making a reliable electrical connection that has the minimum standoff height Note that gold layer 24 has been diffused into the solder bump and therefore is not shown in FIG. 2. An integrated circuit manufactured using "flip chip" technology may have hundreds of these solder bumps. As the number of bumps on the integrated circuit increases, it is desirable from a cost and die size perspective for the solder connections to be smaller and formed closer together. However, the amount a soldermask opening can be reduced in size is limited by the ability of the soldermask material and process used to resolve at the necessary pad opening size.
Therefore, a need exists to create solder bump connections in semiconductor manufacturing that are reduced in size, pitch, and have good reliability.
Brief Description of the Drawings
The present invention is illustrated by way of example and not limited in the accompanying figures, in which like references indicate similar elements, and in which:
FIG. 1 illustrates a prior art semiconductor die with a solder bump and substrate pad area prior to making an electrical connection.
FIG. 2 illustrates the semiconductor die and substrate pad area of FIG. 1 after making the electrical connection. FIG. 3 illustrates a semiconductor die with a solder bump and substrate pad area prior to making an electrical connection in accordance with the present invention.
FIG. 4 illustrates the semiconductor die and substrate of FIG. 3 after the electrical connection is made. FIG. 5 illustrates a top-down view of a portion of a substrate in accordance with the present invention.
FIG. 6 illustrates a cross-sectional view of the portion of the substrate of FIG. 5. Description of a Preferred Embodiment
Generally, the present invention provides a solder bump structure and a method for forming a bump structure that includes a conductive trace formed on a substrate having a first surface area, the first surface area being of a first solderability. A conductive pad is formed on the first surface area of the conductive trace. The conductive pad has a second surface area, the second surface area being of a second solderability. The second solderability is greater than the first solderability. Because of the different solderabilities, the solder bump on the semiconductor die can be reflowed and connected to the second surface area without using an additional layer to contain the solder on the second surface area.
FIG. 3 illustrates a semiconductor die 40 with a eutectic solder bump 46 prior to making an electrical connection with a pad area 56 on substrate 50 in accordance with the present invention. A pad 42 is formed on semiconductor die 40. A copper stud 44 may then be formed on pad 42 for supporting a solder bump 46. In the illustrated embodiment, the solder bump 46 has a diameter of approximately 50 microns. There are various techniques for forming the solder bumps on semiconductor die 40, such as for example, the C4 (Controlled Collapse Chip Connection) bump process, or the E3 (Extended Eutectic Evaporative) bump process, or the like. The method used to form solder bump 46 is not important for purposes of describing the present invention and will not be described further.
In the illustrated embodiment, a dielectric portion of substrate 50 is a conventional substrate formed from an organic material. In other embodiments, substrate 50 may formed from an inorganic material, such as for example, silicon. A pad location is provided on substrate 50 corresponding to the placement of solder bump 46. A copper trace 52 is formed on substrate 50. The copper trace is routed on substrate 50 to transmit electrical signals between the integrated circuits on semiconductor die 40 and a printed circuit board (not shown). In some embodiments, the copper trace may actually be a via formed under the pad area. At a designated location on copper trace 52, the pad area is defined for contacting and electrically connecting with solder bump 46. The pad area is prepared by first forming a nickel layer 54 on the copper trace 52. A gold layer 56 is then formed on the nickel layer 54. Note that in the illustrated embodiment gold is the material used for layer 56. However, in other embodiments, the gold may be replaced with another oxide resistant wettable metal. In addition, the layer 56 may be a mask that is removed when the oxidation of copper trace 52 is complete.
The gold of gold layer 56 has a greater "solderability" than the copper of copper trace 52. For purposes of describing the present invention, the solderability, sometimes known as "wettability", of a metal is defined as the relative ease in which the metal can be soldered. Generally, gold is known to be easier to solder than copper, therefore, gold has a greater solderability than copper when using the lead-tin solders common in semiconductor manufacturing. In addition, copper is known to more easily form oxides on its surface than gold. The oxides further decrease the solderability of copper, thus requiring the use of a solder flux to help form reliable solder joints. In the illustrated embodiment, the need for a soldermask is eliminated by using conductive layers that have different solderabilities. In addition, the presence of an oxide layer on the surface of, for example, copper trace 52 further increases the difference in solderability between the gold and copper. The oxide layer may simply be a native oxide or an oxide layer deposited or grown on the surface of copper trace 52. Therefore, the solder is less likely to wet the surface of the copper having the oxide, thus effectively forming a dam that inhibits the solder from wicking along trace 52.
By eliminating the need to use a soldermask, smaller solder pads can be used. Also, the smaller pads can be formed on a smaller pitch. In addition, a smaller pitch allows more densely routed traces across the substrate. In the illustrated embodiment, the solder bumps are about 50 microns in diameter, and a pitch between two adjacent traces is about 100 microns, where "pitch" is defined as the distance between the centers of two substantially parallel traces. Also, eliminating the soldermask layer helps maintain a greater standoff height (labeled "A" in FIG. 4) between the semiconductor die 40 and substrate 50 as compared to the prior art of FIG. 1 and FIG. 2.
FIG. 4 illustrates the semiconductor die 40 and substrate 50 of FIG. 3 after the solder bump is melted, or reflowed, and electrical connection is made between semiconductor die 40 and substrate 50. During the reflow process, gold pad 56 is diffused into the solder bump and disappears as a separate, distinct layer. FIG. 4 illustrates that the difference in solderability between the gold and the native oxides on the copper inhibits solder wicking down copper trace 52, thus providing a reflowed solder bump with adequate standoff height labeled "A".
FIG. 5 illustrates a top-down view of a portion of substrate 50 in accordance with one embodiment of the present invention. The gold pad 56 is formed on one end of copper trace 52. In the illustrated embodiment, pad 56 has a generally rectangular shape and a surface area partly defined by the width of copper trace 52. In other embodiments, the shape of pad 56 can be different. Also, for illustration purposes, only one trace 52 is shown, in other embodiments, many traces may be routed substantially parallel to trace 52. Also illustrated in FIG. 5 is another gold pad 62 connected to a via 64. Via 64 is used to provide electrical connection from one metal layer of substrate 50 to another metal layer of substrate 50. Substrate 50 may have many metal layers. Gold pad 62 is formed in a manner similar to gold pad 56. In some embodiments, a soldermask layer 60 may be formed over substrate 50 in an area around the die attach area. Copper trace 52 is shown continuing under soldermask layer 60 as dashed lines. After the semiconductor die is attached to the substrate, an epoxy is used to physically attach the die to the substrate (not shown). The epoxy will cover the bump structures and provide strength and enhance reliability of the connections. When the epoxy is applied to substrate 50, it will cover substrate 50 around the die up to the edge of soldermask layer 60.
FIG. 6 illustrates a cross-sectional view of the portion of the substrate of FIG. 5 on a line along the center of copper trace 52. A semiconductor die (not shown) will be positioned over substrate 50 so that the solder bumps on the die will align with the corresponding pad locations on substrate 50. Depending on the size of the die and the location of the bumps on the die, an edge of the die will be somewhere between pad 56 and soldermask layer 60.
While the invention has been described in the context of a preferred embodiment, it will be apparent to those skilled in the art that the present invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above. For example, other metals that have different solderabilities may be used to form the trace and the solder pad instead of copper and gold. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true scope of the invention.

Claims

ClaimsWhat is claimed is:
1. An apparatus for interconnecting a semiconductor die to a printed circuit board, comprising: a substrate; a conductive trace formed on the substrate having a first surface area, the first surface area being of a first solderability; a conductive pad formed on the first surface area of the conductive trace having a second surface area, the second surface area being of a second solderability, the second solderability is greater than the first solderability; and wherein a solder bump on the semiconductor die can be connected to the second surface area without using another material to contain the solder on the second surface area.
2. The apparatus of claim 1 , wherein the conductive trace comprises copper.
3. The apparatus of claim 1 , wherein the conductive pad has a layer that comprises gold.
4. The apparatus of claim 3, wherein the conductive pad has a layer that comprises nickel between the layer comprising gold and the conductive trace.
5. The apparatus of claim 1 , wherein a native oxide of the first surface area adjacent to the second surface area increases a differential solderability between the first and second surface areas to inhibit the solder from flowing over the first surface area. A method for electrically connecting a semiconductor die to a substrate, comprising the steps of: forming a conductive trace on the substrate, the conductive trace comprising a first metal; defining a surface area of the conductive trace on which to form a conductive pad; and forming the conductive pad comprising a second metal, the second metal having greater solderability than the first metal; wherein a solder bump for electrically connecting the semiconductor die to the substrate, when melted, will not flow onto the first metal.
The method of claim 6 wherein the conductive trace is formed of copper.
The method of claim 6 wherein the step of forming the conductive trace includes forming the conductive trace having a surface comprising a native oxide and the step of forming the conductive pad includes forming the conductive pad of gold.
A substrate for supporting a semiconductor die, comprising: a copper trace for transmitting an electrical signal to or from the semiconductor die; a gold pad formed on the copper trace, the gold pad for being a solderable connection to the semiconductor; and wherein a surface of the copper trace has a relatively lower solderability than a surface of the gold pad, thereby allowing a solder bump to be melted and reflowed without the use of a soldermask to contain the solder while the solder is in a liquid state. The substrate of claim 9, wherein the copper trace includes a native oxide surface layer that increases a differential solderability between the gold pad and the copper trace.
PCT/US2001/049443 2001-12-26 2001-12-26 Method of mounting a semiconductor die on a substrate without using a solder mask WO2003071842A1 (en)

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US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US9064858B2 (en) 2003-11-10 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
USRE44500E1 (en) 2003-11-10 2013-09-17 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
USRE44524E1 (en) 2003-11-10 2013-10-08 Stats Chippac, Ltd. Bump-on-lead flip chip interconnection
US8558378B2 (en) * 2003-11-10 2013-10-15 Stats Chippac, Ltd. Bump-on-lead flip chip interconnection
USRE44562E1 (en) 2003-11-10 2013-10-29 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
USRE44579E1 (en) 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
USRE44608E1 (en) 2003-11-10 2013-11-26 Stats Chippac, Ltd. Solder joint flip chip interconnection
USRE44761E1 (en) 2003-11-10 2014-02-11 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US20120211887A1 (en) * 2003-11-10 2012-08-23 Stats Chippac, Ltd. Bump-on-Lead Flip Chip Interconnection
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
USRE44355E1 (en) 2003-11-10 2013-07-09 Stats Chippac, Ltd. Method of forming a bump-on-lead flip chip interconnection having higher escape routing density
USRE44431E1 (en) 2003-11-10 2013-08-13 Stats Chippac, Ltd. Bump-on-lead flip chip interconnection
US9922915B2 (en) 2003-11-10 2018-03-20 STATS ChipPAC Pte. Ltd. Bump-on-lead flip chip interconnection
US9219045B2 (en) 2003-11-10 2015-12-22 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US9373573B2 (en) 2003-11-10 2016-06-21 STATS ChipPAC Pte. Ltd. Solder joint flip chip interconnection
US9379084B2 (en) 2003-11-10 2016-06-28 STATS ChipPAC Pte. Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US9385101B2 (en) 2003-11-10 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US9773685B2 (en) 2003-11-10 2017-09-26 STATS ChipPAC Pte. Ltd. Solder joint flip chip interconnection having relief structure
US9865556B2 (en) 2003-11-10 2018-01-09 STATS ChipPAC Pte Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US9899286B2 (en) 2003-11-10 2018-02-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US9159665B2 (en) 2005-03-25 2015-10-13 Stats Chippac, Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
US10580749B2 (en) 2005-03-25 2020-03-03 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming high routing density interconnect sites on substrate
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate

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