USRE44579E1 - Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask - Google Patents
Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask Download PDFInfo
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- USRE44579E1 USRE44579E1 US13756679 US201313756679A USRE44579E US RE44579 E1 USRE44579 E1 US RE44579E1 US 13756679 US13756679 US 13756679 US 201313756679 A US201313756679 A US 201313756679A US RE44579 E USRE44579 E US RE44579E
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- bump
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- semiconductor
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
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- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
Description
The present non-provisional application is a reissue application of U.S. Pat. No. 8,026,128, which claims the benefit of priority of U.S. Provisional Application Ser. No. 61/141,791, filed Dec. 31, 2008. The present nonprovisional application, and further is a continuation-in-part of U.S. application Ser. No. 12/062,293, now U.S. Pat. No. 7,700,407, filed Apr. 3, 2008, and which is a division of U.S. application Ser. No. 10/985,654, now U.S. Pat. No. 7,368,817, filed Nov. 10, 2004, entitled “Bump-on-Lead Flip Chip Interconnection” by Rajendra D. Pense Pendse, which claims the benefit of U.S. Provisional Application No. 60/533,918, filed Dec. 31, 2003, and U.S. Provisional Application No. 60/518,864, filed Nov. 10, 2003.
The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of providing self-confinement of conductive bump material during reflow without use of a solder mask.
Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size may be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
In typical design rules, the minimum escape pitch of trace line 20 is limited by the fact that SRO 16 must be at least as large as the base diameter (D) of interconnect 12 plus a solder mask registration tolerance (SRT). In addition, a minimum ligament (L) of solder mask material is needed between adjacent openings by virtue of the limits of the solder mask application process. More specifically, the minimum escape pitch is defined as P=D+2*SRT+L. In one embodiment, D is 100 micrometers (μm), SRT is 10 μm, and L is 60 μm, hence, the minimum escape pitch is 100+2*10+60=180 μm.
A need exists to minimize escape pitch of trace lines for higher routing density. Accordingly, in one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a semiconductor die having a die bump pad, providing a substrate having a trace line with substrate bump pad, depositing conductive bump material on the substrate bump pad or die bump pad, mounting the semiconductor die over the substrate so that the conductive bump material is disposed between the die bump pad and substrate bump pad, and reflowing the conductive bump material without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The conductive bump material is self-confined within a footprint of the die bump pad or substrate bump pad during reflow.
In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a first semiconductor structure having a first bump pad, providing a second semiconductor structure having a second bump pad, depositing conductive bump material between the first and second bump pads, and reflowing the conductive bump material without a solder mask around the first and second bump pads to form an interconnect. The conductive bump material is self-confined within the first and second bump pads during reflow.
In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of depositing conductive bump material over a first bump pad, and reflowing the conductive bump material without a solder mask. The conductive bump material is self-confined within the first bump pad during reflow.
In another embodiment, the present invention is a semiconductor device comprising a semiconductor die having a first bump pad and substrate having a second bump pad. An interconnect is formed between the first and second bump pads by reflowing conductive bump material without a solder mask. The conductive bump material is self-confined within the first and second bump pads.
The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.
Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, resistors, and transformers, create a relationship between voltage and current necessary to perform electrical circuit functions.
Passive and active components are formed over the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the electrical conductivity of semiconductor material in active devices, transforming the semiconductor material into an insulator, conductor, or dynamically changing the semiconductor material conductivity in response to an electric field or base current. Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of the electric field or base current.
Active and passive components are formed by layers of materials with different electrical properties. The layers can be formed by a variety of deposition techniques determined in part by the type of material being deposited. For example, thin film deposition may involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components.
The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. The portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.
Depositing a thin film of material over an existing pattern can exaggerate the underlying pattern and create a non-uniformly flat surface. A uniformly flat surface is required to produce smaller and more densely packed active and passive components. Planarization can be used to remove material from the surface of the wafer and produce a uniformly flat surface. Planarization involves polishing the surface of the wafer with a polishing pad. An abrasive material and corrosive chemical are added to the surface of the wafer during polishing. The combined mechanical action of the abrasive and corrosive action of the chemical removes any irregular topography, resulting in a uniformly flat surface.
Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation. To singulate the die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with solder bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.
Electronic device 50 may be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device 50 may be a sub-component of a larger system. For example, electronic device 50 may be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASICs), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components.
In
In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate carrier. Second level packaging involves mechanically and electrically attaching the intermediate carrier to the PCB. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to the PCB.
For the purpose of illustration, several types of first level packaging, including wire bond package 56 and flip chip 58, are shown on PCB 52. Additionally, several types of second level packaging, including ball grid array (BGA) 60, bump chip carrier (BCC) 62, dual in-line package (DIP) 64, land grid array (LGA) 66, multi-chip module (MCM) 68, quad flat non-leaded package (QFN) 70, and quad flat package 72, are shown mounted on PCB 52. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB 52. In some embodiments, electronic device 50 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using cheaper components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.
Flip chip semiconductor packages and wafer level packages (WLP) are commonly used with integrated circuits (ICs) demanding high speed, high density, and greater pin count. In
BGA 60 is electrically and mechanically connected to PCB 52 with a BGA style second level packaging using interconnects 112. Semiconductor die 58 is electrically connected to conductive signal traces 54 in PCB 52 through interconnects 110, signal lines 114, and interconnects 112. A molding compound or encapsulant 116 is deposited over semiconductor die 58 and carrier 106 to provide physical support and electrical isolation for the device. The flip chip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die 58 to conduction tracks on PCB 52 in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance.
In another embodiment, active area 108 of semiconductor die 58 is directly mounted facedown to PCB 115, i.e., without an intermediate carrier, as shown in
An electrically conductive bump material is deposited over die bump pad 122 or substrate bump pad 126 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to die bump pad 122 and substrate bump pad 126 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form interconnect 132. In some applications, interconnect 132 is reflowed a second time to improve electrical contact between die bump pad 122 and substrate bump pad 126. The bump material around the narrow substrate bump pad 126 maintains die placement during reflow. Although interconnect 132 is shown connected to trace line 124 as a bump-on-lead (BOL), the interconnect can also be formed over a bump pad on substrate 130 having an area on the same order or greater than die bump pad 122. An optional underfill material 138 is deposited between semiconductor die 120 and substrate 130.
In high routing density applications, it is desirable to minimize escape pitch of trace lines 124. The escape pitch between trace lines 124 can be reduced by eliminating the solder mask for reflow containment, i.e., by reflowing the bump material without a solder mask. Solder mask 140 may be formed over a portion of substrate 130. However, solder mask 140 is not formed over substrate bump pad 126 of trace line 124 for reflow containment. That is, the portion of trace line 124 designed to mate with the bump material is devoid of any SRO of solder mask 140. Since no SRO is formed around die bump pad 122 or substrate bump pad 126, trace lines 124 can be formed with a finer pitch, i.e., trace lines 124 can be disposed closer together or to nearby structures. Without solder mask 140, the pitch between trace lines 124 is given as P=D+PLT+W/2, wherein D is the base diameter of interconnect 132, PLT is die placement tolerance, and W is the width of the trace line 124. In one embodiment, given a bump base diameter of 100 μm, PLT of 10 μm, and trace line width of 30 μm, the minimum escape pitch of trace line 124 is 125 μm. The solder mask-less bump formation eliminates the need to account for the ligament spacing of solder mask material between adjacent openings, SRT, and minimum resolvable SRO, as found in the prior art.
When the bump material is reflowed without a solder mask to metallurgically and electrically connect die bump pad 122 to substrate bump pad 126, the wetting and surface tension causes the bump material to maintain self-confinement and be retained within the space between die bump pad 122 and substrate bump pad 126 and portion of substrate 130 immediately adjacent to trace line 124 substantially within the footprint of the bump pads.
To achieve the desired self-confinement property, the bump material can be immersed in a flux solution prior to placement on die bump pad 122 or substrate bump pad 126 to selectively render the region contacted by the bump material more wettable than the surrounding area of trace line 124. The molten bump material remains confined substantially within the area defined by the bump pads due to the wettable properties of the flux solution. The bump material does not run-out to the less wettable areas. A thin oxide layer or other insulating layer can be formed over areas where bump material is not intended to make the area less wettable. Hence, solder mask 140 is not needed around die bump pad 122 or substrate bump pad 126.
In another embodiment, a composite interconnect 144 is formed between die bump pad 122 and substrate bump pad 126 to achieve the desired self-confinement of the bump material. Composite interconnect 144 includes a non-fusible base 146 made of Cu, Au, Sn, Ni, and Pb, and a fusible cap 148 made of solder, Sn, or indium, as shown in
An electrically conductive bump material is deposited over die bump pad 152 or substrate bump pad 156 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to die bump pad 152 and substrate bump pad 156 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form interconnect 162. In some applications, interconnect 162 is reflowed a second time to improve electrical contact between die bump pad 152 and substrate bump pad 156. The bump material around the narrow substrate bump pad 156 maintains die placement during reflow. Although interconnect 162 is shown connected to trace line 154 as BOL, the bump material can also be reflowed over a bump pad on substrate 160 having an area on the same order or greater than die bump pad 152. An optional underfill material 168 is deposited between semiconductor die 150 and substrate 160.
In high routing density applications, it is desirable to minimize escape pitch. In order to reduce the pitch between trace lines 154, the bump material is reflowed without a solder mask. The escape pitch between trace lines 154 can be reduced by eliminating the solder mask for solder reflow containment, i.e., by reflowing the bump material without a solder mask. Solder mask 170 may be formed over a portion of substrate 160. However, solder mask 170 is not formed over substrate bump pad 156 of trace line 154 for solder reflow containment. That is, the portion of trace line 154 designed to mate with the bump material is devoid of an SRO of solder mask 170. Since no SRO is formed around die bump pad 152 or substrate bump pad 156, trace lines 154 can be formed with a finer pitch, i.e., trace lines 154 can be disposed closer to adjacent structures.
Without solder mask 170, the pitch between trace lines 154 is given as P=D/2+PLT+W/2, wherein D is the base diameter of bump 162, PLT is die placement tolerance, and W is the width of the trace line 154. In one embodiment, given a bump diameter of 100 μm, PLT of 10 μm, and trace line width of 30 μm, the minimum escape pitch of trace line 154 is 75 μm. The solder mask-less bump formation eliminates the need to account for the ligament spacing of solder mask material between adjacent openings, SRT, and minimum resolvable SRO, as found in the prior art.
When the bump material is reflowed without a solder mask to metallurgically and electrically connect die bump pad 152 of semiconductor die 150 to substrate bump pad 156 of trace line 154, the wetting and surface tension causes the bump to maintain self-confinement and be retained within the space between die bump pad 152 and substrate bump pad 156 and portion of substrate 160 immediately adjacent to trace line 154 substantially within the footprint of the bump pads.
To achieve the desired self-confinement property, the bump material can be immersed in a flux solution prior to placement on die bump pad 152 or substrate bump pad 156 to selectively render the region contacted by the bump material more wettable than the surrounding area of trace line 154. The molten bump material remains confined substantially within the area defined by the bump pads due to the wettable properties of the flux solution. The bump material does not run-out to the less wettable areas. A thin oxide layer or other insulating layer can be formed over areas where bump material is not intended to make the area less wettable. Hence, solder mask 170 is not needed around die bump pad 152 or substrate bump pad 156.
In another embodiment, a composite interconnect is formed between die bump pad 152 and substrate bump pad 156 to achieve the desired self-confinement of the bump material. The composite interconnect includes a non-fusible base made of Cu, Au, Sn, Ni, or Pb, and a fusible cap made of solder, Sn, or indium, similar to
While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.
Claims (25)
Priority Applications (7)
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US53391803 true | 2003-12-31 | 2003-12-31 | |
US10985654 US7368817B2 (en) | 2003-11-10 | 2004-11-10 | Bump-on-lead flip chip interconnection |
US12062293 US7700407B2 (en) | 2003-11-10 | 2008-04-03 | Method of forming a bump-on-lead flip chip interconnection having higher escape routing density |
US14179108 true | 2008-12-31 | 2008-12-31 | |
US12471180 US8026128B2 (en) | 2004-11-10 | 2009-05-22 | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
US13756679 USRE44579E1 (en) | 2003-11-10 | 2013-02-01 | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
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US13756679 USRE44579E1 (en) | 2003-11-10 | 2013-02-01 | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
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Citations (112)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5186383A (en) | 1991-10-02 | 1993-02-16 | Motorola, Inc. | Method for forming solder bump interconnections to a solder-plated circuit trace |
US5378859A (en) | 1992-03-02 | 1995-01-03 | Casio Computer Co., Ltd. | Film wiring board |
US5386624A (en) | 1993-07-06 | 1995-02-07 | Motorola, Inc. | Method for underencapsulating components on circuit supporting substrates |
US5434410A (en) | 1992-05-29 | 1995-07-18 | Texas Instruments Incorporated | Fine-grain pyroelectric detector material and method |
US5508561A (en) | 1993-11-15 | 1996-04-16 | Nec Corporation | Apparatus for forming a double-bump structure used for flip-chip mounting |
US5519580A (en) | 1994-09-09 | 1996-05-21 | Intel Corporation | Method of controlling solder ball size of BGA IC components |
US5650595A (en) | 1995-05-25 | 1997-07-22 | International Business Machines Corporation | Electronic module with multiple solder dams in soldermask window |
US5710071A (en) | 1995-12-04 | 1998-01-20 | Motorola, Inc. | Process for underfilling a flip-chip semiconductor device |
US5844782A (en) | 1994-12-20 | 1998-12-01 | Sony Corporation | Printed wiring board and electronic device using same |
US5854514A (en) | 1996-08-05 | 1998-12-29 | International Buisness Machines Corporation | Lead-free interconnection for electronic devices |
US5869886A (en) | 1996-03-22 | 1999-02-09 | Nec Corporation | Flip chip semiconductor mounting structure with electrically conductive resin |
US5872399A (en) | 1996-04-01 | 1999-02-16 | Anam Semiconductor, Inc. | Solder ball land metal structure of ball grid semiconductor package |
US5889326A (en) | 1996-02-27 | 1999-03-30 | Nec Corporation | Structure for bonding semiconductor device to substrate |
US5915169A (en) | 1995-12-22 | 1999-06-22 | Anam Industrial Co., Ltd. | Semiconductor chip scale package and method of producing such |
US5985456A (en) | 1997-07-21 | 1999-11-16 | Miguel Albert Capote | Carboxyl-containing polyunsaturated fluxing adhesive for attaching integrated circuits |
US6049122A (en) | 1997-10-16 | 2000-04-11 | Fujitsu Limited | Flip chip mounting substrate with resin filled between substrate and semiconductor chip |
US6109507A (en) | 1997-11-11 | 2000-08-29 | Fujitsu Limited | Method of forming solder bumps and method of forming preformed solder bumps |
US6201305B1 (en) | 2000-06-09 | 2001-03-13 | Amkor Technology, Inc. | Making solder ball mounting pads on substrates |
US6218630B1 (en) | 1997-06-30 | 2001-04-17 | Fuji Photo Film Co., Ltd. | Printed circuit board having arrays of lands arranged inside and outside of each other having a reduced terminal-pitch |
US6229220B1 (en) | 1995-06-27 | 2001-05-08 | International Business Machines Corporation | Bump structure, bump forming method and package connecting body |
US6228466B1 (en) | 1997-04-11 | 2001-05-08 | Ibiden Co. Ltd. | Printed wiring board and method for manufacturing the same |
JP2001156203A (en) | 1999-11-24 | 2001-06-08 | Matsushita Electric Works Ltd | Printed wiring board for mounting semiconductor chip |
US6259163B1 (en) | 1997-12-25 | 2001-07-10 | Oki Electric Industry Co., Ltd. | Bond pad for stress releif between a substrate and an external substrate |
US20010013423A1 (en) | 1996-10-31 | 2001-08-16 | Hormazdyar M. Dalal | Flip chip attach on flexible circuit carrier using chip with metallic cap on solder |
US6281450B1 (en) | 1997-06-26 | 2001-08-28 | Hitachi Chemical Company, Ltd. | Substrate for mounting semiconductor chips |
US6297560B1 (en) | 1996-10-31 | 2001-10-02 | Miguel Albert Capote | Semiconductor flip-chip assembly with pre-applied encapsulating layers |
US6324754B1 (en) | 1998-03-25 | 2001-12-04 | Tessera, Inc. | Method for fabricating microelectronic assemblies |
US6329605B1 (en) | 1998-03-26 | 2001-12-11 | Tessera, Inc. | Components with conductive solder mask layers |
US6335571B1 (en) | 1997-07-21 | 2002-01-01 | Miguel Albert Capote | Semiconductor flip-chip package and method for the fabrication thereof |
US6335568B1 (en) | 1998-10-28 | 2002-01-01 | Seiko Epson Corporation | Semiconductor device and method of fabrication thereof, circuit board, and electronic equipment |
US20020041036A1 (en) | 1998-02-03 | 2002-04-11 | Smith John W. | Microelectronic assemblies with composite conductive elements |
US6383916B1 (en) | 1998-12-21 | 2002-05-07 | M. S. Lin | Top layers of metal for high performance IC's |
US6396707B1 (en) | 1999-10-21 | 2002-05-28 | Siliconware Precision Industries Co., Ltd. | Ball grid array package |
US6409073B1 (en) | 1998-07-15 | 2002-06-25 | Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. | Method for transfering solder to a device and/or testing the device |
US6441316B1 (en) | 1999-08-27 | 2002-08-27 | Mitsubishi Denki Kabushiki Kaisha | Printed-circuit board and a semiconductor module, and a manufacturing process of the semiconductor module |
US6448665B1 (en) | 1997-10-15 | 2002-09-10 | Kabushiki Kaisha Toshiba | Semiconductor package and manufacturing method thereof |
JP2002270732A (en) | 2001-03-13 | 2002-09-20 | Sharp Corp | Electronic component with underfill material |
US6458622B1 (en) | 1999-07-06 | 2002-10-01 | Motorola, Inc. | Stress compensation composition and semiconductor component formed using the stress compensation composition |
US20030049411A1 (en) | 2001-09-10 | 2003-03-13 | Delphi Technologies,Inc | No-flow underfill material and underfill method for flip chip devices |
US6573610B1 (en) | 2000-06-02 | 2003-06-03 | Siliconware Precision Industries Co., Ltd. | Substrate of semiconductor package for flip chip package |
US6600234B2 (en) | 1999-02-03 | 2003-07-29 | Casio Computer Co., Ltd. | Mounting structure having columnar electrodes and a sealing film |
US6608388B2 (en) | 2001-11-01 | 2003-08-19 | Siliconware Precision Industries Co., Ltd. | Delamination-preventing substrate and semiconductor package with the same |
WO2003071842A1 (en) | 2001-12-26 | 2003-08-28 | Motorola, Inc. | Method of mounting a semiconductor die on a substrate without using a solder mask |
US6678948B1 (en) | 1998-09-01 | 2004-01-20 | Robert Bosch Gmbh | Method for connecting electronic components to a substrate, and a method for checking such a connection |
US20040035909A1 (en) | 2002-08-22 | 2004-02-26 | Shing Yeh | Lead-based solder alloys containing copper |
US6710458B2 (en) | 2000-10-13 | 2004-03-23 | Sharp Kabushiki Kaisha | Tape for chip on film and semiconductor therewith |
US20040056341A1 (en) | 2002-09-19 | 2004-03-25 | Kabushiki Kaisha Toshiba | Semiconductor device, semiconductor package member, and semiconductor device manufacturing method |
US6734557B2 (en) | 2002-03-12 | 2004-05-11 | Sharp Kabushiki Kaisha | Semiconductor device |
US20040105223A1 (en) | 2001-03-19 | 2004-06-03 | Ryoichi Okada | Method of manufacturing electronic part and electronic part obtained by the method |
JP2004165283A (en) | 2002-11-11 | 2004-06-10 | Fujitsu Ltd | Semiconductor device |
US6774497B1 (en) | 2003-03-28 | 2004-08-10 | Freescale Semiconductor, Inc. | Flip-chip assembly with thin underfill and thick solder mask |
US6780682B2 (en) | 2001-02-27 | 2004-08-24 | Chippac, Inc. | Process for precise encapsulation of flip chip interconnects |
US6780673B2 (en) | 2002-06-12 | 2004-08-24 | Texas Instruments Incorporated | Method of forming a semiconductor device package using a plate layer surrounding contact pads |
US6787918B1 (en) | 2000-06-02 | 2004-09-07 | Siliconware Precision Industries Co., Ltd. | Substrate structure of flip chip package |
US6809262B1 (en) | 2003-06-03 | 2004-10-26 | Via Technologies, Inc. | Flip chip package carrier |
US6818545B2 (en) | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
US6821878B2 (en) | 2003-02-27 | 2004-11-23 | Freescale Semiconductor, Inc. | Area-array device assembly with pre-applied underfill layers on printed wiring board |
US20040232562A1 (en) | 2003-05-23 | 2004-11-25 | Texas Instruments Incorporated | System and method for increasing bump pad height |
US6849944B2 (en) | 2003-05-30 | 2005-02-01 | Texas Instruments Incorporated | Using a supporting structure to control collapse of a die towards a die pad during a reflow process for coupling the die to the die pad |
US6870276B1 (en) | 2001-12-26 | 2005-03-22 | Micron Technology, Inc. | Apparatus for supporting microelectronic substrates |
JP2005109187A (en) | 2003-09-30 | 2005-04-21 | Tdk Corp | Flip chip packaging circuit board and its manufacturing method, and integrated circuit device |
US6888255B2 (en) | 2003-05-30 | 2005-05-03 | Texas Instruments Incorporated | Built-up bump pad structure and method for same |
US6913948B2 (en) | 1999-11-10 | 2005-07-05 | International Business Machines Corporation | Partially captured oriented interconnections for BGA packages and a method of forming the interconnections |
US20050248037A1 (en) | 2004-05-06 | 2005-11-10 | Advanced Semiconductor Engineering, Inc. | Flip-chip package substrate with a high-density layout |
US7005750B2 (en) | 2003-08-01 | 2006-02-28 | Advanced Semiconductor Engineering, Inc. | Substrate with reinforced contact pad structure |
US7005585B2 (en) | 2002-09-02 | 2006-02-28 | Murata Manufacturing Co., Ltd. | Mounting board and electronic device using same |
US7049705B2 (en) | 2003-07-15 | 2006-05-23 | Advanced Semiconductor Engineering, Inc. | Chip structure |
US7057284B2 (en) | 2004-08-12 | 2006-06-06 | Texas Instruments Incorporated | Fine pitch low-cost flip chip substrate |
US7064435B2 (en) | 2003-07-29 | 2006-06-20 | Samsung Electronics Co., Ltd. | Semiconductor package with improved ball land structure |
US20060131758A1 (en) | 2004-12-22 | 2006-06-22 | Stmicroelectronics, Inc. | Anchored non-solder mask defined ball pad |
US7098407B2 (en) | 2003-08-23 | 2006-08-29 | Samsung Electronics Co., Ltd. | Non-solder mask defined (NSMD) type wiring substrate for ball grid array (BGA) package and method for manufacturing such a wiring substrate |
US7102239B2 (en) | 2003-08-18 | 2006-09-05 | Siliconware Precision Industries Co., Ltd. | Chip carrier for semiconductor chip |
US20060216860A1 (en) | 2005-03-25 | 2006-09-28 | Stats Chippac, Ltd. | Flip chip interconnection having narrow interconnection sites on the substrate |
US20060255473A1 (en) | 2005-05-16 | 2006-11-16 | Stats Chippac Ltd. | Flip chip interconnect solder mask |
US7173828B2 (en) | 2003-07-28 | 2007-02-06 | Siliconware Precision Industries Co., Ltd. | Ground pad structure for preventing solder extrusion and semiconductor package having the ground pad structure |
US7224073B2 (en) | 2004-05-18 | 2007-05-29 | Ultratera Corporation | Substrate for solder joint |
US7242099B2 (en) | 2001-03-05 | 2007-07-10 | Megica Corporation | Chip package with multiple chips connected by bumps |
US20070200234A1 (en) | 2006-02-28 | 2007-08-30 | Texas Instruments Incorporated | Flip-Chip Device Having Underfill in Controlled Gap |
US7271484B2 (en) | 2003-09-25 | 2007-09-18 | Infineon Technologies Ag | Substrate for producing a soldering connection |
US7294929B2 (en) | 2003-12-30 | 2007-11-13 | Texas Instruments Incorporated | Solder ball pad structure |
US7317245B1 (en) | 2006-04-07 | 2008-01-08 | Amkor Technology, Inc. | Method for manufacturing a semiconductor device substrate |
US20080093749A1 (en) | 2006-10-20 | 2008-04-24 | Texas Instruments Incorporated | Partial Solder Mask Defined Pad Design |
US7405484B2 (en) | 2003-09-30 | 2008-07-29 | Sanyo Electric Co., Ltd. | Semiconductor device containing stacked semiconductor chips and manufacturing method thereof |
US20080179740A1 (en) | 2007-01-25 | 2008-07-31 | Advanced Semiconductor Engineering, Inc. | Package substrate, method of fabricating the same and chip package |
US7436063B2 (en) | 2004-10-04 | 2008-10-14 | Rohm Co., Ltd. | Packaging substrate and semiconductor device |
US20080277802A1 (en) | 2007-05-10 | 2008-11-13 | Siliconware Precision Industries Co., Ltd. | Flip-chip semiconductor package and package substrate applicable thereto |
US7521284B2 (en) | 2007-03-05 | 2009-04-21 | Texas Instruments Incorporated | System and method for increased stand-off height in stud bumping process |
US20090108445A1 (en) | 2007-10-31 | 2009-04-30 | Advanced Semiconductor Engineering, Inc. | Substrate structure and semiconductor package using the same |
US20090114436A1 (en) | 2007-11-07 | 2009-05-07 | Advanced Semiconductor Engineering, Inc. | Substrate structure |
US20090152716A1 (en) | 2007-12-12 | 2009-06-18 | Shinko Electric Industries Co., Ltd. | Wiring substrate and electronic component mounting structure |
US20090191329A1 (en) | 2008-01-30 | 2009-07-30 | Advanced Semiconductor Engineering, Inc. | Surface treatment process for circuit board |
US20090288866A1 (en) | 2006-01-16 | 2009-11-26 | Siliconware Precision Industries Co., Ltd. | Electronic carrier board |
US20090308647A1 (en) | 2008-06-11 | 2009-12-17 | Advanced Semiconductor Engineering, Inc. | Circuit board with buried conductive trace formed thereon and method for manufacturing the same |
US7642660B2 (en) | 2002-12-17 | 2010-01-05 | Cheng Siew Tay | Method and apparatus for reducing electrical interconnection fatigue |
US7670939B2 (en) | 2008-05-12 | 2010-03-02 | Ati Technologies Ulc | Semiconductor chip bump connection apparatus and method |
US7671454B2 (en) | 2006-05-12 | 2010-03-02 | Sharp Kabushiki Kaisha | Tape carrier, semiconductor apparatus, and semiconductor module apparatus |
US7700407B2 (en) | 2003-11-10 | 2010-04-20 | Stats Chippac, Ltd. | Method of forming a bump-on-lead flip chip interconnection having higher escape routing density |
US7732913B2 (en) | 2006-02-03 | 2010-06-08 | Siliconware Precision Industries Co., Ltd. | Semiconductor package substrate |
US20100139965A1 (en) | 2008-12-09 | 2010-06-10 | Advanced Semiconductor Engineering, Inc. | Embedded circuit substrate and manufacturing method thereof |
US7750457B2 (en) | 2004-03-30 | 2010-07-06 | Sharp Kabushiki Kaisha | Semiconductor apparatus, manufacturing method thereof, semiconductor module apparatus using semiconductor apparatus, and wire substrate for semiconductor apparatus |
US7790509B2 (en) | 2008-06-27 | 2010-09-07 | Texas Instruments Incorporated | Method for fine-pitch, low stress flip-chip interconnect |
US7791211B2 (en) | 2007-10-19 | 2010-09-07 | Advanced Semiconductor Engineering, Inc. | Flip chip package structure and carrier thereof |
US7847399B2 (en) | 2007-12-07 | 2010-12-07 | Texas Instruments Incorporated | Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles |
US7847417B2 (en) | 2005-12-22 | 2010-12-07 | Shinko Electric Industries Co., Ltd. | Flip-chip mounting substrate and flip-chip mounting method |
US7851928B2 (en) | 2008-06-10 | 2010-12-14 | Texas Instruments Incorporated | Semiconductor device having substrate with differentially plated copper and selective solder |
US7898083B2 (en) | 2008-12-17 | 2011-03-01 | Texas Instruments Incorporated | Method for low stress flip-chip assembly of fine-pitch semiconductor devices |
US20110049703A1 (en) | 2009-08-25 | 2011-03-03 | Jun-Chung Hsu | Flip-Chip Package Structure |
US7902679B2 (en) | 2001-03-05 | 2011-03-08 | Megica Corporation | Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US7902678B2 (en) | 2004-03-29 | 2011-03-08 | Nec Corporation | Semiconductor device and manufacturing method thereof |
US7932170B1 (en) | 2008-06-23 | 2011-04-26 | Amkor Technology, Inc. | Flip chip bump structure and fabrication method |
US7947602B2 (en) | 2007-02-21 | 2011-05-24 | Texas Instruments Incorporated | Conductive pattern formation method |
Patent Citations (116)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1993006964A1 (en) | 1991-10-02 | 1993-04-15 | Motorola, Inc. | Method for forming solder bump interconnections to a solder-plated circuit trace |
US5186383A (en) | 1991-10-02 | 1993-02-16 | Motorola, Inc. | Method for forming solder bump interconnections to a solder-plated circuit trace |
US5378859A (en) | 1992-03-02 | 1995-01-03 | Casio Computer Co., Ltd. | Film wiring board |
US5434410A (en) | 1992-05-29 | 1995-07-18 | Texas Instruments Incorporated | Fine-grain pyroelectric detector material and method |
US5386624A (en) | 1993-07-06 | 1995-02-07 | Motorola, Inc. | Method for underencapsulating components on circuit supporting substrates |
US5508561A (en) | 1993-11-15 | 1996-04-16 | Nec Corporation | Apparatus for forming a double-bump structure used for flip-chip mounting |
US5519580A (en) | 1994-09-09 | 1996-05-21 | Intel Corporation | Method of controlling solder ball size of BGA IC components |
US5844782A (en) | 1994-12-20 | 1998-12-01 | Sony Corporation | Printed wiring board and electronic device using same |
US5650595A (en) | 1995-05-25 | 1997-07-22 | International Business Machines Corporation | Electronic module with multiple solder dams in soldermask window |
US6229220B1 (en) | 1995-06-27 | 2001-05-08 | International Business Machines Corporation | Bump structure, bump forming method and package connecting body |
US5710071A (en) | 1995-12-04 | 1998-01-20 | Motorola, Inc. | Process for underfilling a flip-chip semiconductor device |
US5915169A (en) | 1995-12-22 | 1999-06-22 | Anam Industrial Co., Ltd. | Semiconductor chip scale package and method of producing such |
US5889326A (en) | 1996-02-27 | 1999-03-30 | Nec Corporation | Structure for bonding semiconductor device to substrate |
US5869886A (en) | 1996-03-22 | 1999-02-09 | Nec Corporation | Flip chip semiconductor mounting structure with electrically conductive resin |
US5872399A (en) | 1996-04-01 | 1999-02-16 | Anam Semiconductor, Inc. | Solder ball land metal structure of ball grid semiconductor package |
US5854514A (en) | 1996-08-05 | 1998-12-29 | International Buisness Machines Corporation | Lead-free interconnection for electronic devices |
US20010013423A1 (en) | 1996-10-31 | 2001-08-16 | Hormazdyar M. Dalal | Flip chip attach on flexible circuit carrier using chip with metallic cap on solder |
US6297560B1 (en) | 1996-10-31 | 2001-10-02 | Miguel Albert Capote | Semiconductor flip-chip assembly with pre-applied encapsulating layers |
US6228466B1 (en) | 1997-04-11 | 2001-05-08 | Ibiden Co. Ltd. | Printed wiring board and method for manufacturing the same |
US6281450B1 (en) | 1997-06-26 | 2001-08-28 | Hitachi Chemical Company, Ltd. | Substrate for mounting semiconductor chips |
US6218630B1 (en) | 1997-06-30 | 2001-04-17 | Fuji Photo Film Co., Ltd. | Printed circuit board having arrays of lands arranged inside and outside of each other having a reduced terminal-pitch |
US5985456A (en) | 1997-07-21 | 1999-11-16 | Miguel Albert Capote | Carboxyl-containing polyunsaturated fluxing adhesive for attaching integrated circuits |
US6335571B1 (en) | 1997-07-21 | 2002-01-01 | Miguel Albert Capote | Semiconductor flip-chip package and method for the fabrication thereof |
US6448665B1 (en) | 1997-10-15 | 2002-09-10 | Kabushiki Kaisha Toshiba | Semiconductor package and manufacturing method thereof |
US6049122A (en) | 1997-10-16 | 2000-04-11 | Fujitsu Limited | Flip chip mounting substrate with resin filled between substrate and semiconductor chip |
US6109507A (en) | 1997-11-11 | 2000-08-29 | Fujitsu Limited | Method of forming solder bumps and method of forming preformed solder bumps |
US6259163B1 (en) | 1997-12-25 | 2001-07-10 | Oki Electric Industry Co., Ltd. | Bond pad for stress releif between a substrate and an external substrate |
US20020041036A1 (en) | 1998-02-03 | 2002-04-11 | Smith John W. | Microelectronic assemblies with composite conductive elements |
US6324754B1 (en) | 1998-03-25 | 2001-12-04 | Tessera, Inc. | Method for fabricating microelectronic assemblies |
US6329605B1 (en) | 1998-03-26 | 2001-12-11 | Tessera, Inc. | Components with conductive solder mask layers |
US6409073B1 (en) | 1998-07-15 | 2002-06-25 | Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. | Method for transfering solder to a device and/or testing the device |
US6678948B1 (en) | 1998-09-01 | 2004-01-20 | Robert Bosch Gmbh | Method for connecting electronic components to a substrate, and a method for checking such a connection |
US6335568B1 (en) | 1998-10-28 | 2002-01-01 | Seiko Epson Corporation | Semiconductor device and method of fabrication thereof, circuit board, and electronic equipment |
US6383916B1 (en) | 1998-12-21 | 2002-05-07 | M. S. Lin | Top layers of metal for high performance IC's |
US6600234B2 (en) | 1999-02-03 | 2003-07-29 | Casio Computer Co., Ltd. | Mounting structure having columnar electrodes and a sealing film |
US6458622B1 (en) | 1999-07-06 | 2002-10-01 | Motorola, Inc. | Stress compensation composition and semiconductor component formed using the stress compensation composition |
US6441316B1 (en) | 1999-08-27 | 2002-08-27 | Mitsubishi Denki Kabushiki Kaisha | Printed-circuit board and a semiconductor module, and a manufacturing process of the semiconductor module |
US6396707B1 (en) | 1999-10-21 | 2002-05-28 | Siliconware Precision Industries Co., Ltd. | Ball grid array package |
US6913948B2 (en) | 1999-11-10 | 2005-07-05 | International Business Machines Corporation | Partially captured oriented interconnections for BGA packages and a method of forming the interconnections |
JP2001156203A (en) | 1999-11-24 | 2001-06-08 | Matsushita Electric Works Ltd | Printed wiring board for mounting semiconductor chip |
US6787918B1 (en) | 2000-06-02 | 2004-09-07 | Siliconware Precision Industries Co., Ltd. | Substrate structure of flip chip package |
US6573610B1 (en) | 2000-06-02 | 2003-06-03 | Siliconware Precision Industries Co., Ltd. | Substrate of semiconductor package for flip chip package |
US6201305B1 (en) | 2000-06-09 | 2001-03-13 | Amkor Technology, Inc. | Making solder ball mounting pads on substrates |
US6710458B2 (en) | 2000-10-13 | 2004-03-23 | Sharp Kabushiki Kaisha | Tape for chip on film and semiconductor therewith |
US6780682B2 (en) | 2001-02-27 | 2004-08-24 | Chippac, Inc. | Process for precise encapsulation of flip chip interconnects |
US7242099B2 (en) | 2001-03-05 | 2007-07-10 | Megica Corporation | Chip package with multiple chips connected by bumps |
US6818545B2 (en) | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
US7902679B2 (en) | 2001-03-05 | 2011-03-08 | Megica Corporation | Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump |
JP2002270732A (en) | 2001-03-13 | 2002-09-20 | Sharp Corp | Electronic component with underfill material |
US20040105223A1 (en) | 2001-03-19 | 2004-06-03 | Ryoichi Okada | Method of manufacturing electronic part and electronic part obtained by the method |
US20030049411A1 (en) | 2001-09-10 | 2003-03-13 | Delphi Technologies,Inc | No-flow underfill material and underfill method for flip chip devices |
US6660560B2 (en) | 2001-09-10 | 2003-12-09 | Delphi Technologies, Inc. | No-flow underfill material and underfill method for flip chip devices |
US6608388B2 (en) | 2001-11-01 | 2003-08-19 | Siliconware Precision Industries Co., Ltd. | Delamination-preventing substrate and semiconductor package with the same |
WO2003071842A1 (en) | 2001-12-26 | 2003-08-28 | Motorola, Inc. | Method of mounting a semiconductor die on a substrate without using a solder mask |
US6870276B1 (en) | 2001-12-26 | 2005-03-22 | Micron Technology, Inc. | Apparatus for supporting microelectronic substrates |
US6734557B2 (en) | 2002-03-12 | 2004-05-11 | Sharp Kabushiki Kaisha | Semiconductor device |
US6780673B2 (en) | 2002-06-12 | 2004-08-24 | Texas Instruments Incorporated | Method of forming a semiconductor device package using a plate layer surrounding contact pads |
US20040035909A1 (en) | 2002-08-22 | 2004-02-26 | Shing Yeh | Lead-based solder alloys containing copper |
US7005585B2 (en) | 2002-09-02 | 2006-02-28 | Murata Manufacturing Co., Ltd. | Mounting board and electronic device using same |
US20040056341A1 (en) | 2002-09-19 | 2004-03-25 | Kabushiki Kaisha Toshiba | Semiconductor device, semiconductor package member, and semiconductor device manufacturing method |
JP2004165283A (en) | 2002-11-11 | 2004-06-10 | Fujitsu Ltd | Semiconductor device |
US7642660B2 (en) | 2002-12-17 | 2010-01-05 | Cheng Siew Tay | Method and apparatus for reducing electrical interconnection fatigue |
US6821878B2 (en) | 2003-02-27 | 2004-11-23 | Freescale Semiconductor, Inc. | Area-array device assembly with pre-applied underfill layers on printed wiring board |
US6774497B1 (en) | 2003-03-28 | 2004-08-10 | Freescale Semiconductor, Inc. | Flip-chip assembly with thin underfill and thick solder mask |
US20040232562A1 (en) | 2003-05-23 | 2004-11-25 | Texas Instruments Incorporated | System and method for increasing bump pad height |
US6888255B2 (en) | 2003-05-30 | 2005-05-03 | Texas Instruments Incorporated | Built-up bump pad structure and method for same |
US6849944B2 (en) | 2003-05-30 | 2005-02-01 | Texas Instruments Incorporated | Using a supporting structure to control collapse of a die towards a die pad during a reflow process for coupling the die to the die pad |
US6809262B1 (en) | 2003-06-03 | 2004-10-26 | Via Technologies, Inc. | Flip chip package carrier |
US7049705B2 (en) | 2003-07-15 | 2006-05-23 | Advanced Semiconductor Engineering, Inc. | Chip structure |
US7173828B2 (en) | 2003-07-28 | 2007-02-06 | Siliconware Precision Industries Co., Ltd. | Ground pad structure for preventing solder extrusion and semiconductor package having the ground pad structure |
US7064435B2 (en) | 2003-07-29 | 2006-06-20 | Samsung Electronics Co., Ltd. | Semiconductor package with improved ball land structure |
US7005750B2 (en) | 2003-08-01 | 2006-02-28 | Advanced Semiconductor Engineering, Inc. | Substrate with reinforced contact pad structure |
US7102239B2 (en) | 2003-08-18 | 2006-09-05 | Siliconware Precision Industries Co., Ltd. | Chip carrier for semiconductor chip |
US7098407B2 (en) | 2003-08-23 | 2006-08-29 | Samsung Electronics Co., Ltd. | Non-solder mask defined (NSMD) type wiring substrate for ball grid array (BGA) package and method for manufacturing such a wiring substrate |
US7271484B2 (en) | 2003-09-25 | 2007-09-18 | Infineon Technologies Ag | Substrate for producing a soldering connection |
JP2005109187A (en) | 2003-09-30 | 2005-04-21 | Tdk Corp | Flip chip packaging circuit board and its manufacturing method, and integrated circuit device |
US7405484B2 (en) | 2003-09-30 | 2008-07-29 | Sanyo Electric Co., Ltd. | Semiconductor device containing stacked semiconductor chips and manufacturing method thereof |
US20050103516A1 (en) | 2003-09-30 | 2005-05-19 | Tdk Corporation | Flip-chip mounting circuit board, manufacturing method thereof and integrated circuit device |
US7973406B2 (en) | 2003-11-10 | 2011-07-05 | Stats Chippac, Ltd. | Bump-on-lead flip chip interconnection |
US7700407B2 (en) | 2003-11-10 | 2010-04-20 | Stats Chippac, Ltd. | Method of forming a bump-on-lead flip chip interconnection having higher escape routing density |
US7294929B2 (en) | 2003-12-30 | 2007-11-13 | Texas Instruments Incorporated | Solder ball pad structure |
US7902678B2 (en) | 2004-03-29 | 2011-03-08 | Nec Corporation | Semiconductor device and manufacturing method thereof |
US7750457B2 (en) | 2004-03-30 | 2010-07-06 | Sharp Kabushiki Kaisha | Semiconductor apparatus, manufacturing method thereof, semiconductor module apparatus using semiconductor apparatus, and wire substrate for semiconductor apparatus |
US20050248037A1 (en) | 2004-05-06 | 2005-11-10 | Advanced Semiconductor Engineering, Inc. | Flip-chip package substrate with a high-density layout |
US7224073B2 (en) | 2004-05-18 | 2007-05-29 | Ultratera Corporation | Substrate for solder joint |
US7057284B2 (en) | 2004-08-12 | 2006-06-06 | Texas Instruments Incorporated | Fine pitch low-cost flip chip substrate |
US7436063B2 (en) | 2004-10-04 | 2008-10-14 | Rohm Co., Ltd. | Packaging substrate and semiconductor device |
US20060131758A1 (en) | 2004-12-22 | 2006-06-22 | Stmicroelectronics, Inc. | Anchored non-solder mask defined ball pad |
US20060216860A1 (en) | 2005-03-25 | 2006-09-28 | Stats Chippac, Ltd. | Flip chip interconnection having narrow interconnection sites on the substrate |
US20060255473A1 (en) | 2005-05-16 | 2006-11-16 | Stats Chippac Ltd. | Flip chip interconnect solder mask |
US7847417B2 (en) | 2005-12-22 | 2010-12-07 | Shinko Electric Industries Co., Ltd. | Flip-chip mounting substrate and flip-chip mounting method |
US20090288866A1 (en) | 2006-01-16 | 2009-11-26 | Siliconware Precision Industries Co., Ltd. | Electronic carrier board |
US7732913B2 (en) | 2006-02-03 | 2010-06-08 | Siliconware Precision Industries Co., Ltd. | Semiconductor package substrate |
US20070200234A1 (en) | 2006-02-28 | 2007-08-30 | Texas Instruments Incorporated | Flip-Chip Device Having Underfill in Controlled Gap |
US7317245B1 (en) | 2006-04-07 | 2008-01-08 | Amkor Technology, Inc. | Method for manufacturing a semiconductor device substrate |
US7671454B2 (en) | 2006-05-12 | 2010-03-02 | Sharp Kabushiki Kaisha | Tape carrier, semiconductor apparatus, and semiconductor module apparatus |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US20080093749A1 (en) | 2006-10-20 | 2008-04-24 | Texas Instruments Incorporated | Partial Solder Mask Defined Pad Design |
US20080179740A1 (en) | 2007-01-25 | 2008-07-31 | Advanced Semiconductor Engineering, Inc. | Package substrate, method of fabricating the same and chip package |
US7947602B2 (en) | 2007-02-21 | 2011-05-24 | Texas Instruments Incorporated | Conductive pattern formation method |
US7521284B2 (en) | 2007-03-05 | 2009-04-21 | Texas Instruments Incorporated | System and method for increased stand-off height in stud bumping process |
US20080277802A1 (en) | 2007-05-10 | 2008-11-13 | Siliconware Precision Industries Co., Ltd. | Flip-chip semiconductor package and package substrate applicable thereto |
US7791211B2 (en) | 2007-10-19 | 2010-09-07 | Advanced Semiconductor Engineering, Inc. | Flip chip package structure and carrier thereof |
US20090108445A1 (en) | 2007-10-31 | 2009-04-30 | Advanced Semiconductor Engineering, Inc. | Substrate structure and semiconductor package using the same |
US20090114436A1 (en) | 2007-11-07 | 2009-05-07 | Advanced Semiconductor Engineering, Inc. | Substrate structure |
US7847399B2 (en) | 2007-12-07 | 2010-12-07 | Texas Instruments Incorporated | Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles |
US20090152716A1 (en) | 2007-12-12 | 2009-06-18 | Shinko Electric Industries Co., Ltd. | Wiring substrate and electronic component mounting structure |
US20090191329A1 (en) | 2008-01-30 | 2009-07-30 | Advanced Semiconductor Engineering, Inc. | Surface treatment process for circuit board |
US7670939B2 (en) | 2008-05-12 | 2010-03-02 | Ati Technologies Ulc | Semiconductor chip bump connection apparatus and method |
US7851928B2 (en) | 2008-06-10 | 2010-12-14 | Texas Instruments Incorporated | Semiconductor device having substrate with differentially plated copper and selective solder |
US20090308647A1 (en) | 2008-06-11 | 2009-12-17 | Advanced Semiconductor Engineering, Inc. | Circuit board with buried conductive trace formed thereon and method for manufacturing the same |
US7932170B1 (en) | 2008-06-23 | 2011-04-26 | Amkor Technology, Inc. | Flip chip bump structure and fabrication method |
US7790509B2 (en) | 2008-06-27 | 2010-09-07 | Texas Instruments Incorporated | Method for fine-pitch, low stress flip-chip interconnect |
US20100139965A1 (en) | 2008-12-09 | 2010-06-10 | Advanced Semiconductor Engineering, Inc. | Embedded circuit substrate and manufacturing method thereof |
US7898083B2 (en) | 2008-12-17 | 2011-03-01 | Texas Instruments Incorporated | Method for low stress flip-chip assembly of fine-pitch semiconductor devices |
US20110049703A1 (en) | 2009-08-25 | 2011-03-03 | Jun-Chung Hsu | Flip-Chip Package Structure |
Non-Patent Citations (6)
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