JP2002270732A - Electronic component with underfill material - Google Patents

Electronic component with underfill material

Info

Publication number
JP2002270732A
JP2002270732A JP2001069625A JP2001069625A JP2002270732A JP 2002270732 A JP2002270732 A JP 2002270732A JP 2001069625 A JP2001069625 A JP 2001069625A JP 2001069625 A JP2001069625 A JP 2001069625A JP 2002270732 A JP2002270732 A JP 2002270732A
Authority
JP
Japan
Prior art keywords
electronic component
underfill material
substrate
solder
gap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001069625A
Other languages
Japanese (ja)
Inventor
Toshio Suganuma
俊夫 菅沼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP2001069625A priority Critical patent/JP2002270732A/en
Publication of JP2002270732A publication Critical patent/JP2002270732A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To remarkably increase workability of filling and productivity of a component, enable perfect filling of a gap with an underfill material and enable mounting of other electronic components on a substrate with high efficiency and high density, in an electronic component which is connected with the substrate via colder bumps and in which the gap between the substrate and the component is filled with the underfill material. SOLUTION: One surface side of an electronic component body 11 is coated with an underfill material 13 so as to expose tips of the solder bumps 12 arranged on the electronic component body 11. From a viewpoint for more stiffly attaching an electronic component 1 on the substrate, a side face of the electronic component body 11 may be coated further with the underfill material 13.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、チップサイズパッ
ケージ(Chip Size Package;以下単に「CSP」と記
すことがある)やボールグリッドアレイパッケージ(Ba
ll Grid Array Package;以下単に「BGAP」と記す
ことがある)などの電子部品であって、半田バンプを介
して基板に実装するものに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip size package (hereinafter sometimes simply referred to as "CSP") and a ball grid array package (Ba).
ll Grid Array Package (hereinafter sometimes simply referred to as "BGAP") and the like, which is mounted on a substrate via solder bumps.

【0002】[0002]

【従来の技術】近年、液晶表示装置等において小型軽量
化を目的として、表示部分と駆動回路とを一体化させた
チップオン技術が開発検討されている。このチップオン
技術は、パターン化された配線が表面に形成された基板
上に電子部品を実装するものである。図7に、従来の実
装例を示す工程図を示す。電子部品本体11の下面に、
電極端子(不図示)を形成し、この電極端子に半田バン
プ12を所定の方法により接合する。基板2上に形成さ
れた電極端子(半田クリーム)21上にこの半田バンプ
12を対向配置し(工程(ニ))、電極端子間を半田バ
ンプ12で接続して電子部品1を基板2上に実装する
(工程(ホ))。そしてリフロー炉で半田バンプ12及
び半田クリーム21を溶融一体化させて半田Sとし、電
子部品1を基板2上に固定する(工程(ヘ))。次に、
電子部品1とガラス基板2との間の空隙部Pにエポキシ
樹脂などのアンダーフィル材13を充填する(工程
(ト))。そしてアンダーフィル材13を加熱硬化させ
て電子部品1の接合強度を確保していた。
2. Description of the Related Art In recent years, for the purpose of reducing the size and weight of a liquid crystal display device or the like, a chip-on technology in which a display portion and a driving circuit are integrated has been studied. In this chip-on technique, an electronic component is mounted on a substrate on which patterned wiring is formed on the surface. FIG. 7 is a process chart showing a conventional mounting example. On the lower surface of the electronic component body 11,
An electrode terminal (not shown) is formed, and a solder bump 12 is bonded to the electrode terminal by a predetermined method. The solder bumps 12 are opposed to each other on electrode terminals (solder cream) 21 formed on the substrate 2 (step (d)), and the electrode terminals are connected by the solder bumps 12 to place the electronic component 1 on the substrate 2. Mount (process (e)). Then, the solder bumps 12 and the solder cream 21 are melted and integrated in a reflow furnace to form solder S, and the electronic component 1 is fixed on the substrate 2 (step (f)). next,
A gap P between the electronic component 1 and the glass substrate 2 is filled with an underfill material 13 such as an epoxy resin (step (g)). Then, the underfill material 13 is cured by heating to secure the bonding strength of the electronic component 1.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、ガラス
基板2に電子部品1を実装した後にアンダーフィル材1
3を空隙部Pに完全に充填するには非常に手間がかか
る。また空隙部Pに充填したアンダーフィル材13を硬
化させるのに高温で長時間放置する必要があった。さら
にアンダーフィル材13が空隙部Pに完全に充填できな
い、すなわち空隙部Pに未充填部分があると、外力が加
わったときにその部分から剥離するといった問題があっ
た。加えて、ガラス基板2上に実装した電子部品1の空
隙部Pにアンダーフィル材13を充填する作業域を確保
するために、ICやコンデンサといった他の電子部品を
電子部品1の周囲から離して基板上に実装しなければな
らず、電子部品の配置設計上大きな制約となっていた。
However, after mounting the electronic component 1 on the glass substrate 2, the underfill material 1
It takes a lot of trouble to completely fill the void portion P with 3. Further, it is necessary to leave the underfill material 13 filled in the void portion P at a high temperature for a long time to cure it. Furthermore, there is a problem that the underfill material 13 cannot be completely filled in the gap P, that is, if there is an unfilled portion in the gap P, when the external force is applied, the gap is separated from the portion. In addition, in order to secure a work area for filling the gap P of the electronic component 1 mounted on the glass substrate 2 with the underfill material 13, other electronic components such as ICs and capacitors are separated from the periphery of the electronic component 1. It has to be mounted on a substrate, which is a great constraint on the layout design of electronic components.

【0004】本発明は、このような従来の問題に鑑みて
なされたものであり、半田バンプを介して基板に接続
し、基板との間の空隙部にアンダーフィル材を充填した
電子部品において、充填の作業性および部品の生産性を
大幅に向上させ、前記空隙部にアンダーフィル材を完全
に充填でき、他の電子部品を基板上に高効率・高密度に
実装できる電子部品を提供することをその目的とするも
のである。
SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and has been developed for an electronic component which is connected to a substrate via a solder bump and has a gap between the substrate and the underfill material filled with an underfill material. To provide an electronic component that can significantly improve the workability of filling and the productivity of components, can completely fill the gap with an underfill material, and can mount other electronic components on a substrate with high efficiency and high density. Is the purpose.

【0005】[0005]

【課題を解決するための手段】本発明によれば、チップ
サイズパッケージ本体の一面側に半田バンプを設け、こ
の半田バンプの先端部が露出するように前記本体の一面
側をアンダーフィル材で被覆したことを特徴とする電子
部品が提供される。
According to the present invention, a solder bump is provided on one surface of a chip size package main body, and one surface of the main body is covered with an underfill material so that the tip of the solder bump is exposed. An electronic component is provided.

【0006】ここで、電子部品を基板上により強固に取
り付けるといった観点から、本体の側面をアンダーフィ
ル材でさらに被覆してもよい。
Here, from the viewpoint of mounting the electronic component more firmly on the substrate, the side surface of the main body may be further covered with an underfill material.

【0007】アンダーフィル材は、常温では固化状態で
加熱により液状となる材質であって、半田の溶融温度近
傍まで加熱されると液状となるが、これが冷却されると
耐熱性のある固化状態となるものが望ましい。例えば融
点の異なる少なくとも2つの樹脂を含んでいるものが望
ましい。以下説明の便宜上、融点の高い方の樹脂を「高
融点樹脂」、融点の低い方の樹脂を「低融点樹脂」と記
すことがある。
The underfill material is a material which becomes liquid by heating in a solid state at normal temperature, and becomes liquid when heated to a temperature near the melting temperature of solder. Is desirable. For example, a resin containing at least two resins having different melting points is desirable. Hereinafter, for convenience of description, a resin having a higher melting point may be referred to as a “high melting point resin” and a resin having a lower melting point may be referred to as a “low melting point resin”.

【0008】また、半田を溶融したときに半田バンプ間
の短絡(いわゆる半田ブリッジ)が生じるのを防止する
観点から、アンダーフィル材にフラックス剤を含有させ
るのが好ましい。
Further, from the viewpoint of preventing a short circuit between solder bumps (so-called solder bridge) from occurring when the solder is melted, it is preferable to include a flux agent in the underfill material.

【0009】[0009]

【発明の実施の形態】本発明者は、半田バンプ間の空隙
部にアンダーフィル材を容易且つ完全に充填することが
できないか鋭意検討を続けた結果、電子部品を基板に装
着する前に、電子部品に設けられた半田バンプ間の空隙
部にアンダーフィル剤を予め充填しておけばよいことを
見出し本発明をなすに至った。このような構成によれ
ば、電子部品に設けられた半田バンプ間の空隙部にアン
ダーフィル材を隙間なく充填することができ、しかも充
填の作業性に優れる。またアンダーフィル材を空隙部に
充填するための作業域を電子部品を実装した基板上に確
保する必要がなくなり、電子部品を基板上に高効率・高
密度に実装できる。
BEST MODE FOR CARRYING OUT THE INVENTION The inventor of the present invention has conducted intensive studies as to whether or not an underfill material can be easily and completely filled in a gap between solder bumps. As a result, before mounting an electronic component on a board, The inventor has found that it is sufficient to previously fill the gap between the solder bumps provided on the electronic component with an underfill agent, and has accomplished the present invention. According to such a configuration, the gap between the solder bumps provided on the electronic component can be filled with the underfill material without any gap, and the filling workability is excellent. Further, it is not necessary to secure a work area for filling the void portion with the underfill material on the substrate on which the electronic component is mounted, and the electronic component can be mounted on the substrate with high efficiency and high density.

【0010】以下、本発明の電子部品について図面を参
照しながら詳細に説明する。図1に、本発明の電子部品
の一実施態様を示す斜視図を示す。図1の電子部品1
は、電子部品本体11の電極(不図示)上に半田バンプ
12を形成し、この半田バンプ12間の空隙部Pに、半
田バンプ12の先端部が露出するようにアンダーフィル
材13の層を形成したものである。
Hereinafter, the electronic component of the present invention will be described in detail with reference to the drawings. FIG. 1 is a perspective view showing an embodiment of the electronic component of the present invention. Electronic component 1 of FIG.
A solder bump 12 is formed on an electrode (not shown) of the electronic component body 11, and a layer of an underfill material 13 is formed in a gap P between the solder bumps 12 so that the tip of the solder bump 12 is exposed. It is formed.

【0011】ここで使用するアンダーフィル材として
は、後述する本発明の電子部品の作製方法からも理解さ
れるように、常温では固化状態で、所定の温度、例えば
80〜100℃程度に加熱するにより液状となり、さら
に180〜240℃程度に加熱することにより化学反応
を起こし、その後冷却する過程で強力に硬化する材質で
ある必要がある。このような特徴を持たせるためには、
融点の異なる2つの樹脂を含有させればよい。一例を示
せば、低融点樹脂としては水酸基を有する樹脂、例えば
融点が80〜100℃程度となるように分子量を調節し
たポリエチレングリコールやポリプロピレングリコール
などが挙げられる。一方、高融点樹脂としては、例えば
カルボキシル基を有する高級カルボン酸化合物などが挙
げられる。
The underfill material used here is heated to a predetermined temperature, for example, about 80 to 100 ° C. in a solidified state at normal temperature, as understood from the method for manufacturing an electronic component of the present invention described later. Therefore, it is necessary that the material be a material that becomes liquid, further causes a chemical reaction when heated to about 180 to 240 ° C., and hardens strongly in a process of cooling thereafter. In order to have such features,
What is necessary is just to contain two resins with different melting points. As an example, examples of the low melting point resin include a resin having a hydroxyl group, for example, polyethylene glycol or polypropylene glycol whose molecular weight is adjusted so that the melting point is about 80 to 100 ° C. On the other hand, examples of the high melting point resin include a higher carboxylic acid compound having a carboxyl group.

【0012】アンダーフィル材には、半田バンプ同士が
短絡する、いわゆる半田ブリッジの発生を防止するため
にフラックス剤を添加しておくことが推奨される。フラ
ックス剤を添加しておくと、アンダーフィル材と半田の
双方が溶融した場合でもまったく両者は融合せず、半田
ブリッジの発生が防止される。フラックス剤としては従
来公知のものが使用でき、例えばロジン系フラックス剤
などが使用できる。
It is recommended that a flux agent be added to the underfill material in order to prevent a short circuit between the solder bumps, that is, a so-called solder bridge. When the flux agent is added, even if both the underfill material and the solder are melted, they are not fused at all, and the occurrence of a solder bridge is prevented. A conventionally known flux agent can be used, and for example, a rosin-based flux agent and the like can be used.

【0013】アンダーフィル材には、電子部品本体や基
板の熱膨張係数に近づけるために、炭酸カルシウムや石
英粉、炭化シリコン、窒化シリコンなどの熱膨張係数の
小さい無機材料を分散添加してもよい。添加量としては
無添加アンダーフィル材100重量部に対して50重量
部以下が好ましい。また応力集中や歪みを緩和するため
にポリブタジエンやシリコン等のゴム粒子を分散添加し
てもよい。添加量としては無添加アンダーフィル材10
0重量部に対して20重量部以下が好ましい。
An inorganic material having a small thermal expansion coefficient, such as calcium carbonate, quartz powder, silicon carbide, or silicon nitride, may be added to the underfill material in order to approximate the thermal expansion coefficient of the electronic component body or the substrate. . The amount of addition is preferably 50 parts by weight or less based on 100 parts by weight of the unfilled underfill material. Further, rubber particles such as polybutadiene and silicon may be dispersed and added to alleviate stress concentration and strain. The additive amount is as follows.
It is preferably 20 parts by weight or less based on 0 parts by weight.

【0014】基板と電子部品との隙間は一般に30〜9
0μmの範囲であるから、電子部品本体と基板とを導通
可能に接続する半田バンプはこの程度の高さであること
が必要である。またアンダーフィル材表面から露出する
半田バンプ先端部の高さは、基板表面に形成された電極
に半田バンプが接触できる程度であって、半田バンプの
材質や形状、基板電極の形状などを考慮し適宜決定すれ
ばよく、例えば1〜10μm程度である。一方、半田バ
ンプ先端部がアンダーフィル表面に過剰に露出している
と、電子部品と基板との空隙部が広くなり電子部品に設
けたアンダーフィル材で空隙部を充分に充填できなくな
るおそれがある。
The gap between the substrate and the electronic component is generally 30 to 9
Since the thickness is within the range of 0 μm, the height of the solder bumps for connecting the electronic component body and the substrate in a conductive manner needs to be about this height. The height of the tip of the solder bump exposed from the surface of the underfill material is such that the solder bump can contact the electrode formed on the surface of the board, and the material and shape of the solder bump and the shape of the board electrode are taken into consideration. It may be appropriately determined, for example, about 1 to 10 μm. On the other hand, if the tip portion of the solder bump is excessively exposed on the underfill surface, the gap between the electronic component and the substrate becomes large, and the gap may not be sufficiently filled with the underfill material provided in the electronic component. .

【0015】電子部品本体に半田バンプを形成するには
従来公知の方法を用いればよく、例えばウエハの回路素
子表面の全面に半田となじみのよい金属を蒸着法あるい
はスパッタ法でメタライズした後、所定の電極位置に半
田をマスク蒸着する方法や、電解めっきを施して半田バ
ンプを形成する方法を用いることができる。半田バンプ
の形状としては特に限定はなく、球状、鼓状、円柱など
従来公知の形状が挙げられる。また使用する半田の組成
としては例えばPb-Sn、Pb-Ag、Bi-Sn、Zn-Cd、Pb-Sn-Sbなど
従来公知のものが挙げられる。中でも耐熱疲労性に優れ
ることからPb-5%Sn、Pb-60%Sn、Sn-3.5%Agが好ましい。
A known method may be used to form solder bumps on the electronic component body. For example, after a metal that is compatible with solder is metallized on the entire surface of the circuit element surface of the wafer by vapor deposition or sputtering, a predetermined method is used. A method in which solder is vapor-deposited at the electrode positions described above, or a method in which electrolytic plating is performed to form solder bumps can be used. The shape of the solder bump is not particularly limited, and may be a conventionally known shape such as a sphere, a drum, or a cylinder. As the composition of the solder to be used, for example, conventionally known solders such as Pb-Sn, Pb-Ag, Bi-Sn, Zn-Cd, and Pb-Sn-Sb are exemplified. Among them, Pb-5% Sn, Pb-60% Sn, and Sn-3.5% Ag are preferable because of their excellent thermal fatigue resistance.

【0016】本発明の電子部品を実装する基板としては
特に限定はなく、例えばガラスやセラミック材料からな
る単一基板、ガラス繊維含有エポキシ、ガラス繊維含有
ポリイミド、高弾性率高強度繊維を含有するエポキシ又
はポリイミドなどが挙げられる。また基板上に形成する
電極端子は、Au,Ag,Cu,Al,Ni又は半田か
らなる金属の1又は2種類以上を組み合わせて使用すれ
ばよく、この中でもスクリーン印刷などの方法で容易に
形成できる点からクリーム状の半田(以下「クリーム半
田」と記すことがある)が好適に使用できる。
The substrate on which the electronic component of the present invention is mounted is not particularly limited. For example, a single substrate made of glass or ceramic material, epoxy containing glass fiber, polyimide containing glass fiber, epoxy containing high modulus and high strength fiber Or polyimide. In addition, the electrode terminals formed on the substrate may be used in combination of one or more of Au, Ag, Cu, Al, Ni or a metal made of solder, and among them, it can be easily formed by a method such as screen printing. From the viewpoint, creamy solder (hereinafter sometimes referred to as “cream solder”) can be preferably used.

【0017】次に、本発明の電子部品の作製方法につい
て説明する。図2に、本発明に係る電子部品の作製方法
の一例を示す工程図を示す。まず、一面側に半田バンプ
12を形成した電子部品本体11を、電子部品本体11
の外形と一致する平面形状を有し前記本体の高さよりも
深い凹部41を有する治具4に装着する(同図
(イ))。そして、この治具4の凹部41にアンダーフ
ィル材13を流し込む(同図(ロ))。ここでアンダー
フィル材13は、低融点物質13a、高融点物質13
b、フラックス剤(不図示)を含み、低融点物質の融点
以上、高融点物質の融点未満、例えば80〜100℃程
度に加熱されていて、溶融してコロイド状となった低融
点物質13a中に微粒状の高融点物質13bが分散した
状態となっている。またアンダーフィル材13の流し込
み量は、電子部品本体11に形成された半田バンプ12
の先端部が浸漬しない程度である。同図のA−A線断面
図を合わせて示す。アンダーフィル材13の流し込みが
完了すると、そのままの状態で常温(18〜25℃程
度)までゆっくりと冷却する。そしてアンダーフィル材
13が固化したら、治具4から電子部品1を取り出す
(同図(ハ))。
Next, a method for manufacturing an electronic component according to the present invention will be described. FIG. 2 is a process chart showing an example of a method for manufacturing an electronic component according to the present invention. First, the electronic component body 11 having the solder bumps 12 formed on one surface side is attached to the electronic component body 11.
The jig 4 is mounted on a jig 4 having a planar shape that matches the outer shape of (a) and having a concave portion 41 that is deeper than the height of the main body ((a) in the figure). Then, the underfill material 13 is poured into the concave portion 41 of the jig 4 (FIG. 2B). Here, the underfill material 13 is composed of the low-melting substance 13 a and the high-melting substance 13.
b, which contains a fluxing agent (not shown) and is heated to the melting point of the low-melting substance or higher and lower than the melting point of the high-melting substance, for example, about 80 to 100 ° C. In a state in which fine-grained high melting point material 13b is dispersed. The amount of the underfill material 13 to be poured is determined by the solder bumps 12 formed on the electronic component body 11.
Is not soaked at the tip. A sectional view taken along line AA of FIG. When the pouring of the underfill material 13 is completed, the underfill material 13 is cooled slowly to room temperature (about 18 to 25 ° C.) in the state as it is. When the underfill material 13 is solidified, the electronic component 1 is taken out of the jig 4 (FIG. 3C).

【0018】このようにして作製した本発明の電子部品
を基板に実装するには、例えば次のようにして行う。図
3は、本発明の電子部品の基板への実装を示す工程図で
ある。基板2の電極端子上に塗布された半田クリーム2
1に、半田バンプ12が対向するように電子部品1を位
置させる(同図(ニ))。そして電子部品1を基板2上
に載置すると、半田バンプ12が半田クリーム21にめ
り込んだ状態となる(同図(ホ))。この状態で基板2
をリフロー炉に入れて加熱する。基板2が80〜100
℃程度にまで加熱されると、まず低融点物質13aが溶
融してアンダーフィル材13が流動し電子部品本体11
と基板2との空隙部Pに充填する(同図(ヘ))。この
ときアンダーフィル材13に含有されているフラックス
剤(不図示)も同時に溶融するが、高融点物質13bは
微粒状のまま低融点物質13a中に分散している。そし
てさらに加熱されて高融点物質の融点以上、例えば18
0〜240℃程度になると高融点物質13bが溶融して
低融点物質13aと液状で接触する。また半田バンプ1
2及び半田クリーム21も溶融して両者は融合して半田
Sとなる(同図(ト))。なお、アンダーフィル材13
および半田Sは溶融した状態であっても融合することは
ない。またアンダーフィル材13中のフラックス剤の作
用により、隣り合う半田バンプ12が接触して融合する
ことはない。次に、基板2をゆっくり常温まで冷却する
(同図(チ))。アンダーフィル材13および半田S
は、それぞれの融点以下に基板2の温度が下がると固化
する。この結果、電子部品本体11と基板2とは半田S
を介して確実・強固に接続され、且つ空隙部Pはアンダ
ーフィル材13で隙間なく充填されるのである。
The electronic component of the present invention thus manufactured is mounted on a substrate, for example, as follows. FIG. 3 is a process chart showing the mounting of the electronic component of the present invention on a substrate. Solder cream 2 applied on electrode terminals of substrate 2
1, the electronic component 1 is positioned so that the solder bumps 12 face each other (FIG. 4D). Then, when the electronic component 1 is mounted on the substrate 2, the solder bumps 12 are immersed in the solder cream 21 (FIG. 4E). In this state, the substrate 2
In a reflow oven and heated. Substrate 2 is 80-100
When heated to about ° C., the low-melting substance 13a first melts and the underfill material 13 flows, and the electronic component body 11
The space P between the substrate and the substrate 2 is filled (FIG. 6F). At this time, the flux agent (not shown) contained in the underfill material 13 is also melted at the same time, but the high melting point material 13b is dispersed in the low melting point material 13a as fine particles. Then, it is further heated to a temperature higher than the melting point of the high melting point material, for example, 18
When the temperature reaches about 0 to 240 ° C., the high-melting substance 13b is melted and comes into liquid contact with the low-melting substance 13a. Also solder bump 1
2 and the solder cream 21 are also melted, and the two are fused to form a solder S ((g) in the figure). The underfill material 13
Even when the solder S is in a molten state, it does not fuse. Further, due to the action of the flux agent in the underfill material 13, the adjacent solder bumps 12 do not come into contact with each other and fuse. Next, the substrate 2 is slowly cooled to room temperature (FIG. 9H). Underfill material 13 and solder S
Solidifies when the temperature of the substrate 2 falls below the respective melting points. As a result, the electronic component body 11 and the board 2
And the gap P is filled with the underfill material 13 without gaps.

【0019】以上説明した本発明の電子部品の作製方法
および基板への実装方法の各工程におけるアンダーフィ
ル材および半田、フラックス剤の状態変化をまとめて表
1に示す。
Table 1 summarizes the state changes of the underfill material, the solder, and the flux agent in each step of the above-described method of manufacturing the electronic component and the method of mounting on the substrate according to the present invention.

【0020】[0020]

【表1】 [Table 1]

【0021】表1において、アンダーフィル材で電子部
品の一面側を被覆する工程(ロ)では、低融点物質およ
びフラックス剤が液状となり、微粒状の高融点物質を含
有した状態で前記一面側を流動し充満する。そして常温
まで冷却する工程(ハ)では、低融点物質およびフラッ
クス剤も固化し、電子部品本体の一面側をアンダーフィ
ル材で被覆した状態となる。本発明の電子部品はこの状
態で保管・輸送などがなされる。
In Table 1, in the step (b) of coating one surface of the electronic component with the underfill material, the low-melting substance and the fluxing agent are turned into a liquid state, and the one-side is coated with the fine high-melting substance. Flow and charge. Then, in the step (c) of cooling to room temperature, the low-melting-point substance and the flux agent are also solidified, and one side of the electronic component body is covered with an underfill material. The electronic component of the present invention is stored and transported in this state.

【0022】そして電子部品を基板に実装する段階にお
いて、基板上に塗布された半田クリームに半田バンプを
対向させて、電子部品を基板上に載置する工程(ニ)、
工程(ホ)では、高融点物質および低融点物質、フラッ
クス剤、半田バンプ、半田クリームのいずれも固化状態
である。次に約80〜100℃に加熱する工程(ヘ)で
は、低融点物質およびフラックス剤が液状となり空隙部
にアンダーフィル材が流動・充満する。そして約180
〜240℃にまで加熱する工程(ト)では、高融点物質
および半田バンプ、半田クリームもが液状となり、高融
点物質と低融点物質および半田バンプと半田クリームが
それぞれ液状で混合し、高融点物質と低融点物質との接
触で強い接合力が生じ、半田バンプと半田クリームとは
均一に融合する。そして常温まで冷却する工程(チ)で
は、高融点物質および低融点物質、フラックス剤、半田
バンプ、半田クリームのいずれもが再び固化状態とな
り、高融点物質と低融点物質との液状接触により強い接
着力が生じ、半田バンプと半田クリームとは一体化して
確実・強固な接続となる。
In the step of mounting the electronic component on the substrate, a step (d) of placing the electronic component on the substrate with the solder bumps facing the solder cream applied on the substrate;
In the step (e), the high-melting substance and the low-melting substance, the flux agent, the solder bumps, and the solder cream are all in a solidified state. Next, in the step (f) of heating to about 80 to 100 ° C., the low-melting substance and the flux agent become liquid, and the underfill material flows and fills the voids. And about 180
In the step (g) of heating to up to 240 ° C., the high melting point material, the solder bumps, and the solder cream also become liquid, and the high melting point material and the low melting point material, and the solder bumps and the solder cream are mixed in a liquid state respectively. A strong bonding force is generated by contact between the solder bump and the low melting point material, and the solder bump and the solder cream are uniformly fused. Then, in the step (h) of cooling to room temperature, all of the high-melting substance and the low-melting substance, the flux agent, the solder bumps, and the solder cream are again solidified, and the high-melting substance and the low-melting substance are strongly bonded by liquid contact. A force is generated, and the solder bump and the solder cream are integrated into a reliable and strong connection.

【0023】次に、本発明に係る電子部品の他の実施態
様を示す。図4は、本発明に係る電子部品の他の実施形
態を示す斜視図である。図1に示した電子部品と違う点
は、電子部品本体11の側面をもアンダーフィル材13
で被覆した点である。
Next, another embodiment of the electronic component according to the present invention will be described. FIG. 4 is a perspective view showing another embodiment of the electronic component according to the present invention. The difference from the electronic component shown in FIG.
This is the point covered with.

【0024】このような電子部品の作製方法の一例を図
5に示す。図5は、作製方法の概略工程図であり、図2
で示した工程図との違いは、工程(イ)において、電子
部品本体11を収容する凹部41の平面形状が、電子部
品本体11の平面形状よりも大きい点である。これによ
り、電子部品本体11を凹部41に収容したときに電子
部品本体11と凹部41の周壁との間に所定の隙間がで
きる。アンダーフィル材13をこの凹部41に注ぐと前
記隙間にもアンダーフィル材13が充填され、これを冷
却固化した後電子部品1を治具から取り出すと、図4に
示すような電子部品本体11の半田バンプ12の形成面
および側面がアンダーフィル材13で被覆された電子部
品1ができる。
FIG. 5 shows an example of a method for manufacturing such an electronic component. FIG. 5 is a schematic process diagram of the manufacturing method, and FIG.
The difference from the process diagram shown in FIG. 13 is that the planar shape of the concave portion 41 that accommodates the electronic component body 11 is larger than the planar shape of the electronic component body 11 in the process (a). Thereby, when the electronic component main body 11 is accommodated in the concave portion 41, a predetermined gap is formed between the electronic component main body 11 and the peripheral wall of the concave portion 41. When the underfill material 13 is poured into the concave portion 41, the gap is also filled with the underfill material 13, and after cooling and solidifying, the electronic component 1 is taken out of the jig. The electronic component 1 in which the formation surface and the side surface of the solder bump 12 are covered with the underfill material 13 is obtained.

【0025】この電子部品1を基板2に実装する場合の
工程図の一例を図6に示す。図6に示す実装方法は図3
に示したものと機構は同じであるのでその説明は省略
し、異なる点のみ説明する。すなわち、電子部品本体1
1の側面を被覆したアンダーフィル材13は、リフロー
炉での加熱により溶融して基板2上に流動し、電子部品
本体11の側面と基板2とのフィレット(すみ肉)Fを
形成する。これにより電子部品1の基板2への接着強度
が向上し、電子部品1が基板2から剥離することが有効
に防止される。
FIG. 6 shows an example of a process diagram when the electronic component 1 is mounted on the substrate 2. The mounting method shown in FIG.
Since the mechanism is the same as that described above, the description thereof will be omitted, and only different points will be described. That is, the electronic component body 1
The underfill material 13 covering the side surface of the electronic component 1 is melted by heating in a reflow furnace and flows on the substrate 2 to form a fillet F between the side surface of the electronic component body 11 and the substrate 2. Thereby, the bonding strength of the electronic component 1 to the substrate 2 is improved, and the electronic component 1 is effectively prevented from peeling off from the substrate 2.

【0026】[0026]

【発明の効果】本発明の電子部品では、半田バンプの先
端部が露出するように電子部品本体の一面側にアンダー
フィル材が予め形成されているので、電子部品を基板に
装着した後のアンダーフィル材の充填作業が不要とな
り、電子部品の生産性が大幅に向上すると共に、他の電
子部品を基板上に高効率・高密度に実装できる。またア
ンダーフィル材は空隙部に隙間なく充填されているの
で、電子部品を基板に強固に接着できる。
According to the electronic component of the present invention, the underfill material is previously formed on one surface of the electronic component body so that the tip of the solder bump is exposed. The work of filling the fill material is not required, and the productivity of electronic components is greatly improved, and other electronic components can be mounted on the substrate with high efficiency and high density. In addition, since the underfill material is filled in the gap without any gap, the electronic component can be firmly bonded to the substrate.

【0027】また、電子部品本体の側面をもアンダーフ
ィル材で被覆すれば、基板に実装する際に溶融してフィ
レットとなり電子部品の接着強度が大きくなる。
Further, if the side surface of the electronic component body is also covered with the underfill material, the electronic component melts and becomes a fillet when mounted on a substrate, thereby increasing the adhesive strength of the electronic component.

【0028】アンダーフィル材が融点の異なる2以上の
樹脂を含んでいると、電子部品の作製が容易となり、ま
た電子部品を基板により強固に接着できる。
When the underfill material contains two or more resins having different melting points, the production of electronic components becomes easy, and the electronic components can be more firmly bonded to the substrate.

【0029】またアンダーフィル材がフラックス剤を含
んでいると、電子部品の実装時に溶融した半田バンプ同
士が接触し短絡する半田ブリッジを有効に防止できる。
Further, when the underfill material contains a flux agent, it is possible to effectively prevent a solder bridge in which molten solder bumps come into contact with each other at the time of mounting an electronic component and short-circuit occurs.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明に係る電子部品の一実施態様を示す斜
視図である。
FIG. 1 is a perspective view showing an embodiment of an electronic component according to the present invention.

【図2】 図1の電子部品の作製方法の一例を示す工程
図である。
FIG. 2 is a process chart illustrating an example of a method for manufacturing the electronic component in FIG.

【図3】 図1の電子部品の基板への実装の一例を示す
工程図である。
FIG. 3 is a process chart showing an example of mounting the electronic component of FIG. 1 on a substrate.

【図4】 本発明に係る電子部品の他の実施態様を示す
斜視図である。
FIG. 4 is a perspective view showing another embodiment of the electronic component according to the present invention.

【図5】 図4の電子部品の作製方法の一例を示す工程
図である。
5 is a process chart showing an example of a method for manufacturing the electronic component in FIG.

【図6】 図4の電子部品の基板への実装の一例を示す
工程図である。
6 is a process chart showing an example of mounting the electronic component of FIG. 4 on a substrate.

【図7】 従来の電子部品の基板への実装を示す工程図
である。
FIG. 7 is a process chart showing a conventional mounting of an electronic component on a substrate.

【符号の説明】[Explanation of symbols]

1 電子部品 2 基板 11 電子部品本体 12 半田バンプ 13 アンダーフィル材 13a 低融点物質 13b 高融点物質 DESCRIPTION OF SYMBOLS 1 Electronic component 2 Substrate 11 Electronic component main body 12 Solder bump 13 Underfill material 13a Low melting material 13b High melting material

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 電子部品本体の一面側に半田バンプを設
け、この半田バンプの先端部が露出するように前記本体
の一面側をアンダーフィル材で被覆したことを特徴とす
る電子部品。
1. An electronic component, wherein a solder bump is provided on one surface side of an electronic component main body, and one surface side of the main body is covered with an underfill material so that a tip end of the solder bump is exposed.
【請求項2】 前記本体の側面をも前記アンダーフィル
材で被覆した請求項1記載の電子部品。
2. The electronic component according to claim 1, wherein a side surface of said main body is also covered with said underfill material.
【請求項3】 前記アンダーフィル材が、融点の異なる
少なくとも2つ樹脂を含んでいる請求項1又は2記載の
電子部品。
3. The electronic component according to claim 1, wherein the underfill material includes at least two resins having different melting points.
【請求項4】 前記アンダーフィル材がフラックス剤を
含む請求項1〜3のいずれかに記載の電子部品。
4. The electronic component according to claim 1, wherein the underfill material contains a flux agent.
JP2001069625A 2001-03-13 2001-03-13 Electronic component with underfill material Pending JP2002270732A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001069625A JP2002270732A (en) 2001-03-13 2001-03-13 Electronic component with underfill material

Publications (1)

Publication Number Publication Date
JP2002270732A true JP2002270732A (en) 2002-09-20

Family

ID=18927639

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2002270732A (en)

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US9773685B2 (en) 2003-11-10 2017-09-26 STATS ChipPAC Pte. Ltd. Solder joint flip chip interconnection having relief structure
US7901983B2 (en) 2004-11-10 2011-03-08 Stats Chippac, Ltd. Bump-on-lead flip chip interconnection
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