JP3890814B2 - Electronic component mounting method - Google Patents
Electronic component mounting method Download PDFInfo
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- JP3890814B2 JP3890814B2 JP14532999A JP14532999A JP3890814B2 JP 3890814 B2 JP3890814 B2 JP 3890814B2 JP 14532999 A JP14532999 A JP 14532999A JP 14532999 A JP14532999 A JP 14532999A JP 3890814 B2 JP3890814 B2 JP 3890814B2
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- solder
- substrate
- electronic component
- solder bump
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
【０００１】
【発明の属する技術分野】
本発明は、基板上にはんだバンプを介して電子部品を搭載する電子部品の実装方法に関し、特に、基板と電子部品との間に、はんだ接合部の強度を向上させるための樹脂材を配置するものに関する。
【０００２】
【従来の技術】
従来、例えば、はんだボールを有するＣＳＰ（チップサイズパッケージ）や半導体素子等の電子部品を、基板（例えばプリント配線基板等）上に搭載する実装構造においては、はんだ接合部の耐落下衝撃性や耐熱疲労性の改善のために、熱硬化性の樹脂材であるアンダーフィル材をはんだの周りに充填させ、はんだ接合強度を向上させていた（例えば、特開平７−６６３２６号公報）。
【０００３】
一般に、このアンダーフィル材の充填方法は、電子部品と基板の一面（例えば電極部）とをはんだ接合した後に、電子部品と基板との間に、液状の熱硬化性樹脂を注入、充填し、熱硬化させていた。
【０００４】
【発明が解決しようとする課題】
しかしながら、上記充填方法では、注入、充填、熱硬化という各工程を行うための注入機や恒温槽が必要となり、且つ、熱硬化させるために、ワークを高温で長時間（例えば、１２０℃、２時間程度）、恒温槽に放置する必要があった。
【０００５】
このため、アンダーフィル材の充填に関わる製造コストが増大するとともに、基板上に他部品（ＬＥＤ、アルミ電解コンデンサ等）が実装されている場合、上記の高温・長時間の熱処理において、耐熱性の弱い他部品の品質が劣化（熱劣化）するという問題があった。
【０００６】
本発明は上記問題に鑑み、基板上にはんだバンプを介して電子部品を搭載するとともに、基板と電子部品との間に樹脂材を配置するようにした電子部品の実装方法において、該樹脂材の充填・硬化に関わる製造コストの低減及び他部品の熱劣化防止を実現することを目的とする。
【０００７】
【課題を解決するための手段】
ところで、この種の実装方法において、はんだバンプのリフロー工程は必然的に行われるが、その加熱時間は、上記した従来の樹脂材の硬化時間に比べて非常に短時間（例えば数分程度）である。本発明は、このリフローによる加熱を利用することで、基板と電子部品との間に配置される樹脂材の熱硬化を、該リフローと同時に行うようにすれば良いのではないかという着想点に基づいてなされたものである。
【０００８】
即ち、請求項１記載の発明では、一面側に突出して形成されたはんだバンプ（１）を有する電子部品（２）を、はんだバンプを介して基板（３）の一面上に搭載する工程（Ｓ２）を行った後、基板の一面上における電子部品の端部に、硬化温度がはんだバンプの溶融温度以上である液状の熱硬化性樹脂（４）を注入する工程（Ｓ３）を行い、この後、電子部品を搭載した基板をリフロー炉に投入し、リフロー炉内において、電子部品の一面と基板の一面との間に熱硬化性樹脂をはんだバンプの溶融温度未満の温度にて充填する工程（Ｓ４）と、この後、はんだバンプの溶融温度以上に加熱することにより、はんだバンプを溶融させて基板の一面に接合するとともに、液状の熱硬化性樹脂を硬化させる工程（Ｓ５）と、を行うことを特徴としている。
【０００９】
本発明によれば、はんだバンプ（１）の溶融・接合工程（Ｓ５）において、液状の熱硬化性樹脂（４）を同時に熱硬化させることができるため、はんだリフローに用いる装置により、樹脂の熱硬化が完了する。また、はんだリフローの加熱は、上述のように、従来の樹脂の熱硬化時間に比べて短時間であるため、基板（３）上に他部品が実装されている場合、該他部品の熱劣化を防止できる。
【００１０】
ここで、本発明のはんだバンプの溶融・接合工程においては、溶融したはんだバンプ（１）と液状の熱硬化性樹脂（４）とが一時的に共存した状態となるが、濡れ性や粘性の相違から、両者が混ざり合うことはない。
【００１１】
よって、本発明によれば、樹脂材の充填・硬化に関わる製造コストの低減及び他部品の熱劣化防止を実現する電子部品の実装方法を提供することができる。
【００１２】
また、接続後のはんだ部分の熱疲労寿命を向上させるためには、硬化後の熱硬化性樹脂（４）がはんだの熱膨張係数に近いことが好ましく、そのようなものとしては、ナフタレン型エポキシ樹脂またはビスフェノールＡ型エポキシ樹脂に、酸無水物系硬化剤を含有させたものが挙げられる。
【００１３】
なお、上記各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示す一例である。
【００１４】
【発明の実施の形態】
以下、本発明を図に示す実施形態について説明する。図１は、本発明の実施形態に係る電子部品の実装方法を示す工程図であり、実装される基板面と直交する方向の概略断面を示す。図１において、（ａ）〜（ｄ）は、最終的に図１（ｅ）に示す実装構造を作るための実装工程の途中状態を示すものである。
【００１５】
図１（ｅ）に示す実装構造は、一面側に突出して形成されたはんだバンプ１を有するＣＳＰ（本発明でいう電子部品）２を、はんだバンプ１を介してプリント配線基板（本発明でいう基板、以下、単に基板という）３の一面側に形成された電極部３ａ上に電気的に接続したものである。なお、図中の符号２ａは、はんだバンプ１と導通するＣＳＰ２の電極部である。
【００１６】
ここで、詳しく図示しないが、ＣＳＰ２は、通常知られているもの、例えば樹脂によってインターポーザ表面に搭載された半導体チップを内包したパッケージであって、インターポーザ裏面においてスルーホール等によって上記半導体チップと導通する上記電極部２ａ上に、例えばＳｎ／Ｐｂ等のはんだ材料よりなるはんだバンプ１をアレイ状に配置したものを採用できる。
【００１７】
また、基板３及びその電極部３ａについても、通常用いられるものを採用でき、例えば、基板３としては、樹脂よりなるプリント配線基板の他にもセラミック配線基板等を採用でき、電極部３ａとしては、金属めっき材料、導体厚膜及び金属（銅等）箔等を採用できる。
【００１８】
そして、該実装構造においては、ＣＳＰ２の一面と基板３の一面との間において、はんだバンプ１以外の部分を埋めるように、硬化されたアンダーフィル材（本発明でいう熱硬化性樹脂）４が充填されている。このアンダーフィル材４は、はんだの熱膨張係数（例えば２６ｐｐｍ／℃）とほぼ等しく、弾性率が３４００ＭＰａ以上の物性を有する熱硬化性樹脂よりなり、ガラスフィラー入りエポキシ樹脂等が該当する。
【００１９】
また、このアンダーフィル材４のエポキシ樹脂としては、約６０〜７０℃（アンダーフィル材充填温度）で、最も低粘度（５００ｍＰａ・ｓ程度）となり、且つ、後述のリフロープロファイルによる加熱工程（例えば４〜８分）においてはんだバンプ１の溶融温度以上で硬化する特性を有するもの、例えば、酸無水物系硬化材を使ったナフタレン型エポキシ樹脂やビスフェノールＡ型エポキシ樹脂等を使用することができる。
【００２０】
次に、かかる図１（ｅ）に示す実装構造を実現する実装方法について工程順に説明していく。
【００２１】
まず、図１（ａ）に示す工程では、基板３の一面側に形成された電極部３ａ上に、はんだ印刷機（図示せず）を使って、はんだペースト５を印刷し、転写する（はんだペースト印刷工程Ｓ１）。
【００２２】
次に、図１（ｂ）に示す工程では、はんだバンプ１が一面側に形成されたＣＳＰ２を用意する。このはんだバンプ１は基板３の電極部３ａに対応して形成されている。そして、部品装着マウンタ（図示せず）を用いて、このマウンタの吸着ノズル６にＣＳＰ２の他面側を吸着固定する。次に、吸着されたＣＳＰ２の一面側と基板３の一面側とを対向させ、はんだバンプ１と電極部３ａとが接するように、ＣＳＰ２を基板３の一面上にマウント（搭載）する（電子部品搭載工程Ｓ２）。
【００２３】
次に、図１（ｃ）に示す工程では、アンダーフィル注入用のディスペンサ７により、基板３の一面上におけるＣＳＰ２の端部に、液状のアンダーフィル材４を注入する（アンダーフィル材注入工程Ｓ３）。
【００２４】
次に、図１（ｄ）に示す工程では、ＣＳＰ２をマウントした基板３を、はんだリフロー用のリフロー炉に投入し、図２に示す様な温度条件（リフロープロファイル）により、アンダーフィル材４の充填及びはんだ付けを行う。
【００２５】
図２に示すリフロープロファイルにおいて、約６０℃で所定時間（例えば数十秒）一定とする領域Ｐ１は、アンダーフィル材４をＣＳＰ２と基板３との間に充填させるための領域（アンダーフィル材充填領域）であり、約１５０℃で所定時間（例えば百秒程度）一定とする領域Ｐ２は、予熱領域であり、１８３℃以上で所定時間（例えば百秒程度）維持する領域Ｐ３は、本加熱領域である。また、図２中の点Ｔ１は、はんだ溶融点（はんだバンプ１の溶融温度）、点Ｔ２は、はんだ凝固点である。
【００２６】
まず、アンダーフィル材充填領域Ｐ１では、アンダーフィル材４が最も低粘度となるため、毛細管現象により、ＣＳＰ２と基板３との間にほぼ完全に充填する（アンダーフィル材充填工程Ｓ４）。このとき、はんだペースト５の粘度は、１８００００ｍＰａ・ｓ程度であるため、液状のアンダーフィル材４によってはんだペースト５が押し流されることはない。なお、この領域Ｐ１は、例えば６０〜７０℃で、２０〜６０秒程度とできる。
【００２７】
そして、アンダーフィル材充填領域Ｐ１から炉内温度を上昇させ、予熱領域Ｐ２に入る。ここで、領域Ｐ１からいきなり本加熱領域Ｐ３に入ると、基板や各部品が熱衝撃を受け、品質劣化を生じる。予熱領域Ｐ２は、このような熱衝撃を防止するために設けられたものである。そして、さらに炉内温度を上昇させ、予熱領域Ｐ２から、はんだのリフロー工程に相当する本加熱領域Ｐ３に入る。
【００２８】
はんだ溶融点Ｔ１を越えて、本加熱領域Ｐ３に入ると、はんだペースト５とはんだバンプ１とが溶融する。その後、炉内温度を降下させ、冷却領域に入り、はんだ凝固点Ｔ２に達すると、はんだ接合が完了する。
【００２９】
また、本加熱領域Ｐ３においては、はんだ溶融点Ｔ３を過ぎたところで、アンダーフィル材４が硬化する。ここで、アンダーフィル材４の硬化完了は、はんだ溶融点Ｔ３を過ぎたところであれば、セルフアライメントが保証されるため、本加熱領域Ｐ３のどの時点でも構わない。
【００３０】
ここで、本加熱領域Ｐ３がはんだの溶融・接合及びアンダーフィル材の硬化を行う工程（溶融・接合及び硬化工程Ｓ５）となる。この工程Ｓ５中、溶融したはんだバンプ１と液状のアンダーフィル材４とが一時的に共存した状態となるが、樹脂と金属との濡れ性や粘性の相違から、両者が混ざり合うことはない。
【００３１】
こうして、上記の各工程Ｓ１〜Ｓ５を経て、図１（ｅ）に示す実装構造が出来上がる。
【００３２】
ところで、本実施形態によれば、溶融・接合及び硬化工程Ｓ５において、液状のアンダーフィル材４を同時に熱硬化させることができるため、はんだリフロー用のリフロー炉を用いて、アンダーフィル材４の熱硬化を完了させることができる。
【００３３】
また、上記リフロープロファイルによる加熱時間は例えば４〜８分であり、さらにはんだリフローの加熱（本加熱領域Ｐ３）は例えば１００秒程度であり、従来の樹脂の熱硬化時間（約２時間）に比べて短時間の加熱で済むため、基板３上にＣＳＰ２以外の他部品が実装されている場合、該他部品の熱劣化を防止できる。
【００３４】
よって、本実施形態によれば、アンダーフィル材の充填・硬化に関わる製造コストの低減及び他部品の熱劣化防止を実現する電子部品の実装方法を提供することができる。
【００３５】
また、本実施形態によれば、アンダーフィル材４として、はんだの熱膨張係数に近い材料を選定しているため、実装構造において、はんだ部の熱疲労寿命を向上させることができる。
【００３６】
また、本実施形態では、一面側に突出して形成されたはんだバンプ１を有するＣＳＰ２を、はんだバンプ１と基板３の電極部３ａとがはんだペースト５を介して接するように、基板３の一面上に搭載した後に、両部材２、３間に液状のアンダーフィル材４を注入するから、はんだバンプ１とはんだペースト５と基板３の電極部３ａとの間に、アンダーフィル材４が入り込むことが殆ど無く、確実な接続が得られる。
【００３７】
なお、他部品の搭載は、リフロー炉に投入する前のいつの時点でも良い。例えば、ＣＳＰ２を搭載する前に基板１に実装されていても良いし、ＣＳＰ２の搭載工程Ｓ２中に行っても良いし、ＣＳＰ２の搭載後に行っても良い。
【００３８】
また、電子部品としては、ＣＳＰ以外にも、一面側に突出して形成されたはんだバンプを有するものであれば何でも良い。
【図面の簡単な説明】
【図１】本発明の実施形態に係る電子部品の実装方法を示す工程図である。
【図２】上記実装方法におけるリフロープロファイルを示す図である。
【符号の説明】
１…はんだバンプ、２…ＣＳＰ（チップサイズパッケージ）、
３…プリント配線基板、４…アンダーフィル材、Ｓ２…電子部品搭載工程、
Ｓ３…アンダーフィル材注入工程、Ｓ４…アンダーフィル材充填工程、
Ｓ５…溶融・接合及び硬化工程。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic component mounting method for mounting an electronic component on a substrate via a solder bump, and in particular, a resin material for improving the strength of a solder joint is disposed between the substrate and the electronic component. About things.
[0002]
[Prior art]
Conventionally, for example, in a mounting structure in which an electronic component such as a CSP (chip size package) having a solder ball or a semiconductor element is mounted on a substrate (for example, a printed wiring board), the drop impact resistance or heat resistance of the solder joint portion is used. In order to improve fatigue, an underfill material, which is a thermosetting resin material, is filled around the solder to improve the solder joint strength (for example, JP-A-7-66326).
[0003]
In general, the underfill material filling method includes injecting and filling a liquid thermosetting resin between the electronic component and the substrate after soldering the electronic component and one surface of the substrate (for example, the electrode portion), It was heat cured.
[0004]
[Problems to be solved by the invention]
However, the above filling method requires an injecting machine and a thermostatic bath for performing the steps of pouring, filling, and thermosetting, and the workpiece is kept at a high temperature for a long time (for example, 120 ° C., 2 ° C.). It was necessary to leave it in a thermostatic bath for about an hour).
[0005]
For this reason, the manufacturing cost related to the filling of the underfill material is increased, and when other components (LED, aluminum electrolytic capacitor, etc.) are mounted on the substrate, the heat resistance can be improved in the above-described high-temperature and long-time heat treatment. There was a problem that the quality of other weak parts deteriorated (thermal deterioration).
[0006]
In view of the above problems, the present invention provides an electronic component mounting method in which an electronic component is mounted on a substrate via a solder bump and a resin material is disposed between the substrate and the electronic component. The purpose is to reduce the manufacturing cost related to filling and curing and to prevent thermal deterioration of other parts.
[0007]
[Means for Solving the Problems]
By the way, in this type of mounting method, the solder bump reflow process is inevitably performed, but the heating time is very short (for example, about several minutes) compared to the curing time of the conventional resin material described above. is there. The present invention is based on the idea that the heat curing of the resin material disposed between the substrate and the electronic component may be performed simultaneously with the reflow by using the heating by the reflow. It was made based on.
[0008]
That is, according to the first aspect of the present invention, the step of mounting the electronic component (2) having the solder bump (1) formed so as to protrude on the one surface side on the one surface of the substrate (3) via the solder bump (S2). ) , A step (S3) of injecting a liquid thermosetting resin (4) having a curing temperature equal to or higher than the melting temperature of the solder bumps to the edge of the electronic component on one surface of the substrate is performed. The step of charging the substrate on which the electronic component is mounted into the reflow furnace, and filling the thermosetting resin at a temperature lower than the melting temperature of the solder bump between one surface of the electronic component and one surface of the substrate in the reflow furnace ( performing a S4), thereafter, by heating above the melting temperature of the solder bumps, by melting the solder bumps as well as bonded to one surface of the substrate, and curing the thermosetting resin liquid (S5), the As a feature That.
[0009]
According to the present invention, since the liquid thermosetting resin (4) can be simultaneously cured in the melting / joining step (S5) of the solder bump (1), the heat of the resin can be obtained by the apparatus used for solder reflow. Curing is complete. Also, since the solder reflow heating is shorter than the conventional resin thermosetting time, as described above, when other components are mounted on the substrate (3), the other components are thermally deteriorated. Can be prevented.
[0010]
Here, in the melting / joining process of the solder bump of the present invention, the molten solder bump (1) and the liquid thermosetting resin (4) are in a coexisting state. Because of the differences, the two do not mix.
[0011]
Therefore, according to the present invention, it is possible to provide a method for mounting an electronic component that realizes a reduction in manufacturing cost related to filling and curing of a resin material and prevention of thermal deterioration of other components.
[0012]
Moreover, in order to improve the thermal fatigue life of the solder part after connection, it is preferable that the thermosetting resin (4) after curing is close to the thermal expansion coefficient of the solder, such as naphthalene type epoxy A resin or a bisphenol A type epoxy resin containing an acid anhydride curing agent may be mentioned.
[0013]
In addition, the code | symbol in the bracket | parenthesis of each said means is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments shown in the drawings will be described below. FIG. 1 is a process diagram showing a method for mounting an electronic component according to an embodiment of the present invention, and shows a schematic cross section in a direction orthogonal to the board surface to be mounted. In FIG. 1, (a)-(d) shows the intermediate state of the mounting process for finally making the mounting structure shown in FIG.1 (e).
[0015]
The mounting structure shown in FIG. 1 (e) has a CSP (electronic component in the present invention) 2 having a solder bump 1 formed so as to protrude on one side, and a printed wiring board (in the present invention) through the solder bump 1. A substrate (hereinafter, simply referred to as a substrate) is electrically connected to an electrode portion 3a formed on one surface side. Note that reference numeral 2 a in the drawing denotes an electrode portion of the CSP 2 that is electrically connected to the solder bump 1.
[0016]
Here, although not shown in detail, the CSP 2 is a generally known package, for example, a package containing a semiconductor chip mounted on the surface of the interposer by resin, and is electrically connected to the semiconductor chip by a through hole or the like on the back surface of the interposer. For example, an array of solder bumps 1 made of a solder material such as Sn / Pb can be used on the electrode portion 2a.
[0017]
Also, as the substrate 3 and its electrode part 3a, those commonly used can be adopted. For example, as the substrate 3, a ceramic wiring board or the like can be adopted in addition to a printed wiring board made of resin, and as the electrode part 3a, Metal plating materials, conductive thick films, metal (copper, etc.) foils, etc. can be used.
[0018]
In the mounting structure, a cured underfill material (thermosetting resin referred to in the present invention) 4 is embedded between one surface of the CSP 2 and one surface of the substrate 3 so as to fill a portion other than the solder bumps 1. Filled. The underfill material 4 is made of a thermosetting resin having a physical expansion coefficient approximately equal to the thermal expansion coefficient (for example, 26 ppm / ° C.) of the solder and an elastic modulus of 3400 MPa or more, and corresponds to an epoxy resin containing a glass filler.
[0019]
Further, the epoxy resin of the underfill material 4 has a temperature of about 60 to 70 ° C. (underfill material filling temperature), the lowest viscosity (about 500 mPa · s), and a heating process (for example, 4) ˜8 minutes) can be used, for example, a naphthalene type epoxy resin or a bisphenol A type epoxy resin using an acid anhydride-based curing material.
[0020]
Next, a mounting method for realizing the mounting structure shown in FIG.
[0021]
First, in the process shown in FIG. 1A, a solder paste 5 is printed and transferred onto an electrode portion 3a formed on one surface side of a substrate 3 using a solder printer (not shown) (solder). Paste printing step S1).
[0022]
Next, in the step shown in FIG. 1B, a CSP 2 having a solder bump 1 formed on one side is prepared. The solder bump 1 is formed corresponding to the electrode portion 3 a of the substrate 3. Then, by using a component mounting mounter (not shown), the other surface side of the CSP 2 is suction fixed to the suction nozzle 6 of the mounter. Next, the CSP 2 is mounted (mounted) on one surface of the substrate 3 so that the one surface side of the adsorbed CSP 2 and the one surface side of the substrate 3 face each other, and the solder bump 1 and the electrode portion 3a are in contact with each other (electronic component). Mounting step S2).
[0023]
Next, in the step shown in FIG. 1C, the liquid underfill material 4 is injected into the end of the CSP 2 on one surface of the substrate 3 by the underfill injection dispenser 7 (underfill material injection step S3). ).
[0024]
Next, in the step shown in FIG. 1 (d), the substrate 3 on which the CSP 2 is mounted is put into a reflow furnace for solder reflow, and the underfill material 4 is formed under the temperature condition (reflow profile) as shown in FIG. Fill and solder.
[0025]
In the reflow profile shown in FIG. 2, a region P1 that is constant for about a predetermined time (for example, several tens of seconds) at about 60 ° C. is a region for filling the underfill material 4 between the CSP 2 and the substrate 3 (underfill material filling). The region P2 that is constant at a predetermined time (for example, about 100 seconds) at about 150 ° C. is a preheating region, and the region P3 that is maintained at a temperature of 183 ° C. or higher for a predetermined time (for example, about 100 seconds) is the main heating region. It is. Further, a point T1 in FIG. 2 is a solder melting point (melting temperature of the solder bump 1), and a point T2 is a solder solidifying point.
[0026]
First, in the underfill material filling region P1, since the underfill material 4 has the lowest viscosity, it is almost completely filled between the CSP 2 and the substrate 3 by a capillary phenomenon (underfill material filling step S4). At this time, since the viscosity of the solder paste 5 is about 180,000 mPa · s, the solder paste 5 is not pushed away by the liquid underfill material 4. In addition, this area | region P1 can be made into about 20 to 60 second at 60-70 degreeC, for example.
[0027]
Then, the temperature in the furnace is increased from the underfill material filling region P1, and the preheating region P2 is entered. Here, when the main heating region P3 is suddenly entered from the region P1, the board and each component are subjected to a thermal shock, resulting in quality deterioration. The preheating region P2 is provided to prevent such a thermal shock. Then, the furnace temperature is further raised, and the main heating region P3 corresponding to the solder reflow process is entered from the preheating region P2.
[0028]
When the solder melting point T1 is passed and the main heating region P3 is entered, the solder paste 5 and the solder bump 1 are melted. Thereafter, the temperature in the furnace is lowered, the cooling zone is entered, and when the solder solidification point T2 is reached, the solder joint is completed.
[0029]
Further, in the main heating region P3, the underfill material 4 is cured after the solder melting point T3. Here, the completion of the curing of the underfill material 4 can be performed at any point in the main heating region P3 because self-alignment is assured as long as the solder melting point T3 is passed.
[0030]
Here, the main heating region P3 is a step of melting and joining the solder and curing the underfill material (melting and joining and curing step S5). In this step S5, the melted solder bump 1 and the liquid underfill material 4 are in a coexisting state, but they are not mixed due to the difference in wettability and viscosity between the resin and the metal.
[0031]
Thus, the mounting structure shown in FIG. 1E is completed through the above-described steps S1 to S5.
[0032]
By the way, according to this embodiment, since the liquid underfill material 4 can be thermally cured at the same time in the melting / bonding and curing step S5, the heat of the underfill material 4 can be obtained using a reflow furnace for solder reflow. Curing can be completed.
[0033]
Moreover, the heating time by the said reflow profile is 4 to 8 minutes, for example, and also the heating of solder reflow (main heating area | region P3) is about 100 second, for example, compared with the thermosetting time (about 2 hours) of the conventional resin. Therefore, when other components other than the CSP 2 are mounted on the substrate 3, thermal degradation of the other components can be prevented.
[0034]
Therefore, according to the present embodiment, it is possible to provide an electronic component mounting method that realizes a reduction in manufacturing cost related to filling and curing of the underfill material and prevention of thermal deterioration of other components.
[0035]
Moreover, according to this embodiment, since the material close | similar to the thermal expansion coefficient of solder is selected as the underfill material 4, it can improve the thermal fatigue life of a solder part in a mounting structure.
[0036]
Further, in the present embodiment, the CSP 2 having the solder bump 1 formed so as to protrude to one surface side is placed on one surface of the substrate 3 so that the solder bump 1 and the electrode portion 3a of the substrate 3 are in contact with each other through the solder paste 5. Since the liquid underfill material 4 is injected between the members 2 and 3 after being mounted on the substrate, the underfill material 4 may enter between the solder bumps 1, the solder paste 5, and the electrode portions 3 a of the substrate 3. There is almost no reliable connection.
[0037]
Other components may be mounted at any time before being put into the reflow furnace. For example, it may be mounted on the substrate 1 before mounting the CSP 2, may be performed during the mounting step S2 of the CSP 2, or may be performed after mounting the CSP 2.
[0038]
In addition to the CSP, any electronic component may be used as long as it has solder bumps formed so as to protrude to the one surface side.
[Brief description of the drawings]
FIG. 1 is a process diagram showing a method for mounting an electronic component according to an embodiment of the present invention.
FIG. 2 is a diagram showing a reflow profile in the mounting method.
[Explanation of symbols]
1 ... solder bump, 2 ... CSP (chip size package),
3 ... printed wiring board, 4 ... underfill material, S2 ... electronic component mounting process,
S3: Underfill material injection step, S4: Underfill material filling step,
S5: Melting / joining and curing process.
Claims (2)
前記基板の前記一面上における前記電子部品の端部に、硬化温度が前記はんだバンプの溶融温度以上である液状の熱硬化性樹脂（４）を注入する工程（Ｓ３）を行い、
この後、前記電子部品を搭載した前記基板をリフロー炉に投入し、前記リフロー炉内において、
前記電子部品の前記一面と前記基板の前記一面との間に前記熱硬化性樹脂を前記はんだバンプの溶融温度未満の温度にて充填する工程（Ｓ４）と、
この後、前記はんだバンプの溶融温度以上に加熱することにより、前記はんだバンプを溶融させて前記基板の前記一面に接合するとともに、前記液状の熱硬化性樹脂を硬化させる工程（Ｓ５）と、を行うことを特徴とする電子部品の実装方法。 After performing the step (S2) of mounting the electronic component (2) having the solder bump (1) formed so as to protrude on the one surface side on the one surface of the substrate (3) through the solder bump,
Performing a step (S3) of injecting a liquid thermosetting resin (4) having a curing temperature equal to or higher than the melting temperature of the solder bumps to the edge of the electronic component on the one surface of the substrate ;
Thereafter, the substrate on which the electronic component is mounted is put into a reflow furnace, and in the reflow furnace,
Filling the thermosetting resin between the one surface of the electronic component and the one surface of the substrate at a temperature lower than the melting temperature of the solder bumps (S4);
Thereafter, the step of heating the solder bump above the melting temperature of the solder bump to melt the solder bump and joining it to the one surface of the substrate, and curing the liquid thermosetting resin (S5), mounting method of electronic components, which comprises carrying out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14532999A JP3890814B2 (en) | 1999-05-25 | 1999-05-25 | Electronic component mounting method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14532999A JP3890814B2 (en) | 1999-05-25 | 1999-05-25 | Electronic component mounting method |
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| Publication Number | Publication Date |
|---|---|
| JP2000332167A JP2000332167A (en) | 2000-11-30 |
| JP3890814B2 true JP3890814B2 (en) | 2007-03-07 |
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| JP14532999A Expired - Fee Related JP3890814B2 (en) | 1999-05-25 | 1999-05-25 | Electronic component mounting method |
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| CN1303678C (en) * | 2002-06-28 | 2007-03-07 | 矽品精密工业股份有限公司 | Chip carrier holed semiconductor package element and mfg. method thereof |
| JP2007335741A (en) * | 2006-06-16 | 2007-12-27 | Sony Computer Entertainment Inc | Semiconductor device and its manufacturing method |
| JP5245270B2 (en) * | 2007-03-28 | 2013-07-24 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| WO2010122757A1 (en) | 2009-04-24 | 2010-10-28 | パナソニック株式会社 | Method for mounting semiconductor package component, and structure having semiconductor package component mounted therein |
| JP5464897B2 (en) * | 2009-04-24 | 2014-04-09 | パナソニック株式会社 | Mounting method and mounting structure for semiconductor package components |
| JP6816918B2 (en) * | 2015-11-04 | 2021-01-20 | リンテック株式会社 | Manufacturing method of semiconductor devices |
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