JP2007335741A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a flip chip mounting structure, wherein a protection of a bonding part between a protruding electrode formed in a semiconductor chip and an electrode pad formed in a wiring substrate coexists with a protection of a member such as a Low-k film and the like constituting the semiconductor chip. <P>SOLUTION: In the semiconductor device, a semiconductor chip 30 is mounted as a flip chip on a wiring substrate 20, and an underfill 70 is charged between the semiconductor chip 30 and the wiring substrate 20. The underfill 70 contains an insulating resin 72 and an inorganic filler 74. An elastic modulus of the underfill 70 in a region (region U) located upward of a bottom 33 of a protruding electrode 32 is lower than the elastic modulus of the underfill 70, in a region (region L) located downward of the bottom 33 of the protruding electrode 32. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device having a structure in which a semiconductor chip is flip-chip mounted on a wiring board, and a manufacturing method thereof.

  In recent years, as electronic devices such as computers, mobile phones, and PDAs (Personal Digital Assistance) have become smaller, more advanced, and faster, such ICs (integrated circuits) and LSIs (Large Scale Integrated Circuits) for such electronic devices have been developed. There is a demand for further miniaturization, higher speed and higher density of a semiconductor device on which a semiconductor chip is mounted.

  As a semiconductor chip mounting means for reducing the size of a semiconductor device, a technique is known in which a semiconductor chip is flip-chip mounted on a wiring board in a state where the electrode surface on which the protruding electrode is formed is face-down. Technology for improving the connection reliability between the protruding electrodes provided on the semiconductor chip and the electrode pads provided on the wiring board by filling the gap between the semiconductor chip and the wiring board with an underfill in the flip chip mounting structure Is known (see, for example, Patent Document 1).

Further, as the semiconductor chip is miniaturized, there is a problem that the capacity between the wirings increases due to the reduction of the wiring interval, and the signal propagation speed decreases. In order to solve this problem, an insulating material having a low relative dielectric constant (Low-k) is used for an interlayer film of a semiconductor chip.
JP 2005-353672 A

  The conventional underfill has mainly been aimed at improving the connection reliability between the protruding electrode provided on the semiconductor chip and the electrode pad provided on the wiring board. It was not suitable for protecting members such as k-films. For this reason, it is difficult to simultaneously achieve the protection of the joint between the protruding electrode provided on the semiconductor chip and the electrode pad provided on the wiring board and the protection of the member such as the low-k film of the semiconductor chip. there were.

  The present invention has been made in view of these problems, and an object of the present invention is to join a protruding electrode provided on a semiconductor chip and an electrode pad provided on a wiring board in a semiconductor device having a flip chip mounting structure. The present invention provides a technique capable of achieving both protection of a portion and protection of a member such as a low-k film constituting a semiconductor chip.

  One embodiment of the present invention is a semiconductor device. The semiconductor device includes a wiring board on which a substrate electrode is formed, and a protruding electrode that is mounted on the wiring board with the electrode surface facing down and electrically connected to the substrate electrode via solder. And an underfill containing an insulating resin and an inorganic filler, which is filled between the semiconductor chip and the wiring substrate, and has an elastic modulus of the underfill in the region located above the bottom of the protruding electrode Is lower than the elastic modulus of the underfill in the region located below the bottom of the protruding electrode.

  According to this aspect, the semiconductor chip is protected by the underfill portion having a relatively low elastic modulus, i.e., the rigidity is higher, and the elastic modulus is relatively higher at the wiring substrate and the joint portion between the wiring substrate and the semiconductor chip. It can be protected with a portion of the underfill that is larger, ie, more flexible. As a result, it is possible to achieve both the protection of the junction between the protruding electrode provided on the semiconductor chip and the electrode provided on the wiring board and the protection of the member such as the low-k film constituting the semiconductor chip.

  In the above aspect, the inorganic filler content of the underfill in the region positioned below the bottom of the protruding electrode is greater than the inorganic filler content of the underfill in the region positioned above the bottom of the protruding electrode. Also good.

  Another embodiment of the present invention is a method for manufacturing a semiconductor device. The manufacturing method of the semiconductor device is a manufacturing method of a semiconductor device in which a semiconductor chip is flip-chip mounted on a wiring board, and the semiconductor chip is mounted on the wiring board in a state where the electrode surface is face down. A joining step of joining the formed wiring electrode and the protruding electrode provided on the semiconductor chip by solder, and an underfill filling step of filling an underfill containing an insulating resin and an inorganic filler between the semiconductor chip and the wiring substrate, And a filler sedimentation step for sedimenting the inorganic filler in the underfill, and an underfill curing step for curing the underfill.

  According to this aspect, the semiconductor chip is protected by the underfill portion having a relatively low elastic modulus, that is, higher rigidity, and the wiring substrate and the joint portion between the wiring substrate and the semiconductor chip are relatively elastic. A semiconductor device protected by an underfill portion having a high rate, that is, a higher flexibility can be manufactured.

  In the semiconductor device manufacturing method of the above aspect, the insulating resin is a thermosetting resin, and in the filler sedimentation step, the underfill is maintained at a temperature lower than the heat curing temperature of the insulating resin for a predetermined time. The underfill may be heated to the thermosetting temperature of the insulating resin.

  According to the present invention, in a semiconductor device having a flip-chip mounting structure, protection of a junction between a protruding electrode provided on a semiconductor chip and an electrode pad provided on a wiring board and low-k constituting the semiconductor chip It is possible to achieve both protection of a member such as a membrane.

  FIG. 1 is a schematic diagram illustrating a structure of a semiconductor device 10 according to an embodiment. The semiconductor device 10 includes a wiring substrate 20, a semiconductor chip 30, and an underfill 70. The semiconductor device 10 of this embodiment has a BGA (Ball Grid Array) type semiconductor package structure in which a plurality of solder balls 50 are arranged in an array on the back surface of the wiring board 20.

  The wiring board 20 has a multilayer wiring structure in which interlayer insulating films and wiring layers are alternately stacked. FIG. 2 is a cross-sectional view showing the structure of the wiring board 20 in more detail. A plurality of wiring layers 22 are stacked via an interlayer insulating film 24. For example, copper is used for the wiring layer 22. The wiring layers 22 having different layers are electrically connected by via plugs 26 provided in the interlayer insulating film 24. A solder resist film 28 made of a resin material having excellent heat resistance is formed around the wiring layer 22a on the back surface of the wiring board 20. When soldering the wiring board 20, solder adheres to areas other than necessary. The lowermost interlayer insulating film 24a is coated so that it does not. A plurality of ball land portions 29 to which the solder balls 50 are bonded are arranged in an array on the back surface of the wiring board 20. The surface of the ball land portion 29 is covered with an organic surface protective coating material (OSP) 21. On the other hand, a plurality of electrode pads 25 made of nickel, lead, gold, or alloys thereof are formed in an array on the surface of the wiring board 20 on the side where the semiconductor chip is mounted. A C4 (Controlled Collapse Chip Connection) bump 27 made of tin, lead, or an alloy thereof is provided on 25.

  Thus, the wiring board 20 of the present embodiment can be thinned to about 300 μm with a six-layer structure, for example, by being coreless. By reducing the thickness of the wiring board 20, the wiring resistance is reduced, so that the operation speed of the semiconductor device 10 can be increased.

  Returning to FIG. 1, flip-chip mounting is performed on the surface of the wiring substrate 20 with a semiconductor chip 30 such as an LSI facing down. More specifically, the protruding electrodes 32 of the semiconductor chip 30 and the C4 bumps 27 of the wiring board 20 are joined by solder 80. The semiconductor chip 30 has a low dielectric interlayer insulating film (low-k film). With the low-k film, the capacitance between the miniaturized wirings in the semiconductor chip 30 can be reduced.

  FIG. 3 is an enlarged view of a main part showing a connection structure between the wiring board 20 and the semiconductor chip 30. As shown in FIG. 3, the underfill 70 is filled between the semiconductor chip 30 and the wiring substrate 20. The underfill 70 includes an insulating resin 72 and an inorganic filler 74.

Examples of the insulating resin 72 include resins mainly composed of epoxy. The elastic modulus (Young's modulus) of the insulating resin 72 is preferably about 1 to 4 GPa. Examples of the inorganic filler 74 include SiO ₂ (silica). The elastic modulus (Young's modulus) of the inorganic filler 74 is preferably 50 Gpa or more.

  The elastic modulus of the underfill 70 in the region located above the bottom 33 of the protruding electrode 32 (region U in FIG. 3) is the region positioned below the bottom 33 of the protruding electrode 32 (region L in FIG. 3). ) Of the underfill 70 is lower than the elastic modulus.

  More specifically, the inorganic filler content of the underfill 70 in the region L is larger than the inorganic filler content of the underfill 70 in the region U.

  As for the inorganic filler content rate of the underfill 70 in the area | region L, 50-80 wt% is preferable. The elastic modulus (Young's modulus) of the underfill 70 in the region L is preferably 10 GPa or more. On the other hand, the inorganic filler content of the underfill 70 in the region U is preferably 0 to 50 wt%. The elastic modulus (Young's modulus) of the underfill 70 in the region U is preferably 1 to 5 GPa.

  By providing the underfill 70 between the semiconductor chip 30 and the wiring substrate 20, the stress applied to the C4 bump 27 due to the gap variation between the wiring substrate 20 and the semiconductor chip 30 due to thermal expansion during a temperature cycle is suppressed. Can do.

  Furthermore, by filling the space between the semiconductor chip 30 and the wiring board 20 using the underfill 70 of the present embodiment, the semiconductor chip 30 has a relatively low elastic modulus, that is, a rigidity of the underfill 70 having higher rigidity. Can be protected with a piece. Further, the wiring substrate 20 and the joint portion between the wiring substrate 20 and the semiconductor chip 30 can be protected by a portion of the underfill 70 having a relatively large elastic modulus, that is, higher flexibility. As a result, both the protection of the joint between the protruding electrode 32 provided on the semiconductor chip 30 and the C4 bump 27 provided on the wiring substrate 20 and the protection of the members such as the low-k film constituting the semiconductor chip 30 are achieved. Can be made.

(Semiconductor chip mounting method)
First, as shown in FIG. 4A, with the surface of the semiconductor chip 30 on which the external electrode terminals are provided facing down, the protruding electrodes 32 and the corresponding C4 bumps 27 are joined by solder 80. As a result, the semiconductor chip 30 is flip-chip mounted on the wiring board 20. More specifically, after the solder 80 is printed on the C4 bumps 27, the semiconductor chip 30 is mounted on the wiring board 20, and reflow processing is performed.

Next, as shown in FIG. 4B, a molten underfill 70 is poured between the semiconductor chip 30 and the wiring substrate 20. The underfill 70 includes an insulating resin 72 and an inorganic filler 74. As described above, epoxy can be used as the insulating resin 72. In addition, SiO ₂ can be used as the inorganic filler 74. As for the content rate of the inorganic filler 74 with respect to the whole underfill 70, 30-60 wt% is preferable. The inorganic filler 74 contained in the underfill 70 is desirably fine powder removed using a known powder removing device or the like. By removing the fine powder from the inorganic filler 74, the sedimentation property or fluidity of the inorganic filler 74 when the underfill 70 is thermally cured can be improved. More specifically, when the distance between the semiconductor chip 30 and the wiring substrate 20 is 100 μm, it is desirable that the inorganic filler has a particle size distribution of 5 to 10 μm.

  Next, the underfill 70 is thermally cured and the inorganic filler 74 contained in the underfill 70 is allowed to settle. When epoxy is used for the insulating resin 72, a state where the heating temperature is lower than the thermosetting temperature (150 to 165 ° C.) of the insulating resin 72 (for example, 80 ° C.) is maintained for 10 to 60 minutes (filler sedimentation step) ) Thereafter, the above-mentioned thermosetting temperature is maintained for about 1 to 4 hours (underfill curing step). In this way, the inorganic filler 74 is allowed to settle by keeping the state of low viscosity before the insulating resin 72 is cured, and the inorganic filler content of the underfill 70 in the region L is set as shown in FIG. It can be made larger than the inorganic filler content of the underfill 70 in U.

  The temperature conditions for the filler sedimentation step and the underfill curing step can be appropriately set according to the gap between the semiconductor chip 30 and the wiring substrate 20, the size of the semiconductor chip 30, and the like.

  In the above-described manufacturing method, a method of precipitating the inorganic filler when the underfill is thermally cured is used, but the manufacturing method of the semiconductor device 10 of the present embodiment is not limited to this. For example, after filling the region D shown in FIG. 3 with an underfill having a relatively high inorganic filler content and thermosetting, filling the region U shown in FIG. 3 with an underfill having a relatively high inorganic filler content, You may employ | adopt the two-stage underfill formation process made to thermoset.

It is the schematic which shows the structure of the semiconductor device which concerns on embodiment. It is sectional drawing which shows in more detail the structure of the wiring board of embodiment. It is a principal part enlarged view which shows the connection structure of a board | substrate and a semiconductor chip. It is process drawing which shows the mounting method of a semiconductor chip.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device, 20 Wiring board, 25 Electrode pad, 27 C4 bump, 30 Semiconductor chip, 32 Projection electrode, 70 Underfill, 72 Insulating resin, 74 Inorganic filler.

Claims (4)

A wiring board on which substrate electrodes are formed;
A semiconductor chip mounted on the wiring board in a state where the electrode surface is face-downed and having a protruding electrode on the electrode surface that is electrically connected to the substrate electrode via solder;
An underfill filled between the semiconductor chip and the wiring board, containing an insulating resin and an inorganic filler,
With
2. A semiconductor device according to claim 1, wherein an elastic modulus of an underfill in a region located above the bottom of the protruding electrode is lower than an elastic modulus of an underfill in a region positioned below the bottom of the protruding electrode.   The inorganic filler content of the underfill in the region positioned below the bottom of the protruding electrode is greater than the inorganic filler content of the underfill in the region positioned above the bottom of the protruding electrode. The semiconductor device according to claim 1. A method of manufacturing a semiconductor device in which a semiconductor chip is flip-chip mounted on a wiring board,
Mounting the semiconductor chip with the electrode surface face down on the wiring board, and bonding the wiring electrode provided on the wiring board and the protruding electrode provided on the semiconductor chip by solder; and
An underfill filling step of filling an underfill containing an insulating resin and an inorganic filler between the semiconductor chip and the wiring board;
A filler sedimentation step of sedimenting the inorganic filler in the underfill;
An underfill curing step of curing the underfill;
A method for manufacturing a semiconductor device, comprising: The insulating resin is a thermosetting resin,
In the filler sedimentation step, the underfill is maintained at a temperature lower than the thermosetting temperature of the insulating resin for a predetermined time,
4. The method of manufacturing a semiconductor device according to claim 3, wherein, in the underfill curing step, the underfill is heated to a thermosetting temperature of the insulating resin.

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