TWI460844B - Stacking package structure with chip embedded inside and die having through silicon via and method of the same - Google Patents

Description

Stacked package structure with embedded wafer and germanium via film and manufacturing method thereof

The present invention relates to a semiconductor device package structure, and more particularly to a stacked package structure.

The chip package includes functions such as power distribution, signal distribution, heat dispersion, protection, and support. When a semiconductor component becomes more complicated, conventional packaging technologies such as leadframe packaging technology, flexible packaging technology, and rigid packaging technology are not suitable for the fabrication of smaller wafers and high density components. In general, array packages such as Ball Grid Array (BGA) packages provide high density interconnects relative to their surface areas. A typical BGA package contains intricate signal paths that result in high impedance and inefficient thermal paths, resulting in very poor heat dissipation. As the packing density is increased, the heat generated by effectively dispersing the components becomes more important. In order to meet the packaging needs of the new generation of electronic products, we are committed to creating a package structure with reliability, low cost, small size and high efficiency. For example, these packaging requirements are a reduction in electronic signal transmission delay, a reduction in overlapping configuration areas, and an expansion in the range of input/output (I/O) connection pad configurations. In order to meet these needs, a Wafer Level Package (WLP) has been developed in which an array of I/O terminals is distributed over its active surface rather than a peripheral pin package. Such a distribution of endpoints can increase the number of I/O terminals and improve the electrical performance of this component. Moreover, when disposed on a printed circuit board by means of an internal connection, the area occupied by the IC is only the size of the wafer, not the size of a package lead frame. Therefore, the size of the WLP can be made very small. One type is a Chip-Scale Package (CSP).

Improvements in IC packaging are driven by industrial demands such as increased heat dissipation and electrical performance, as well as reduced manufacturing size and cost. In the field of semiconductor components, component density continues to increase and component dimensions continue to decrease. The need for packaging or interconnect technology in this high density component is also increased to match the conditions mentioned above. The composition of the solder bumps can be achieved using a solder composite material. The flip chip technology is a well-known technology in the art for electrically connecting a die and a mounting substrate, such as a printed wiring board. The active face of this die is limited to a number of electrical connections and is typically used at the edge of the wafer. The electrical connections are placed on the active surface of a flip chip as an end point. The bumps comprise solder and/or plastic for mechanical bonding and electrical coupling to a substrate. The solder bumps after the redistribution of the circuit layer (RDL) have a bump height of about 50 to 100 um. The wafer is placed back against a mounting substrate and the bumps are aligned to the bond pads on the mounting substrate as shown in the first figure. If the bump is a solder bump, the solder bump on the flip chip is soldered to the bond pad on the substrate. In terms of cost, the solder joint is relatively inexpensive, but it increases the electrical resistance and problems such as cracks and voids gradually occur due to fatigue of the thermomechanical stress. Typically, this solder is tin-lead alloy and lead-based material, but these materials have become less used due to environmental issues such as disposal of toxic materials and filtration of toxic materials into groundwater supplies.

Moreover, since conventional packaging techniques must divide the dice on the wafer into individual dies and then package the dies separately, these techniques are quite time consuming in the manufacturing process. Wafer packaging technology is highly influenced by the development of integrated circuits, so packaging technology will also be so demanding as electronic products become more demanding in size. For the reasons mentioned above, today's packaging technology trends are moving toward ball grid array (BGA), flip chip (FC-BGA), chip size packaging (CSP), wafer level packaging (WLP). "Wafer-on-package" is interpreted as a monolithic package, and all internal connections on the wafer complete the other process steps as before the wafer is cut (cut). In general, after all assembly processes or packaging processes are completed, the individual semiconductor packages are separated from the wafer having one of a plurality of semiconductor wafers. This wafer level package has a very small dimension combined with excellent electrical properties. In the ninth figure, this prior art is a technology published by Samsung Electronics in April 2006, which shows that the 3D stacked structure has a minimum form factor, using a wafer level process to pass through vias (TSV). The inner join 902 is used to stack the tantalum wafer 901. However, this can only handle semiconductor components having the same grain size and the same pad (TSV) position structure, which must be designed to be more advanced. This cannot be used for different wafers with different grain sizes and can only be used for higher density memory applications under normal conditions.

Conventional grains are only covered by glass, while other surfaces of the grains are exposed. This may cause the grain to break due to external forces. This process is also very complex and, therefore, the present invention provides a relatively safe structure to overcome the above mentioned problems and also provide for the implementation of preferred components.

It is an object of the present invention to provide a semiconductor component package (wafer assembly) that provides a low cost, high efficiency, and high reliability package structure.

The semiconductor device package structure of the present invention comprises a first die having a via (TSV) opening on the back side of the first die to expose the bond pad; a buildup coupling to the bond The pad and the end metal pad are coupled to the bonding pad and the end metal pad by using the 矽 conductive via; the substrate has a second die embedded therein, and the upper circuit wiring and the lower circuit wiring are respectively disposed on the upper side of the substrate And a lower side; and a conductive via structure for coupling the end metal pad with the upper circuit wiring and the lower circuit wiring.

The semiconductor device package structure further includes solder bumps fused to the end pads, wherein the end pads are located under the substrate and/or the first die. The build-up layer includes a first dielectric layer, and a second dielectric layer is disposed on the first dielectric layer. The material of the substrate includes FR4, FR5, BT, PI, and epoxy resin. The semiconductor component package structure further comprises an adhesive material covering the second die, and the adhesive material comprises an elastic material. The first die comprises an image sensor, an optical component, a memory component, a logic component, an analog component, or a central processing unit (CPU) component. The material of the conductive via structure includes Cu, Cu/Ni or Sn/Ag/Cu. The Foot Print Size of the substrate may be larger than the size of the second die. The structure further includes an upper buildup layer formed over the second die and the substrate, and a lower buildup layer formed under the second die and the substrate. The upper enhancement layer includes a third dielectric layer, an RDL, a metal pad coupled to the second die and the RDL, and a fourth dielectric layer over the third dielectric layer to cover the RDL. . The lower enhancement layer includes a fifth dielectric layer, a second RDL, a second terminal metal pad coupled to the second RDL, and a sixth dielectric layer over the fifth dielectric layer to cover the first Two RDL. The structure includes a second substrate under the substrate, and the second substrate has a second upper circuit line and a second lower circuit line respectively disposed on the upper side and the lower side of the second substrate.

A method for forming a semiconductor die assembly includes: bonding a planar substrate to a back side of a germanium wafer; curing an adhesive dielectric layer, the adhesive dielectric layer being formed on the planar substrate; sputtering a seed crystal a metal layer is disposed on the back side of the planar substrate; a photoresist layer is coated on the back side of the planar substrate to expose a via region; and a metal material is filled into the via region to bond a die pad to the planar substrate An end pad; and removing the photoresist layer and etching the seed metal layer.

The method further includes the step of aligning the side of the circuit of the planar substrate toward the back side of the germanium wafer before bonding the planar substrate to the germanium wafer. The method further includes a step of forming a solder ball on the Under Bump Metallurgy (UBM) of the planar substrate after removing the photoresist layer.

The invention will now be described in detail in the preferred embodiments and drawings. However, it is to be noted that the preferred embodiments of the present invention are intended to be illustrative only, and that the present invention may be covered by other embodiments than those described in detail herein. The scope of the invention is not limited to the description and is subject to the scope of the appended claims.

The present invention discloses a stacked semiconductor device package structure. The present invention provides a semiconductor wafer assembly comprising a planar substrate with a second die embedded therein and a wafer level package having a via via (TSV), as shown in the third, fourth and sixth figures. .

The first figure shows a cross-sectional view of a wafer having a semiconductor die 100 and bond pads 102 formed on the circuit side 101 of the die 100. In one example, the die 100 is comprised of an image sensor, an optical component, a memory component, a logic component, an analog component, or a central processing unit (CPU) component. Referring to the seventh figure, the germanium wafer 701 has a via (TSV) 103 formed on the back side of the germanium wafer (the hole of the bonding pad is exposed) to connect the bonding pad 102. In one embodiment the die is a CMOS sensor. The buildup layer 107 is formed below the back side of the germanium wafer to connect the metal pad 104 and the bond pad 102 through the TSV 103. If the pitch of the bond pads 102 is too small for the fabrication of the metal pads and subsequent processes, then only the metal pads 104 can be fabricated under the bond pads 102 without the need to re-route the layers (RDL). The buildup layer 107 includes a first dielectric layer 106 formed on the back side of the germanium wafer, and a second adhesive dielectric layer 105 formed on the first dielectric layer 106. For example, the first dielectric layer 106 and the second dielectric layer 105 are coated on the back side of the germanium wafer by a lithography process to expose the TSV 103 (uncured), thereby coupling the Metal pad 104 and TSV 103.

The second figure shows a cross-sectional view of a planar substrate in which a second die is embedded (note: the second die includes a multi-wafer having a shoulder-and-shoulder structure) through which the second build-up and vias pass. In this example, the planar substrate 700 shown in the seventh diagram is a multi-layer planar substrate. This planar substrate size is the same as the wafer size. The footprint of the substrate can be larger than the size of the die (wafer) 200. For example, the substrate is composed of FR4, FR5, BT, PI, and epoxy resin, and the substrate is preferably a BT substrate having fiberglass. The wafer 200 is attached to the surface of a second substrate 210 by an adhesive material 218. It may have elastic properties to absorb the stress generated by heat. The adhesive material 218 encapsulates the wafer 200. The wafer 200 has a bonding pad 201 coupled through a hole 202 to a redistribution wiring layer (RDL) 246. The bond pad 201 can be an Al pad, a Cu pad or other metal pad. The upper buildup layer 250 is formed on the surface of the wafer 200 and on a substrate 206. The upper build-up layer 250 includes a dielectric layer 203, a hole 202, an RDL 246, and an adhesive dielectric layer 204. The dielectric layer 203 is formed on the wafer 200 and the substrate 206, and the adhesive dielectric layer 204 is formed on the dielectric layer. 203 is over to cover RDL 246. The RDL 246 is formed by an electroplating, sputtering or etching process. The copper plating is continuously operated until the copper layer reaches the desired thickness. The conductive layer extends to receive the area of the wafer and is referenced to a Fan-Out mechanism. This fan-out mechanism provides better heat dissipation and greater spacing between solder balls to reduce signal interference. The upper build-up layer 250 is formed on the wafer circuit side to connect the bond pads 201 of the wafer 200 and the circuit wiring 207 through the holes 202 and the RDL 246. For example, the dielectric layer 203 and the dielectric layer 204 coated on the surface of the die 200 form an opening to the hole 202 by a lithography process, and the bonding pad 201 passes through the hole 202 to couple the RDL 246. In order to consider better reliability, it is preferably as fine as possible for the dielectric layer 203. The substrate 206 has an upper circuit wiring 207 formed above the substrate 206 and a lower circuit wiring 208 formed under the substrate 206, for example, to form a double-maleamide tripod-copper foil (BT-CCL) substrate 220. In one embodiment, the untreated BT substrate does not have a via, but has circuit wiring on both sides of the substrate. In one example, the substrate will be made of PI, BT, FR4, FR5, printed circuit board (PCB), tantalum, ceramic, glass, metal, alloy or the like. Alternatively, if the substrate is selected from a silicone rubber, a silicone resin, a modified epoxy resin, EMC or the like, it is suitable for use in (vacuum) printing techniques.

The substrate 210 has a die pad 209 (for heat dissipation) and a pre-formed circuit trace pattern 211 formed on the upper surface, and a circuit trace pattern 212 on the lower surface of the substrate 210, for example, to form a BT-CCL substrate. 230. A connection conductive via 213 may be formed through the substrate 210 for connecting the circuit wiring patterns 209, 248 to ground (GND) and the heat sink. The die (wafer) 200 has a back side and is adhered to the die pad 209 of the substrate 210 with an adhesive material 218. The adhesive material (which can act as a stress buffer layer to absorb the thermal stress caused by the CTE mismatch relationship) 218 is used to fill the gap between the back side of the die 200 and the upper surface of the substrate 210 and the sidewalls and crystal grains of the die 200. The gap between the sidewalls of the open window. The adhesive material 218 is sealed by printing, coating or dispensing onto the lower surface of the die 200. Adhesive material 218 is formed adjacent to die 200 to achieve a protective effect. In one embodiment, the adhesive material 218 covers the upper surface of the substrate 206 and the surface of the die 200, and only the bonding pad 201 is exposed and under the build-up layer 250. The surface height of the die 200 and the surface height of the substrate 206 can be achieved by the adhesive material 218 to the same height. Connecting conductive vias 205 can be formed through the substrates 206 and 210. The conductive vias 205 of the substrate can be achieved by computer numerical control (CNC) or laser perforation.

The lower build-up layer 240 is of an alternative structure and process and is formed below the surface of the wafer 200 and substrate 210. The lower build-up layer 240 includes a dielectric layer 214, a via 242, a UBM 217, an RDL 248, 216, and a dielectric layer 215. The dielectric layer 214 is formed under the surface of the substrate 210 and has an opening to form a hole 242 therein. And the dielectric layer 215 is formed under the dielectric layer 214 to cover the RDL 246. For example, the dielectric layer 214 and the dielectric layer 215 are applied to the surface of the substrate 210, and an opening is formed by the lithography process corresponding to the holes 242 and the UBM 217, and the holes 242 are coupled to the UBM 217 through the RDL 216. UBM 217 functions as a solder metal pad.

The third figure shows a cross-sectional view of a stacked semiconductor wafer assembly constructed by joining two components of the aforementioned embodiments, such as the combination of the first wafer and the second wafer. The planar substrate in the figure. The face-to-face architecture is shown with a CNC through hole in which Cu is plated. In this architecture, the upper package is stacked over the lower package by substrates 206 and 210. A plurality of CNC through holes 205a are plated with Cu/Ni/Au and penetrate the stack structure from top to bottom. One aspect of this embodiment is that the active faces of the two packages (this surface comprising metal pads 104, 262) are face to face structures. As shown in the second figure, the planar substrate includes a substrate 206 and a substrate 210 and is embedded with a second wafer 200, two build-up layers 250, 240, and a via 205 extending through the planar substrate. Referring to the eighth figure, the wafer back side 701 and the other side of the wafer back side 701 are bonded together under vacuum to form a stacked semiconductor wafer structure 800. It is worth noting that this adhesive dielectric layer is then cured. The conductive via 205 is also filled with the conductive material after bonding to form a conductive via structure 205a. In one embodiment, the material of the conductive via structure 205a comprises Cu, Cu/Ni or Sn/Ag/Cu. The conductive via structure 205a has an upper metal pad 262 formed therein, and a lower metal pad 228 is formed under the conductive via structure 205a. It should be noted that the upper metal pad 262 is coupled (interposed) to the metal pad 104. A second adhesive dielectric layer 105 is attached to the adhesive dielectric layer 204. A solder ball or solder joint (conductive bump) 219 is formed in the under bump metal layer (UBM) 217 to function as an end pad. In more applications, the multilayer wafer has the same structure as the first die (wafer) bonding stack (interconnected) above the first die (circuit side). The multi-layer planar structure in-line wafers can also be stacked together using the same kind of application. Another embodiment of the present invention utilizes an SMT process to mount the CSP, WL-CSP, mini BGA, or active device over the first die. Of course, the use of this application requires the fabrication of circuit wiring over the upper surface of the first die.

The fourth figure shows another embodiment of the present invention. This structure is mostly similar to the previously mentioned embodiment except that the inner connection structure 232 is coupled to the metal pad 104 below the surface of the TSV 103 and the metal pad 262 above the surface of the via structure 205a. This means that the metal pads 262 and 104 act like a UBM.

Please refer to the fifth and sixth figures for showing other embodiments of the present invention. However, in this example, the planar substrate is a single planar substrate. The thickness of the package structure can be thinner than the package structure shown in the third and fourth figures. This structure is mostly similar to the previously mentioned embodiments and will not be described again.

Advantages: The package size is independent of the size of the wafer and can be maintained at one of the wafers with the same ball pitch, which provides better reliability in the connection of the holes. The active of the wafer is protected during processing and provides a preferred electrical insulation effect in the upper surface. Thinner wafers have a better effect on reliability and provide a simple process to form this thinner wafer. Stacked packages are easier to provide and are also easier to fan out.

A method of forming a semiconductor die assembly includes aligning the sides of the circuit of a planar substrate with respect to the back side of a wafer and bonding them together under vacuum. Next, the adhesive dielectric layer is cured, and the adhesive dielectric layer is formed on the planar substrate and then cleaned by RIE. Next, a seed metal (e.g., Ti/Cu) is sputtered onto the back side of the substrate, and the photoresist is coated or laminated thereon, and then the via region is revealed by a photolithography process. The next step is to deposit Cu or fill the Cu paste into the via region to connect the bonding pads of a die to the inner pad of the substrate, and then remove the photoresist layer and etch the seed metal Cu. /Ti to form this inner connecting structure. Finally, the solder balls are placed over the under bump metal layer (UBM) and then reflowed (for BGA type). In theory, the under bump metallization (UBM) is formed prior to the formation of the solder balls as a barrier or adhesion layer to prevent problems between the solder balls and the ball pads.

While the invention has been described in detail, the preferred embodiments of the present invention In addition, most of the changes or modifications are still included in the spirit and scope of the present invention, and are defined by the scope of the patent application to be described later.

100. . . Grain

101. . . Circuit side

102. . . Mat

103. . .矽 conduction hole

104. . . Metal pad

105. . . Second adhesive dielectric layer

106. . . First dielectric layer

107. . . Addition

200. . . Grain

201. . . Mat

202. . . Hole

203. . . Dielectric layer

204. . . Adhesive dielectric layer

205. . . Conductive through hole

205a. . . Conductive via structure

206. . . Substrate

207. . . Upper circuit wiring

208. . . Lower circuit wiring

209. . . Grain metal pad

210. . . Substrate

211. . . Circuit wiring pattern

212. . . Circuit wiring pattern

213. . . Conductive through hole

214. . . Dielectric layer

215. . . Dielectric layer

216. . . Redistribution circuit layer

217. . . Under bump metal layer

218. . . Adhesive material

219. . . Solder ball

220. . . Substrate

228. . . Lower metal pad

230. . . BT-CCL substrate

232. . . Internal connection structure

240. . . Lower layer

242. . . Hole

246. . . Redistribution circuit layer

248. . . Circuit wiring pattern

250. . . Upper layer

262. . . Metal pad

700. . . Planar substrate

701. . . Silicon wafer

800. . . Stacked semiconductor wafer structure

901. . .矽 chip

902. . . TSV internal link

The first figure shows a cross-sectional view of a wafer level package having a germanium via (TSV) and a buildup on the back side of the first die in accordance with an embodiment of the present invention.

The second drawing shows a cross-sectional view of a planar substrate in which the second die, the double buildup layer, and the via are embedded in accordance with an embodiment of the present invention.

The third figure shows a cross-sectional view of a stacked semiconductor wafer assembly corresponding to one embodiment of the present invention.

The fourth figure shows a cross-sectional view of a stacked semiconductor wafer assembly corresponding to one embodiment of the present invention.

The fifth drawing shows a cross-sectional view of a planar substrate in which the second die, buildup, and via are embedded in accordance with further embodiments of the present invention.

The sixth drawing shows a cross-sectional view of a stacked semiconductor wafer assembly corresponding to one embodiment of the present invention.

The seventh drawing shows a schematic view of the back side of the wafer and the back side of the substrate corresponding to the embodiment of the present invention.

The eighth figure shows a schematic diagram of a stacked semiconductor wafer assembly corresponding to an embodiment of the present invention.

The ninth diagram shows a schematic diagram of a stacked semiconductor wafer assembly corresponding to the prior art.

100‧‧‧ grain

102‧‧‧ joint pad

103‧‧‧矽通孔孔

104‧‧‧Metal pad

105‧‧‧Second adhesive dielectric layer

106‧‧‧First dielectric layer

107‧‧‧Additional

200‧‧‧ grain

201‧‧‧ joint pad

202‧‧‧ hole

203‧‧‧ dielectric layer

204‧‧‧Adhesive dielectric layer

205a‧‧‧conductive via structure

206‧‧‧Substrate

207‧‧‧Upper circuit wiring

208‧‧‧Circuit wiring

209‧‧‧Grain metal pad

210‧‧‧Substrate

211‧‧‧Circuit wiring pattern

212‧‧‧Circuit wiring pattern

213‧‧‧ conductive vias

214‧‧‧ dielectric layer

215‧‧‧ dielectric layer

216‧‧‧Re-distribution layer

217‧‧‧ under bump metal layer

218‧‧‧Adhesive material

219‧‧‧ solder balls

220‧‧‧Substrate

228‧‧‧Metal pad

230‧‧‧BT-CCL substrate

240‧‧‧Additional

242‧‧‧ holes

246‧‧‧Re-distribution layer

248‧‧‧Circuit wiring pattern

250‧‧‧Upgrading

262‧‧‧Metal pad

Claims (14)

A semiconductor device package structure includes: a first die having a turn-on via opening on a back side of the first die to expose a bond pad; a build-up coupling to the bond pad and an end metal pad And connecting the bonding pad and the end metal pad through the through hole; a second die is embedded in the substrate, and the upper circuit and the lower circuit are respectively disposed on the upper side and the lower side of the substrate; The conductive via structure is configured to couple the end metal pad and the upper circuit and the lower circuit; and an upper buildup layer is formed on the second die and the substrate, wherein the upper buildup layer comprises a third dielectric a layer, a redistribution circuit layer (RDL), a hole coupled to the metal pad of the second die and the redistribution circuit layer, and a fourth dielectric layer on the third dielectric layer to cover the redistribution circuit Floor. The semiconductor device package structure of claim 1, wherein the build-up layer comprises a first dielectric layer, and a second dielectric layer is over the first dielectric layer. The semiconductor device package structure according to claim 1, wherein the material of the substrate comprises FR4, FR5, BT, PI and epoxy resin. The semiconductor device package structure of claim 1, further comprising an adhesive material covering the second die, wherein the adhesive material further comprises an elastic material. The semiconductor device package structure of claim 1, wherein the material of the conductive via structure comprises Cu, Cu/Ni or Sn/Ag/Cu. The semiconductor device package structure of claim 1, further comprising a second substrate under the substrate, wherein the second substrate has a second upper circuit wiring and a second lower circuit wiring respectively on the upper side of the second substrate And the lower side. A semiconductor device package structure includes: a first die having a turn-on via opening on a back side of the first die to expose a bond pad; a build-up coupling to the bond pad and an end metal pad And connecting the bonding pad and the end metal pad through the through hole; a second die is embedded in the substrate, and the upper circuit and the lower circuit are respectively disposed on the upper side and the lower side of the substrate; The conductive via structure is configured to couple the end metal pad and the upper circuit and the lower circuit; and a build-up layer is formed under the second die and the substrate, wherein the lower buildup layer comprises a fifth dielectric layer a second redistribution circuit layer, a second terminal metal pad coupled to the second redistribution circuit layer, and a sixth dielectric layer on the fifth dielectric layer to cover the second redistribution circuit layer . The semiconductor device package structure of claim 7, wherein the build-up layer comprises a first dielectric layer and a second dielectric layer over the first dielectric layer. The semiconductor device package structure according to claim 7, wherein the material of the substrate comprises FR4, FR5, BT, PI and epoxy resin. The semiconductor device package structure of claim 7, further comprising an adhesive material covering the second die, wherein the adhesive material further comprises an elastic material. The semiconductor device package structure of claim 7, wherein the material of the conductive via structure comprises Cu, Cu/Ni or Sn/Ag/Cu. The semiconductor device package structure of claim 7, further comprising a second substrate under the substrate, wherein the second substrate has a second upper circuit wiring and a second lower circuit wiring respectively on the upper side of the second substrate And the lower side. A method of forming a semiconductor die assembly, comprising: bonding a planar substrate to a back side of a germanium wafer; curing an adhesive dielectric layer, the adhesive dielectric layer being formed on the planar substrate; sputtering a crystalline metal Layered on the back side of the planar substrate; coating a photoresist layer on the back side of the planar substrate and exposing a via region; filling a metal material to the via region to connect a die pad and the plane An end pad of the substrate; and removing the photoresist layer and etching the seed metal layer. The method of forming a semiconductor die as described in claim 13 , further comprising: aligning the circuit side of the planar substrate to face the back side of the germanium wafer before bonding the planar substrate and the wafer; After removing the photoresist layer, solder balls are formed on the under bump metal layer (UBM) of the planar substrate.