WO2021092779A1

WO2021092779A1 - Chip package on package structure and electronic device

Info

Publication number: WO2021092779A1
Application number: PCT/CN2019/117720
Authority: WO
Inventors: 张宏英; 朱靖华; 王钿; 顾识群
Original assignee: 华为技术有限公司
Priority date: 2019-11-12
Filing date: 2019-11-12
Publication date: 2021-05-20
Also published as: CN114651322A

Abstract

A chip package on package structure (100) and an electronic device (1), which relate to the technical field of electronics, and are used for solving the problems of how to reduce the size of the chip without simplifying chip functions, ensure the performance of the chip, and lower the possibility of chip breakage. The chip package on package structure (100) comprises: a main stacking structure (10) which comprises a first dielectric layer (12) and first bumps (13) exposed on the surface of the first dielectric layer (12); a plurality of auxiliary stacking structures (30) which comprise a second dielectric layer (32) and second bumps (33) exposed on the surface of the second dielectric layer (32), wherein the first dielectric layer (12) and the second dielectric layer (32) are laminated, and the first bumps (13) and the second bumps (33) are electrically connected; and a third dielectric layer (40), which is located on the side of the auxiliary stacking structures (30) away from the first dielectric layer (12), and is laminated to the first dielectric layer (12).

Description

Chip stack packaging structure, electronic equipment

Technical field

This application relates to the field of electronic technology, and in particular to a chip stack package structure and electronic equipment.

Background technique

With the development of electronic technology, users have higher and higher requirements for the performance of electronic devices, resulting in an increase in the number of transistors in electronic devices, which requires larger and larger chip sizes. However, as electronic devices continue to develop toward integration and ultra-thinness, the chips in electronic devices have to be miniaturized.

Based on this, in order to meet the performance requirements and size requirements at the same time, those skilled in the art propose a package on package (POP) structure, which uses a micro bump bonding process and uses solder balls to stack multiple sub-stack structures. Bonding to the same main stack structure, and then filling an underfill layer between adjacent solder balls for stability.

However, for the above structure, on the one hand, since the solder (copper/tin, copper/tin/silver, etc.) constituting the solder balls has a large fluidity, in order to avoid bridging between adjacent solder balls, the spacing between the solder balls is usually It needs to be greater than 30um, which limits the number of input/output (I/O) interfaces on the fixed-size secondary stack structure, resulting in that the size of the secondary stack structure still cannot be made smaller. On the other hand, due to the large difference between the coefficient of thermal expansion (CTE) of the underfill layer and the CTE of the film layer in the main stack structure, the main stack structure will expand and expand at high temperatures when bonding the main stack structure with other components. During the low-temperature cooling process, a relatively large interaction force will be generated between the underfill layer and the main stack structure, which is likely to cause cracks in the main stack structure.

Summary of the invention

The embodiments of the present application provide a chip stack package structure and electronic equipment, which are used to solve the problem of how to reduce the size of the chip without simplifying the function of the chip, ensure the performance of the chip, and reduce the possibility of chip cracking.

In order to achieve the above objective, this embodiment adopts the following technical solutions:

In a first aspect, a chip stack package structure is provided, including: a main stack structure, the main stack structure includes a first dielectric layer and first bumps exposed on the surface of the first dielectric layer; a plurality of sub-stacked structures, sub-stacked structures It includes a second dielectric layer and a second bump exposed on the surface of the second dielectric layer; the first dielectric layer is bonded to the second dielectric layer, and the first bump is electrically connected to the second bump; third The dielectric layer is located on the side of the sub-stack structure away from the first dielectric layer, and is attached to the first dielectric layer. The chip stack package structure provided in the embodiment of the present application adopts a hybrid bonding process to electrically connect the main stack structure and the auxiliary stack structure. Since the adjacent first bumps and the adjacent second bumps are insulated and isolated by the first dielectric layer and the second dielectric layer, respectively, the first dielectric layer and the second dielectric layer have better stability and fluidity. small. Therefore, the distance between adjacent first bumps and adjacent second bumps can be set smaller, for example, can reach about 9um, or even smaller, which greatly increases the interconnection between the main stack structure and the sub stack structure density. Compared with the related art using a micro bump bonding process to electrically connect the main stack structure and the sub stack structure through solder balls, the chip stack package structure provided by the embodiment of the present application has a fixed size in the sub stack structure Next, compared with related technologies, the number of input/output (I/O) interfaces on the secondary stack structure can be increased to meet the performance requirements of the secondary stack structure. Under the condition that the number of I/O interfaces on the secondary stacking structure remains unchanged, the size of the secondary stacking structure can be reduced compared with related technologies to meet the needs of reducing the size of the secondary stacking structure. In addition, in the chip stack package structure provided by the embodiments of the present application, the third dielectric layer is located on the side of the secondary stack structure away from the main stack structure, protects the secondary stack structure, and covers the surface of the first dielectric layer. The first dielectric layer is directly attached to the third dielectric layer, and the materials of the first dielectric layer and the third dielectric layer are both dielectric materials, and the coefficient of thermal expansion (CTE) of the two is the same or similar. Therefore, during high-temperature expansion and low-temperature cooling, the expansion and contraction of the first dielectric layer and the third dielectric layer are the same or similar, and the interaction force between the first dielectric layer and the third dielectric layer can be ignored Regardless, the third dielectric layer can mechanically protect the first dielectric layer. In the same way, the first dielectric layer located on the surface of the main stack structure is directly attached to the second dielectric layer located on the surface of the sub-stack structure, and the materials of the first dielectric layer and the second dielectric layer are also dielectric materials . Therefore, the interaction force between the first dielectric layer and the second dielectric layer can be ignored. In this way, during the high-temperature expansion and low-temperature cooling process, the interaction force among the first dielectric layer, the second dielectric layer, and the third dielectric layer can be ignored. The risk of stress caused by material CTE mismatch is reduced, thereby reducing the deformation stress imposed by other layers on the main stack structure, and can reduce the possibility of cracks in the main stack structure. Since the interaction force between the first dielectric layer, the second dielectric layer and the third dielectric layer is negligible, there is no need to increase the thickness of the main stack in this case. The ability of the structure to resist deformation stress can reduce the thickness of the main stack structure stack, thereby reducing the thickness of the chip stack package structure.

Optionally, the thermal expansion coefficient of the material constituting the first dielectric layer and the thermal expansion coefficient of the material constituting the third dielectric layer are the same or similar. In this way, in the process of high temperature expansion and low temperature cooling, the deformability of the first dielectric layer and the third dielectric layer are the same or approximately the same, and the interaction force between the two is almost negligible, which can reduce the stress and deformation caused by The main stack structure may appear to be split.

Optionally, the chip stack package structure further includes a first plastic encapsulation layer, and the first plastic encapsulation layer is disposed on a surface of the third dielectric layer away from the first dielectric layer. By providing the first plastic encapsulation layer, no matter how large the thickness of the secondary stack structure is, the first plastic encapsulation layer can play a role of packaging protection, which can meet various packaging requirements.

Optionally, the first plastic encapsulation layer and the third dielectric layer expose the surface of the sub-stack structure away from the first dielectric layer, and are flush with the surface of the sub-stack structure away from the first dielectric layer. The first plastic encapsulation layer and the third dielectric layer expose the surface of the sub-stack structure away from the first dielectric layer, which can improve the heat dissipation effect of the sub-stack structure.

Optionally, the material constituting the first dielectric layer, the material constituting the second dielectric layer, and the material constituting the third dielectric layer are the same. The materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are the same, and the CTE of the three is the same. The expansion and contraction of the three are the most similar during the high temperature expansion and low temperature cooling process. The interaction force is the smallest.

Optionally, along the direction perpendicular to the main stack structure, the thickness of the secondary stack structure is greater than the thickness of the third dielectric layer. In the embodiment of the present application, the sub-stack structure having a thickness greater than the thickness of the third dielectric layer can be packaged, which has a wide range of applications.

Optionally, the main stack structure further includes: a main bare chip located on the side of the first dielectric layer away from the second dielectric layer; a signal transfer layer located on the side of the main bare chip away from the first dielectric layer; signal transfer The side of the layer away from the main bare chip is provided with interconnection terminals; a plurality of vias penetrate the main bare chip, one end of the via is electrically connected with the first bump, and the other end is electrically connected with the interconnection terminal. A via hole is formed inside the main bare chip to complete signal transmission, which can reduce the cross-sectional area of the main stack structure.

Optionally, the secondary stacked structure further includes a secondary bare chip, which is located on the side of the second dielectric layer away from the first dielectric layer; the active surface of the secondary bare chip faces the second dielectric layer and is connected to the second convex Click the electrical connection. Optionally, the chip stack package structure further includes: a first redistribution layer located on the side of the first plastic encapsulation layer away from the third dielectric layer; an adhesive layer located between the first plastic encapsulation layer and the first redistribution layer For bonding the first plastic encapsulation layer and the first rewiring layer; the second rewiring layer is located on the side of the main stack structure away from the third dielectric layer, and is in direct contact and electrical connection with the main stack structure; the second plastic encapsulation layer is located on the first Between the one redistribution layer and the second redistribution layer, and is located at the periphery of the main stack structure and the sub-stack structure; a plurality of conductive parts, the conductive part penetrates the second plastic encapsulation layer, and both ends of the conductive part are connected to the first redistribution The layer and the second redistribution layer are electrically connected. Since the second redistribution layer and the interconnection terminals are directly contacted and bonded, no solder is required in the middle, which can reduce the thickness of the chip stack package structure.

Optionally, the chip stack package structure further includes: a substrate, which is located on the side of the main stack structure away from the third dielectric layer, and is bonded to the main stack structure through solder balls; and an underfill layer is filled between the main stack structure and the substrate. The first rewiring layer is located on the side of the first plastic encapsulation layer away from the third dielectric layer; the second plastic encapsulation layer is located between the first rewiring layer and the substrate, and is located between the main stack structure and the The periphery of the sub-stack structure; a plurality of conductive parts, the conductive part penetrates the second plastic encapsulation layer, and both ends of the conductive part are electrically connected to the first redistribution layer and the substrate, respectively. During packaging, the interconnection terminals are directly bonded to the prepared substrate without the need to prepare a rewiring layer during packaging, which can save time and improve efficiency.

Optionally, the chip stack package structure further includes a top-level package; the top-level package is located on the side of the first redistribution layer away from the first plastic encapsulation layer, and is electrically connected to the first redistribution layer.

In a second aspect, an electronic device is provided, including the chip stack package structure of any one of the first aspects.

Description of the drawings

FIG. 1 is a schematic structural diagram of an electronic device provided by an embodiment of this application;

Fig. 2a is a top view of a chip stack package structure provided by an embodiment of the present application;

Figure 2b is a cross-sectional view taken along the line A1-A2 in Figure 2a;

Figure 3 is a cross-sectional view taken along the line A1-A2 in Figure 2a;

Figure 4 is a cross-sectional view taken along the line A1-A2 in Figure 2a;

Figure 5a is a cross-sectional view taken along the line A1-A2 in Figure 2a;

Figure 5b is a cross-sectional view along the line A1-A2 in Figure 2a;

Figure 6a is a cross-sectional view taken along the line A1-A2 in Figure 2a;

Figure 6b is a cross-sectional view taken along the line A1-A2 in Figure 2a;

Figure 6c is a cross-sectional view taken along the line A1-A2 in Figure 2a;

Figure 6d is a cross-sectional view taken along the line A1-A2 in Figure 2a;

Figure 6e is a cross-sectional view taken along the line A1-A2 in Figure 2a;

FIG. 7a is a schematic diagram of a chip stack package structure provided by an embodiment of the application;

FIG. 7b is a schematic structural diagram of a main stack structure and a secondary stack structure provided by an embodiment of the application;

8a-8m are schematic diagrams of the packaging process of the chip stack package structure shown in FIG. 7a;

FIG. 9 is a schematic diagram of another chip stack package structure provided by an embodiment of the application;

10a-10e are schematic diagrams of the packaging process of the chip stack package structure shown in FIG. 9.

Reference signs:

1-electronic equipment; 2-display module; 3-middle frame; 4-shell; 5-cover plate; 100-chip stack package structure; 10-main stack structure; 12-first dielectric layer; 13-section One bump; 14-main bare chip; 141-via; 142-main pad; 15-signal transfer layer; 151-metal part; 152-insulation layer; 16-interconnect terminal; 17-third plastic package Layer; 171-first plastic via; 20-top package body; 30-sub-stack structure; 32-second dielectric layer; 33-second bump; 34-sub bare chip; 341-sub-pad; 40 -Third dielectric layer; 41-dielectric film layer; 50-first molding layer; 51-molding film layer; 60-first rewiring layer; 70-second rewiring layer; 80-second molding layer; 81-conductive part; 90-adhesive layer; 91-substrate; 92-solder ball; 96-underfill layer.

Detailed ways

Unless otherwise defined, the technical terms or scientific terms used in this application shall have the usual meanings understood by those skilled in the art. The terms "first", "second", "third" and similar words used in the specification and claims of this application do not denote any order, quantity or importance, but are only used to distinguish different components. Therefore, the features defined with "first", "second", and "third" may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

The directional terms such as "left", "right", "upper", and "lower" are defined relative to the schematic placement of the components in the drawings. It should be understood that these directional terms are relative concepts, and they are used for Relative to the description and clarification, it can change accordingly according to the change in the position where the component is placed.

The embodiment of the application provides an electronic device, which can be a terminal device with a display interface such as a mobile phone, a TV, a monitor, a tablet computer, a car computer, etc., or a smart display wearable device such as a smart watch, a smart bracelet, or Communication equipment such as servers, storages, base stations, or smart cars, etc. The embodiments of the present application do not impose special restrictions on the specific form of the above-mentioned electronic equipment. For the convenience of description, the following embodiments all take the electronic device as a mobile phone as an example for description.

In this case, as shown in FIG. 1, the electronic device 1 mainly includes a display module 2, a middle frame 3, a casing (also called a battery cover, a rear casing) 4 and a cover 5.

The display module 2 has a light-emitting side that allows people to see the display screen and a back surface opposite to the above-mentioned light-emitting side. The back of the display module 2 is close to the middle frame 3 and the cover plate 5 is provided on the light-emitting side of the display module 2.

The above-mentioned display module 2 includes a display panel (DP).

In a possible embodiment of the present application, the display module 2 is a liquid crystal display module. In this case, the above-mentioned display screen is a liquid crystal display (LCD). Based on this, the display module 2 also includes a backlight unit (BLU) located on the back of the liquid crystal display screen (away from the side surface of the LCD for displaying images).

The backlight module can provide a light source to the liquid crystal display, so that each sub-pixel in the liquid crystal display can emit light to realize image display.

Or, in another possible embodiment of the present application, the display module 2 is an organic light emitting diode display module. In this case, the above-mentioned display screen is an organic light emitting diode (OLED) display screen. Since each sub-pixel in the OLED display screen is provided with an electroluminescent layer, the OLED display screen can realize self-luminescence after receiving the working voltage. In this case, there is no need to provide the above-mentioned backlight module in the display module 2 with the OLED display screen.

The cover plate 5 is located on the side of the display module 2 away from the middle frame 3, and the cover plate 5 may be, for example, cover glass (CG), which may have certain toughness.

The middle frame 3 is located between the display module 2 and the housing 4, and the surface of the middle frame 3 away from the display module 2 is used to install internal components such as batteries, printed circuit boards (PCB), cameras, antennas, etc. . After the casing 4 and the middle frame 3 are closed, the above-mentioned internal elements are located between the casing 4 and the middle frame 3.

The above-mentioned electronic device 1 also includes electronic devices such as a motherboard, a system-on-chip (SOC), and a chip stack package structure arranged on a PCB. The PCB is used to carry the above-mentioned electronic devices and complete signal interaction with the above-mentioned electronic devices.

Taking the chip-on-package structure as an example, the smaller the size of the chip-on-package structure, the faster the signal transmission speed inside, and the higher the bandwidth of the electronic device 1.

Based on this, an embodiment of the present application provides a chip stack package structure 100, as shown in FIG. 2a, which includes a main stack structure 10, a plurality of sub stack structures 30, and a third dielectric layer 40.

As shown in FIG. 2b (a cross-sectional view along the line A1-A2 in FIG. 2a), the side of the first surface a1 of the main stack structure 10 has a first dielectric layer 12 and a first protrusion exposed on the surface of the first dielectric layer 12. Point 13.

The first surface a1 of the main stack structure 10 provided with the first dielectric layer 12 may be an active surface of the main stack structure 10 or a non-active surface of the main stack structure 10. The active surface refers to the side of the main stack structure 10 where transistors are provided, and the non-active surface refers to the side of the main stack structure 10 where no transistors are provided.

The material constituting the first dielectric layer 12 is a dielectric material, and the material constituting the first dielectric layer 12 may be, for example _{, a metal oxide material such as silicon dioxide (SiO 2} ), or the material constituting the first dielectric layer 12 may be Silicon nitride (Si ₃ N ₄ ), etc. The material constituting the first bump 13 is a simple metal, and the material constituting the first bump 13 is, for example, copper (Cu).

The side of the second surface b2 of the sub-stack structure 30 includes a second dielectric layer 32 and a plurality of second bumps 33 exposed on the surface of the second dielectric layer 32.

Wherein, the second surface b2 of the secondary stack structure 30 faces the first surface a1 of the main stack structure 10, the first dielectric layer 12 is attached to the second dielectric layer 32, and a second bump 33 and a first bump are attached. Point 13 electrical connection.

The material constituting the second dielectric layer 32 is a dielectric material. The material constituting the second dielectric layer 32 may be, for example _{, a metal oxide material such as SiO 2} or the material constituting the second dielectric layer 32 may be Si ₃ N ₄ or the like. . The material constituting the second bump 33 is a simple metal, and the material constituting the second bump 33 is, for example, Cu.

The embodiment of the present application does not limit the arrangement of the multiple secondary stacking structures 30, and the multiple secondary stacking structures 30 can be arranged regularly or irregularly as required.

In addition, as shown in FIG. 2a, the dimensions (or referred to as cross-sectional areas) of the plurality of sub-stacked structures 30 may be the same, or may be completely different, or may be partially the same. In the same way, the functions of the multiple sub-stacked structures 30 may be the same, or may be completely different, or may be partially the same.

For example, the chip stack package structure 100 includes two sub-stack structures 30. The two sub-stacked structures 30 may be a combination of a processor chip and a memory chip. For example, the two sub-stacked structures 30 may be an application processor (AP) chip and a wide input and output dynamic random access memory (wide IO), respectively. dynamic random access memory, WIO DRAM) chip.

When the first bump 13 and the second bump 33 are electrically connected, the materials of the first dielectric layer 12 and the second dielectric layer 32 are both dielectric materials. Therefore, the first dielectric layer 12 and the second dielectric layer 32 are also connected. In other words, the main stack structure 10 and the sub stack structure 30 are electrically connected through a hybrid bonding (HB) process.

The third dielectric layer 40 is located on the side of the sub-stacked structure 30 away from the first dielectric layer 12 and is attached to the first dielectric layer 12. In other words, the position on the first dielectric layer 12 that is not electrically connected to the secondary stack structure 30 is covered by the third dielectric layer 40.

Wherein, the material constituting the third dielectric layer 40 is a dielectric material, the material constituting the third dielectric layer 40 may be, for example _{, a metal oxide material such as SiO 2} or the material constituting the third dielectric layer 40 is Si ₃ N ₄ and so on.

The material constituting the third dielectric layer 40, the material constituting the second dielectric layer 32, and the material constituting the first dielectric layer 12 may be the same or different, but they are all dielectric materials, and the thermal expansion coefficient is about 0.3~ 1.5ppm/℃.

Among them, in order to make the first dielectric layer 12, the second dielectric layer 32 and the third dielectric layer 40 have the same or similar degree of thermal deformation, so as to reduce the possibility of the main stack structure 10 cracking caused by the stress deformation. In some embodiments, the thermal expansion coefficient of the material constituting the first dielectric layer 12, the thermal expansion coefficient of the material constituting the second dielectric layer 32, and the thermal expansion coefficient of the material constituting the third dielectric layer 40 are the same or similar. . In the embodiment of the present application, the third dielectric layer 40 may be formed by, for example, a filling process (filling) or a deposition process.

The chip stack package structure 100 provided in the embodiment of the present application uses a hybrid bonding process to electrically connect the main stack structure 10 and the auxiliary stack structure 30. Since the adjacent first bump 13 and the adjacent second bump 33 are insulated and isolated by the first dielectric layer 12 and the second dielectric layer 32, respectively, the first dielectric layer 12 and the second dielectric layer 32 are stable Good performance and low liquidity. Therefore, the distance between the adjacent first bumps 13 and the adjacent second bumps 33 can be set smaller, for example, it can reach about 9um, or even smaller, which greatly increases the main stack structure 10 and the sub stack structure. 30 interconnect density. Compared with the related art that electrically connects the main stack structure 10 and the sub stack structure 30 through solder balls through the micro bump bonding process, the chip stack package structure 100 provided in the embodiment of the present application is in the sub stack structure 30 In the case of a fixed size, the number of input/output (I/O) interfaces on the secondary stack structure 30 can be increased compared with related technologies to meet the performance requirements of the secondary stack structure 30. Under the condition that the number of I/O interfaces on the secondary stack structure 30 remains unchanged, the size of the secondary stack structure 30 can be reduced compared with the related art to meet the requirement of reducing the size of the secondary stack structure 30.

In addition, in the chip stack package structure 100 provided by the embodiment of the present application, the third dielectric layer 40 is located on the side of the sub-stack structure 30 away from the main stack structure 10 to protect the sub-stack structure 30 and cover the first dielectric layer. The surface of 12. The first dielectric layer 12 is directly attached to the third dielectric layer 40, and the materials of the first dielectric layer 12 and the third dielectric layer 40 are both dielectric materials, and the coefficient of thermal expansion of the two CTE) are the same or similar. Therefore, during high-temperature expansion and low-temperature cooling, the expansion and contraction of the first dielectric layer 12 and the third dielectric layer 40 are the same or similar, and the first dielectric layer 12 and the third dielectric layer 40 are mutually The force can be ignored, and the third dielectric layer 40 can mechanically protect the first dielectric layer 12.

Similarly, the first dielectric layer 12 on the surface of the main stack structure 10 is directly attached to the second dielectric layer 32 on the surface of the sub stack structure 30, and the materials of the first dielectric layer 12 and the second dielectric layer 32 are They are also dielectric materials. Therefore, the interaction force between the first dielectric layer 12 and the second dielectric layer 32 is negligible. In this way, during the high-temperature expansion and low-temperature cooling process, the interaction force among the first dielectric layer 12, the second dielectric layer 32, and the third dielectric layer 40 can be ignored. The risk of stress caused by material CTE mismatch is reduced, thereby reducing the deformation stress applied to the main stacked structure 10 by other film layers, and the possibility of cracks in the main stacked structure 10 can be reduced.

Since the interaction force between the first dielectric layer 12, the second dielectric layer 32, and the third dielectric layer 40 is negligible, in this case, there is no need to increase the thickness of the main stacked structure 10 To improve the ability of the main stack structure 10 to resist deformation stress, the thickness of the stack of the main stack structure 10 can be reduced, thereby reducing the thickness of the chip stack package structure 100.

Based on this, in order to minimize the interaction force among the first dielectric layer 12, the second dielectric layer 32, and the third dielectric layer 40, and simplify the process. In some embodiments, the material constituting the first dielectric layer 12, the material constituting the second dielectric layer 32, and the material constituting the third dielectric layer 40 are the same.

In a possible embodiment, as shown in FIG. 3 (a cross-sectional view along the line A1-A2 in FIG. 2a), the third dielectric layer 40 is away from the first surface c1 of the first dielectric layer 12, and the sub-stack structure The first surface b1 (the first surface b1 is opposite to the second surface b2) away from the first dielectric layer 12 is flush.

In this way, the third dielectric layer 40 exposes the first surface b1 of the sub-stack structure 30 away from the first dielectric layer 12.

Since the heat conduction effect of the third dielectric layer 40 is not very good, after the third dielectric layer 40 covers the surface of the sub-stack structure 30, it will affect the heat dissipation of the sub-stack structure 30. Therefore, after the third dielectric layer 40 exposes the first surface b1 of the sub-stack structure 30 away from the first dielectric layer 12, the heat generated by the sub-stack structure 30 can be directly dissipated from the first surface b1. Thereby, the heat dissipation effect of the sub-stack structure 30 can be improved.

In a possible embodiment, as shown in FIG. 4 (a cross-sectional view along the line A1-A2 in FIG. 2a), the chip stack package structure further includes a first plastic encapsulation layer 50, and the first plastic encapsulation layer 50 is disposed on the third dielectric The layer 40 is on the first surface c1 away from the main stack structure 10.

The material of the first plastic encapsulation layer 50 may be, for example, epoxy molding compound (EMC), and its thermal expansion coefficient is about 6-10 ppm/°C. The first plastic encapsulation layer 50 can be prepared by, for example, a molding filling process.

In this way, after the first plastic encapsulation layer 50 plasticizes and fills the secondary stack structure 30, the first surface d1 of the first plastic encapsulation layer 50 away from the main stack structure 10 is a plane parallel to the main stack structure 10.

In the case where the thickness of the sub-stack structure 30 is relatively thick, the thickness of the third dielectric layer 40 may not meet the requirements because the third dielectric layer 40 is restricted by materials and processes. That is, the thickness h1 of the third dielectric layer 40 in the first direction X is smaller than the thickness h2 of the sub-stacked structure 30 in the first direction, resulting in that the first surface c1 of the third dielectric layer 40 away from the main stacked structure 10 is not flat. And affect the package. Therefore, the first surface c1 of the third dielectric layer 40 away from the main stacked structure 10 is covered with the first plastic encapsulation layer 50. The first plastic encapsulation layer 50 uses a molding process, and the first plastic encapsulation layer 50 is away from the main stacked structure 10 The first surface d1 is a plane parallel to the main stack structure 10 to play a role of leveling. In this case, the thickness of the first plastic encapsulation layer 50 can be adjusted according to the thickness of the sub-stack structure 30 to be suitable for packaging the sub-stack structure 30 with different thicknesses. At the same time, the first plastic encapsulation layer 50 can also protect the third dielectric layer 40.

Based on this, the chip stack package structure provided by the embodiment of the present application does not limit the relationship between the thickness h2 of the secondary stack structure 30 and the thickness h1 of the third dielectric layer 40. As shown in FIG. 4, along the direction perpendicular to the main stack structure 10 (first direction X), the thickness h2 of the sub-stack structure 30 is greater than the thickness h1 of the third dielectric layer 40.

Although, the thermal expansion coefficient of the material constituting the first plastic encapsulation layer 50 (for example, 6-10 ppm/°C) and the thermal expansion coefficient of the material constituting the first dielectric layer 12 (for example, 0.3-1.5 ppm/°C) are quite different, resulting in The first plastic encapsulation layer 50 and the first dielectric layer 12 have different degrees of deformation. However, since the material of the first dielectric layer 12 and the material of the third dielectric layer 40 are both dielectric materials, the coefficient of thermal expansion is the same or similar, and the degree of deformation of the two is the same or similar. Therefore, in the chip stack package structure of the embodiment of the present application, a third dielectric layer 40 is arranged between the first plastic encapsulation layer 50 and the first dielectric layer 12, and the first plastic encapsulation layer 50 is directly attached to the third dielectric layer 40. Together. As a result, the deformation force generated during the high temperature expansion and low temperature cooling process of the first plastic encapsulation layer 50 is relieved by the third dielectric layer 40 and hardly reaches the first dielectric layer 12. The deformation force between the third dielectric layer 40 and the first dielectric layer 12 is very small. Therefore, even if the chip stack package structure 100 is provided with the first plastic encapsulation layer 50, the deformation of the first dielectric layer 12 during the high temperature expansion and low temperature cooling process is almost negligible, which greatly reduces the possibility of cracks in the main stack structure 10 Sex.

In a possible embodiment, since the heat dissipation effect of the first plastic encapsulation layer 50 and the third dielectric layer 40 is poor, in order to improve the heat dissipation effect of the sub-stack structure 30. As shown in FIG. 5a (a cross-sectional view along the line A1-A2 in FIG. 2a), the first plastic encapsulation layer 50 and the third dielectric layer 40 expose the surface of the sub-stacked structure 30 away from the first dielectric layer 12 (the first surface b1 ).

In order to facilitate the packaging of other components, in a possible embodiment, as shown in FIG. 5a, the first plastic encapsulation layer 50 and the third dielectric layer 40 and the sub-stack structure 30 are far away from the first surface of the first dielectric layer 12 b1 is flush.

According to the selected thickness h2 of the plurality of sub-stacked structures 30, in some embodiments, as shown in FIG. 5a, the thickness of the plurality of sub-stacked structures 30 is perpendicular to the direction (first direction X) of the main stacked structure 10 h2 is equal, and the first plastic encapsulation layer 50 and the third dielectric layer 40 are flush with the first surface b1 of each sub-stacked structure 30.

In other embodiments, along the first direction X, the thickness h2 of the plurality of sub-stacked structures 30 is not equal. The first plastic encapsulation layer 50 and the third dielectric layer 40 are flush with the first surface b1 of the sub-stacked structure 30 with a large thickness.

For example, as shown in FIG. 5b (a cross-sectional view along the line A1-A2 in FIG. 2a), the thickness of a stacked structure 30 is h2-1, and the thickness of a stacked structure 30 is h2-2, and h2-2 is greater than h2. -1. In this case, the first plastic encapsulation layer 50 and the third dielectric layer 40 are flush with the first surface b1 of the sub-stacked structure 30 with a thickness of h2-2. The first plastic encapsulation layer 50 and the third dielectric layer 40 do not expose the first surface b1 of the sub-stacked structure 30 with a thickness of h2-1.

Regarding the structure of the main stack structure 10, in a possible embodiment, as shown in FIG. 6a (a cross-sectional view along the line A1-A2 in FIG. 2a), the main stack structure 10 includes the first dielectric layer 12 on the basis of , Also includes: the main bare chip 14. The main bare chip 14 is located on the side of the first dielectric layer 12 away from the second dielectric layer 32.

Regarding the structure of the main bare chip 14, for example, it includes a wafer layer made of silicon and a wiring layer made up of alternating dielectric layers and metal wiring. The wiring layer is arranged on the wafer layer, and the wiring layer is away from the surface of the wafer layer. As the active surface d1 of the master die 14.

As shown in FIG. 6 a, the main stack structure 10 further includes a via hole 141 and a main pad 142. The via hole 141 penetrates the main bare chip 14, and one end of the via hole 141 is electrically connected to the main pad 142. The main pad 142 is located on the active surface d1 of the main die 14.

Wherein, the via hole 141 penetrates the main bare chip 14, that is, the via hole 141 penetrates the wafer layer and the wiring layer. It can be understood that, in order to prevent the via 141 from damaging the wiring of the wiring layer, the penetrating position of the via 141 should avoid the metal wiring in the wiring layer.

The material constituting the main pad 142 may be, for example, aluminum. In this case, the main pad 142 is an aluminum pad.

In some embodiments, as shown in FIG. 6 a, the active surface d1 of the main die 14 faces the first dielectric layer 12. The via 141 is electrically connected to the main pad 142, and the main pad 142 is electrically connected to the first bump 13.

In other embodiments, as shown in FIG. 6b (a cross-sectional view along the line A1-A2 in FIG. 2a), the active surface d1 of the main die 14 faces away from the sub-stack structure 30. The via hole 141 is directly electrically connected to the first bump 13.

In other words, the main stack structure 10 and the sub stack structure 30 are packaged using an embedded die in substrate packaging process.

The main stack structure 10 further includes a signal interposer 15 located on the side of the main bare chip 14 away from the first dielectric layer 12. The signal transfer layer 15 has an interconnection terminal (copper via) 16 on a side away from the main bare chip 14, and the interconnection terminal 16 is electrically connected to the via 141.

It can be understood that, as shown in FIGS. 6 a and 6 b, the signal transfer layer 15 includes an insulating layer 152 and a metal portion 151 penetrating the insulating layer 152. The interconnection terminal 16 is electrically connected to the via hole 141, and in essence, the interconnection terminal 16 is electrically connected to the via hole 141 through the metal portion 151.

It can be seen from the above that, in the chip stack package structure 100 provided by the embodiments of the present application, the main stack structure 10 receives less deformation stress. Therefore, the thickness of the main stack structure 10 can be relatively thin, that is, the thickness of the main bare chip 14 It can be thinner. Due to the limitation of the process, when the via hole 141 is fabricated, it is usually necessary to meet a certain ratio of aperture and thickness. In other words, the pore size is directly proportional to the thickness. In this way, when the thickness of the main bare chip 14 is relatively thin, the aperture of the via hole 141 can be made smaller, and the density of the via hole 141 can be increased, thereby increasing the number of transmission ports of the main stack structure 10.

Regarding the structure of the main stack structure 10, in another possible embodiment, as shown in FIG. 6c (a cross-sectional view along the line A1-A2 in FIG. 2a), the main stack structure 10 is formed on the basis of the first dielectric layer 12 Above, it also includes: the main bare chip 14, the signal transfer layer 15, and the third plastic encapsulation layer 17.

The main bare chip 14 is located on the side of the first dielectric layer 12 away from the second dielectric layer 32. The active surface d1 of the main bare chip 14 is away from the first dielectric layer 12, and the active surface d1 of the main bare chip 14 is provided with a main pad 142, but the main stack structure 10 does not include the above-mentioned via 141.

The signal transfer layer 15 is located on the side of the main bare chip 14 away from the first dielectric layer 12. The signal transfer layer 15 has an interconnection terminal 16 on a side away from the main bare chip 14, and the interconnection terminal 16 is electrically connected to the main pad 142.

The third plastic encapsulation layer 17 is located between the first dielectric layer 12 and the signal transfer layer 15 and is located outside the main bare chip 14. The third plastic encapsulation layer 17 has a first through molding via (TMV) 171 penetrating the third plastic encapsulation layer 17, and both ends of the first through molding via 171 are electrically connected to the first bump 13 and the interconnection terminal 16 respectively .

In other words, the main stack structure 10 and the sub stack structure 30 are packaged by fan-out wafer level packaging (FOWL) technology.

Hereinafter, for ease of description, the main stack structure 10 is described as an example of the structure shown in FIG. 6a.

Regarding the structure of the sub-stacked structure 30, in a possible embodiment, as shown in FIG. 6d (a cross-sectional view along the line A1-A2 in FIG. 2a), the sub-stacked structure 30 includes a sub-die 34, and the sub-die 34 is located The second dielectric layer 32 is away from the side of the first dielectric layer 12.

Regarding the structure of the sub-bare chip 34, for example, it includes a wafer layer made of silicon and a wiring layer made up of alternating dielectric layers and metal wiring. The wiring layer is provided on the wafer layer, and the wiring layer is away from the surface of the wafer layer. As the active surface e1 of the sub-die 34.

Wherein, as shown in FIG. 6d, the active surface e1 of the sub-die 34 has sub-pads 341, the active surface e1 of the sub-die 34 faces the second dielectric layer 32, the sub-pads 341 and the second bumps 33 electrical connection. The material constituting the sub-pad 341 may be aluminum, for example.

Regarding the structure of the sub-stacked structure 30, in order to enrich the functions of the sub-stacked structure 30, without increasing the cross-sectional area of the sub-stacked structure 30. In another possible embodiment, as shown in FIG. 6e (a cross-sectional view along the line A1-A2 in FIG. 2a), at least one of the plurality of auxiliary stacked structures 30 includes a plurality of stacked auxiliary bare structures. The chip 34 is electrically connected to the adjacent secondary bare chips 34, and the secondary bare chip 34 closest to the second dielectric layer 32 is electrically connected to the second dielectric layer 32.

Hereinafter, several detailed embodiments are used to illustrate the chip stack package structure 100 provided in the present application.

Example one

As shown in FIG. 7 a, the chip stack package structure 100 includes a main stack structure 10, a plurality of sub stack structures 30, a third dielectric layer 40 and a first plastic encapsulation layer 50.

The main stack structure 10 includes a main bare chip 14 and a plurality of via holes 141 penetrating the main bare chip 14.

The main stack structure 10 further includes a first dielectric layer 12 located on the first side of the main bare chip 14.

As shown in FIG. 7 b, the first dielectric layer 12 includes a plurality of first bumps 13 penetrating the first dielectric layer 12. The first bump 13 is electrically connected to the via hole 141.

Regarding the structure of the first bump 13, in a possible embodiment, the first bump 13 is a columnar structure.

Regarding the structure of the first bump 13, in another possible embodiment, the first bump 13 has a T-shaped structure. In order to increase the contact area between the first bump 13 and the second bump 33, the stability of the electrical connection is improved.

For example, as shown in FIG. 7b, the first bump 13 includes a first bonding pad metal (BPM) and a first bonding pad via (BPV) that are electrically connected. The first bonding pad hole BPV1 is close to the main die 14 relative to the first bonding pad metal BPM1, the BPV1 is electrically connected to the main pad 142, and the cross-sectional area of the BPV1 is smaller than the cross-sectional area of the BPM1. The cross-sectional area here refers to the area parallel to the cross-section of the main stack structure 10.

As shown in FIG. 7a, the signal transfer layer 15 is located on the second side of the main bare chip 14 opposite to the first side. The signal transfer layer 15 includes an insulating layer 152 and a metal portion 151 penetrating the insulating layer 152. The metal part 151 is electrically connected to the via hole 141. The signal transfer layer 15 further includes an interconnection terminal 16 located on the side of the insulating layer 152 away from the main bare chip 14, and the interconnection terminal 16 is electrically connected to the metal portion 151.

The sub-stack structure 30 includes: a sub-die 34, and the active surface of the sub-die 34 faces the second dielectric layer 32. The sub-stack structure 30 further includes a second dielectric layer 32 and a plurality of second bumps 33 penetrating the second dielectric layer 32.

Regarding the structure of the second bump 33, as shown in FIG. 7b, the second bump 33 includes a second bonding pad metal BPM2 and a second bonding pad hole BPV2 that are electrically connected. The BPV2 is close to the sub-die 34 relative to the BPM2, the BPV2 is electrically connected to the sub-pad 341, and the cross-sectional area of the BPV2 is smaller than the cross-sectional area of the BPM2.

The second dielectric layer 32 and the first dielectric layer 12 are disposed oppositely and attached to each other. The second bump 33 is electrically connected to the secondary bare chip 34, and a second bump 33 is electrically connected to a first bump 13.

As shown in FIG. 7 a, the third dielectric layer 40 is located on the side of the sub-stacked structure 30 away from the first dielectric layer 12 and is bonded to the first dielectric layer 12.

The first plastic encapsulation layer 50 is disposed on the first surface of the third dielectric layer 40 away from the first dielectric layer 12.

The first plastic encapsulation layer 50 and the third dielectric layer 40 expose the first surface b1 of the auxiliary stacked structure 30 away from the main stacked structure 10 and are flush with the first surface b1 of the auxiliary stacked structure 30.

As shown in FIG. 7a, the chip stack package structure 100 further includes: a first redistribution layer (RDL) 60, a second redistribution layer 70, a second molding layer 80, and an adhesive layer 90.

The first redistribution layer 60 is located on the side of the first plastic encapsulation layer 50 away from the third dielectric layer 40.

The second redistribution layer 70 is located on the side of the main stack structure 10 away from the third dielectric layer 40, and the second redistribution layer 70 is in direct contact and electrical connection with the interconnection terminals 16 in the main stack structure 10.

The second plastic encapsulation layer 80 is located between the first rewiring layer 60 and the second rewiring layer 70 and is located at the periphery of the main stacked structure 10 and the auxiliary stacked structure 30.

A plurality of conductive portions 81, the conductive portion 81 penetrates the second plastic encapsulation layer 80, and both ends of the conductive portion 81 are electrically connected to the first redistribution layer 60 and the second redistribution layer 70, respectively.

Wherein, the conductive portion 81 may be, for example, a through molding via (TMV).

The bonding layer 90 is located between the secondary stack structure 30 and the first redistribution layer 60 and is used to bond the first molding layer 50 and the first redistribution layer 60.

Wherein, the material constituting the adhesive layer 90 may be, for example, a thermally conductive glue.

It is understandable that, as shown in FIG. 7a, when the first plastic encapsulation layer 50 exposes the first surface b1 of the secondary bare chip 34 away from the second dielectric layer 32, the adhesive layer 90 is further away from the secondary bare chip 34. The first surface b1 of the two dielectric layers 32 is bonded.

Further, as shown in FIG. 7a, the chip stack package structure 100 further includes: a top package body 20. The top package body 20 is located on the side of the first redistribution layer 60 away from the sub-stack structure 30, and the top package body 20 is connected to the first rewiring layer 60. The wiring layer 60 is electrically connected.

The top package body 20 may be electrically connected to the first redistribution layer 60 through soldering balls, for example.

According to the requirements of the chip stack package structure 100, the top package body 20 may be a stack of multiple memory chips. The top package 20 may be, for example, a memory chip.

When the chip stack package structure 100 is electrically connected to the PCB, for example, the second rewiring layer 70 may be electrically connected to the PCB through solder balls.

Hereinafter, the assembly process of the chip stack package structure 100 shown in FIG. 7a will be described.

As shown in FIG. 8 a, a via hole 141 penetrating the main bare chip 14 and a main pad 142 electrically connected to the via hole 141 are formed on the main bare chip 14. And the first dielectric layer 12 and the first bump 13 are formed on the surface where the main pad 142 is formed.

Wherein, as shown in FIG. 8a, at this time, the via hole 141 does not penetrate the main bare chip 14 but is only electrically connected to the main pad 142. The first bump 13 is exposed on the surface of the first dielectric layer 12 away from the main die 14 and is electrically connected to the main pad 142.

As shown in FIG. 8b, a second dielectric layer 32 and a second bump 33 are formed on the active surface of the secondary die 34 to form the secondary stack structure 30. The sub-pad 341 on the active surface of the sub-die 34 is electrically connected to the second bump 33.

Wherein, the process of forming the structure shown in FIG. 8a and forming the structure shown in FIG. 8b can be performed at the same time. Alternatively, the structure shown in FIG. 8b may be formed first.

As shown in FIG. 8c, then, a plurality of sub-stacked structures 30 are electrically connected to the main bare chip 14 on which the first bumps 13 are formed through a hybrid bonding process.

Wherein, the first dielectric layer 12 and the second dielectric layer 32 are bonded together, and the first bump 13 and the second bump 33 are electrically connected.

As shown in FIG. 8d, then, a dielectric film layer 41 covering the sub-stack structure 30 and the first dielectric layer 12 is formed on the first surface b1 of the sub-stack structure 30 away from the first dielectric layer 12.

As shown in FIG. 8e, then, a plastic film layer 51 covering the dielectric film layer 41 is formed on the first surface c1 of the dielectric film layer 41 away from the first dielectric layer 12.

As shown in FIG. 8f, the plastic encapsulation film layer 51 and the dielectric film layer 41 are then thinned to form the first plastic encapsulation layer 50 and the third dielectric layer 40.

The first plastic encapsulation layer 50 and the third dielectric layer 40 expose the first surface b1 of the auxiliary stacked structure 30 away from the main stacked structure 10 and are flush with the first surface b1 of the auxiliary stacked structure 30 away from the main stacked structure 10.

It should be noted that if the first plastic encapsulation layer 50 and the third dielectric layer 40 do not need to expose the secondary stack structure 30 away from the first surface b1 of the main stack structure 10, the plastic encapsulation film layer 51 and the dielectric film layer 41 are the chip stacks. The first plastic encapsulation layer 50 and the third dielectric layer 40 of the packaging structure 100.

As shown in FIG. 8g, then, the surface of the main bare chip 14 away from the first dielectric layer 12 is thinned to expose the via 141.

Wherein, the side where the first surface b1 of the secondary stack structure 30 is located can be placed on a carrier for carrying, and then the surface of the main bare chip 14 away from the first dielectric layer 12 can be thinned.

As shown in FIG. 8h, then, a signal transfer layer 15 is formed on the surface of the main bare chip 14 away from the first dielectric layer 12. The signal transfer layer 15 is electrically connected to the via hole 141.

As shown in FIG. 8i, then, the structure shown in FIG. 8h is attached to the first redistribution layer 60 having the conductive portion 81 in advance through the adhesive layer 90.

As shown in FIG. 8j, then, a molding material is filled to cover the conductive portion 81 and the interconnection terminal 16.

As shown in FIG. 8k, the molding material is then thinned to form a second molding layer 80 exposing the conductive portion 81 and the interconnection terminal 16.

As shown in FIG. 81, then, a second redistribution layer 70 is formed on the surface of the second encapsulation layer 80 away from the first redistribution layer 60. The second rewiring layer 70 is electrically connected to the conductive portion 81 and the interconnection terminal 16.

For example, the second rewiring layer 70 may be formed through an integrated fan-out (InFO) process.

Then, the top package body 20 is electrically connected to the first rewiring layer 60 to form a chip stack package structure 100 as shown in FIG. 7a to obtain a complete three-dimension package on package package (3D POP package) .

When it is necessary to electrically connect the chip stack package structure 100 shown in FIG. 7a to the PCB, as shown in FIG. 8m, the second rewiring layer 70 is electrically connected to the PCB.

In this embodiment, since the second redistribution layer 70 is in direct contact and electrical connection with the interconnection terminals 16, no solder is required in the middle, and the thickness of the chip stack package structure 100 can be reduced. In addition, the main stack structure 10 is electrically connected to the second redistribution layer 70, and the second redistribution layer 70 can be made thinner than a laminate substrate. Therefore, the thickness of the chip stack package structure 100 can be further reduced. In addition, the chip stack packaging structure 100 is compatible with both the integrated fan-out packaging process and the hybrid bonding stack packaging process to meet packaging requirements.

Example two

The main difference between the second embodiment and the first embodiment is that the electrical connection between the interconnection terminal 16 and the second redistribution layer 70 is different.

As shown in FIG. 9, the chip stacked package structure 100 includes a main stacked structure 10, a plurality of sub-stacked structures 30, a third dielectric layer 40, a first plastic encapsulation layer 50, a first redistribution layer 60, and a laminate substrate 91 , The second plastic encapsulation layer 80, the underfill layer 96 and the top package body 20.

The structure of the main stack structure 10, the sub stack structure 30, the third dielectric layer 40, the first plastic encapsulation layer 50, the first rewiring layer 60, the second plastic encapsulation layer 80 and the top package body 20 in the chip stack package structure 100 can be Refer to the description of FIG. 7a in the first embodiment.

In this embodiment, the chip stack package structure 100 may not include the adhesive layer 90, and the sub-stack structure 30 is not bonded to the first redistribution layer 60.

In addition, as shown in FIG. 9, the substrate 91 is located on the side of the main stack structure 10 away from the third dielectric layer 40, and is electrically connected to the interconnection terminals 16 in the main stack structure 10 through solder balls 92.

The underfill layer 96 is filled between the main stack structure 10 and the substrate 91, and is located at the periphery of the solder balls 92 and the interconnection terminals 16.

The first redistribution layer 60 and the substrate 91 are electrically connected through a conductive portion 81. The conductive portion 81 may be, for example, a TMV, and the conductive portion 81 may also be a solder ball.

Hereinafter, the assembly process of the chip stack package structure 100 shown in FIG. 9 will be described.

As shown in FIGS. 8a to 8h in the first embodiment, the main stack structure 10 and the sub stack structure 30 are electrically connected, and the third dielectric layer 40 and the first plastic encapsulation layer 50 are used for packaging.

As shown in FIG. 10a, then, the interconnection terminal 16 and the substrate 91 in the structure shown in FIG. 8h are electrically connected by solder balls 92.

As shown in FIG. 10b, an underfill glue is then filled between the signal transfer layer 15 and the substrate 91 to form an underfill glue layer 96.

As shown in FIG. 10c, then, the first redistribution layer 60 on which the conductive portion 81 is formed is electrically connected to the substrate 91.

As shown in FIG. 10d, a molding material is then filled between the first redistribution layer 60 and the substrate 91 to form a second molding layer 80.

Then, the top package body 20 is electrically connected to the first redistribution layer 60 to form a chip stack package structure 100 as shown in FIG. 9.

When the chip stack package structure 100 shown in FIG. 9 needs to be electrically connected to the PCB, as shown in FIG. 10e, the substrate 91 is electrically connected to the PCB.

In the embodiment of the present application, the interconnection terminal 16 is directly electrically connected to the prepared substrate 91 during packaging without preparing the second rewiring layer 70 during packaging, which can save time and improve efficiency.

The above are only specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention. It should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

A chip stack packaging structure is characterized in that it comprises:

A main stack structure, the main stack structure comprising a first dielectric layer and first bumps exposed on the surface of the first dielectric layer;

A plurality of sub-stacked structures, the sub-stacked structure includes a second dielectric layer and second bumps exposed on the surface of the second dielectric layer; the first dielectric layer and the second dielectric layer Bonding, the first bump is electrically connected to the second bump;

The third dielectric layer is located on the side of the secondary stack structure away from the first dielectric layer, and is attached to the first dielectric layer.
The chip stack package structure according to claim 1, wherein the thermal expansion coefficient of the material constituting the first dielectric layer and the thermal expansion coefficient of the material constituting the third dielectric layer are the same or similar.
The chip stack package structure according to claim 1 or 2, wherein the chip stack package structure further comprises a first plastic encapsulation layer, and the first plastic encapsulation layer is disposed on the third dielectric layer away from the first plastic encapsulation layer. On the surface of a dielectric layer.
4. The chip stack package structure of claim 3, wherein the first plastic encapsulation layer and the third dielectric layer expose a surface of the sub-stack structure away from the first dielectric layer, and are in contact with The surface of the secondary stack structure away from the first dielectric layer is flush.
The chip stack package structure according to any one of claims 1 to 4, wherein in a direction perpendicular to the main stack structure, the thickness of the secondary stack structure is greater than the thickness of the third dielectric layer.
5. The chip stack package structure according to any one of claims 1 to 5, wherein the main stack structure further comprises:

The main bare chip is located on the side of the first dielectric layer away from the second dielectric layer;

A signal transfer layer located on the side of the main bare chip away from the first dielectric layer; the signal transfer layer has an interconnection terminal on the side away from the main bare chip;

A plurality of via holes penetrate the main bare chip, one end of the via hole is electrically connected to the first bump, and the other end is electrically connected to the interconnect terminal.
The chip stack package structure according to any one of claims 1-6, wherein the sub-stack structure further comprises a sub-die, and the sub-die is located on the second dielectric layer away from the first One side of the dielectric layer;

The active surface of the secondary bare chip faces the second dielectric layer and is electrically connected to the second bump.
7. The chip stack package structure according to any one of claims 2-7, wherein the chip stack package structure further comprises:

The first rewiring layer is located on the side of the first plastic encapsulation layer away from the third dielectric layer;

An adhesive layer, located between the first plastic encapsulation layer and the first redistribution layer, and is used to bond the first plastic encapsulation layer and the first redistribution layer;

The second rewiring layer is located on the side of the main stack structure away from the third dielectric layer, and is in direct contact and electrical connection with the main stack structure;

The second plastic encapsulation layer is located between the first rewiring layer and the second rewiring layer, and is located at the periphery of the main stack structure and the auxiliary stack structure;

A plurality of conductive parts, the conductive part penetrates the second plastic encapsulation layer, and both ends of the conductive part are electrically connected to the first redistribution layer and the second redistribution layer, respectively.
7. The chip stack package structure according to any one of claims 2-7, wherein the chip stack package structure further comprises:

The substrate is located on the side of the main stack structure away from the third dielectric layer, and is bonded to the main stack structure through solder balls;

An underfill layer, which is filled between the main stack structure and the substrate, and is located at the periphery of the solder balls;

The first rewiring layer is located on the side of the first plastic encapsulation layer away from the third dielectric layer;

The second plastic encapsulation layer is located between the first rewiring layer and the substrate, and is located at the periphery of the main stack structure and the auxiliary stack structure;

A plurality of conductive parts, the conductive part penetrates the second plastic encapsulation layer, and both ends of the conductive part are electrically connected to the first redistribution layer and the substrate, respectively.
The chip stack package structure according to claim 8 or 9, wherein the chip stack package structure further comprises a top package body; the top package body is located on the first redistribution layer away from the first plastic encapsulation layer One side, and is electrically connected to the first redistribution layer.
An electronic device, characterized by comprising the chip stack package structure according to any one of claims 1-10.