TWI804094B - Chip package structure and manufacturing method thereof - Google Patents

Abstract

A chip package structure is provided. The chip package structure includes a redistribution structure, a chip, a first encapsulant, a plurality of conductive terminals and a second encapsulant. The redistribution structure has a first surface, a second surface opposite to the first surface, and a peripheral surface connecting the first surface and the second surface. The chip is disposed on the first surface of the redistribution structure and is electrically connected to the redistribution structure. The first encapsulant covers the redistribution structure and the chip, wherein the first encapsulant covers the peripheral surface of the redistribution structure. A plurality of conductive terminals are arranged on the second surface of the redistribution structure and are electrically connected to the redistribution structure. The second encapsulant is arranged on the redistribution structure, and covers the second surface of the redistribution structure and a bottom peripheral surface of the plurality of conductive terminals connected to the redistribution structure.

Description

Chip package structure and manufacturing method thereof

The present invention relates to a packaging structure, and in particular to a chip packaging structure and a manufacturing method thereof.

Generally, in the manufacturing method of wafer-level packaging (WLCSP) or coreless substrate structure (Core less), multi-layer dielectric layers are usually provided and combined with flip chip (flip chip) process and encapsulation process (Encapsulation) to achieve . However, whether it is a coreless substrate or a wafer-level package, although the dielectric layer used as a load bearing and electrical conduction is protected by the encapsulant, the sides of the dielectric layer are mostly exposed to the encapsulant. In addition, it is not only unable to be protected by sealing glue, but also affects the reliability of the chip packaging structure.

The invention provides a chip packaging structure and a manufacturing method thereof, which can effectively protect the rewiring structure, reduce the possibility of cracking at the edge of the rewiring structure during the manufacturing process, and further improve the reliability of electrical signals.

The chip packaging structure of the present invention includes a rewiring structure, a chip, a first packaging compound, a plurality of conductive terminals and a second packaging compound. The redistribution structure has a first surface, a second surface opposite to the first surface, and a surrounding surface connecting the first surface and the second surface. The chip is disposed on the first surface of the rewiring structure and is electrically connected to the rewiring structure. The first packaging colloid covers the rewiring structure and the chip, wherein the first packaging colloid covers the surrounding surface of the rewiring structure. A plurality of conductive terminals are disposed on the second surface of the redistribution structure and are electrically connected to the redistribution structure. The second encapsulant is disposed on the redistribution structure, and covers the second surface of the redistribution structure and the bottom peripheral surface of the plurality of conductive terminals connected to the redistribution structure.

The manufacturing method of the chip package structure of the present invention includes the following steps. A plurality of redistribution structures are formed, wherein the plurality of redistribution structures have a first surface, a second surface opposite to the first surface, and a surrounding surface connecting the first surface and the second surface. A plurality of wafers are disposed on the first surface of the corresponding plurality of redistribution structures to be electrically connected to the plurality of redistribution structures. The first encapsulant is formed to cover the plurality of redistribution structures and the plurality of chips, wherein the first encapsulant covers the surrounding surfaces of the plurality of redistribution structures. A plurality of conductive terminals are formed on the second surface of the plurality of redistribution structures to be electrically connected to the plurality of redistribution structures. The second encapsulant is formed on the plurality of redistribution structures to cover the second surfaces of the plurality of redistribution structures and the bottom peripheral surfaces of the plurality of conductive terminals connected to the plurality of redistribution structures. A singulation process is performed to form a chip package structure.

Based on the above, in the chip package structure of the present invention, each surface of the rewiring structure is coated with the first encapsulant and the second encapsulant, so as to form a complete protection for the rewiring structure, thereby reducing the cost in subsequent manufacturing processes. , so that the edges of the rewiring structure are cracked, and at the same time, external moisture can be prevented from penetrating into the rewiring structure, thereby improving the reliability of electrical signals.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

1A to 1I are cross-sectional views of the process of a manufacturing method of a chip package structure according to an embodiment of the present invention.

Referring to FIG. 1A , a temporary carrier 100 is provided, and a temporary adhesive layer 110 is formed on the temporary carrier 100 . Specifically, the temporary carrier 100 can be, for example, a glass substrate, a ceramic substrate, a silicon substrate, a plastic substrate, or other suitable substrates, and the shape of the substrate can be circular or rectangular, and the shape of the substrate is not limited, basically as long as the temporary carrier 100 has The substantially flat surface can be used to support the redistribution layer 120 (as shown in FIG. 1B ) subsequently formed thereon. The temporary adhesive layer 110 can be, for example, a release layer, such as thermal-release material, light-to-heat-conversion (LTHC) release coating, UV glue or other suitable material. In this embodiment, the temporary adhesive layer 110 can be formed on the temporary carrier 100 by coating or pasting, but it is not limited thereto.

Next, referring to FIG. 1B , a redistribution layer 120 is formed on the temporary adhesive layer 110 . In this embodiment, the method for forming the redistribution layer 120 may include but not limited to the following steps: First, form the patterned circuit layer 124 on the temporary adhesive layer 110 , such as a photolithographic etching process. Next, a dielectric layer 125 is formed on the temporary adhesive layer 110 to cover the patterned circuit layer 124, such as deposition or lamination process. Then, an opening OP1 is formed penetrating through the dielectric layer 125 to expose the patterned wiring layer 124 , such as by a photolithographic etching process. Forming the patterned circuit layer 126 on the dielectric layer 125 and simultaneously forming the via hole 127 in the opening OP1 is, for example, plating and lithographic etching processes. Finally, the dielectric layer 128 is formed on the dielectric layer 125 , such as deposition or lamination process and planarization process. Wherein, the dielectric layer 128 may expose the patterned circuit layer 126 .

In this embodiment, the redistribution layer 120 has a first surface 121 and a second surface 122 opposite to each other, and the second surface 122 of the redistribution layer 120 is in contact with the temporary adhesive layer 110 . The redistribution layer 120 may include patterned wiring layers 124 , 126 , dielectric layers 125 , 128 and a plurality of via holes 127 . A plurality of via holes 127 penetrate through the dielectric layer 125 to electrically connect the patterned circuit layer 124 and the patterned circuit layer 126 . The dielectric layer 128 is disposed on the aforementioned dielectric layer 125 and adjacent to the patterned wiring layer 126 side by side.

In this embodiment, the top surface of the dielectric layer 128 (that is, the surface of the dielectric layer 128 away from the temporary carrier 100 ) can be connected with the top surface of the patterned circuit layer 126 (that is, the surface of the patterned circuit layer 126 away from the temporary carrier 100 ). surface) and is the first surface 121 of the redistribution layer 120 . The bottom surface of the patterned wiring layer 124 (ie, the surface of the patterned wiring layer 124 facing the temporary carrier 100 ) can be flush with the bottom surface of the dielectric layer 125 (ie, the surface of the dielectric layer 125 facing the temporary carrier 100 ), and is for rewiring The second surface 122 of the layer 120 . Here, the material of the patterned circuit layers 124, 126 and the via hole 127 can be, for example, copper or other suitable conductive metal materials, and the material of the dielectric layer 125, 128 can be, for example, a polymer dielectric material, such as polyamide Amines or other suitable materials, but not limited thereto.

Next, please refer to FIG. 1B and FIG. 1C at the same time, perform an etching process on the redistribution layer 120 to expose part of the temporary adhesive layer 110, and form a plurality of redistribution structures 120a (FIG. 1C exemplarily depicts two , but not limited to). Specifically, in this step, a part of the dielectric layers 125 and 128 in the redistribution layer 120 (that is, the pre-defined cutting area) can be removed through a lithographic etching process to form the gap G, and the redistribution layer 120 is divided into a plurality of rewiring structures 120a that are electrically independent from each other. The gap G may be located on opposite sides of the redistribution structure 120a, between two adjacent redistribution structures 120a, and expose a portion of the temporary adhesive layer 110 . Furthermore, besides the original first surface 121 and the second surface 122 opposite to the first surface 121 , the multiple redistribution structures 120a further form a surrounding surface 123 connecting the first surface 121 and the second surface 122 .

Next, referring to FIG. 1D , a plurality of chips 130 are disposed on the first surface 121 of the corresponding plurality of redistribution structures 120 a to be electrically connected to the plurality of redistribution structures 120 a through the conductive connectors 134 . Specifically, the wafer 130 has an active surface 131 and a back surface 132 opposite to each other. The conductive connector 134 is disposed on the active surface 131 , and each chip 130 is electrically connected to the corresponding patterned redistribution layer 126 of the redistribution structure 120 a through the conductive connector 134 through a flip chip bonding process. In this step, there is no electrical connection between the chips 130 . Here, the conductive connector 134 may be, for example, a Cu pillar, a stud bump, a plating bump, a solder bump, a pad or other similar conductive elements. Connectors, but not limited to. The chip 130 can be, for example, a logic chip, a memory chip, a driver chip or a chip with other functions, but is not limited thereto.

Next, referring to FIG. 1E , the first encapsulant 140 is formed to cover the plurality of redistribution structures 120a and the plurality of chips 130, wherein the first encapsulant 140 can be filled into the gap G to cover the surroundings of the plurality of redistribution structures 120a Surface 123. Specifically, the first encapsulant 140 is formed on the temporary adhesive layer 110 by compression molding, transfer molding or similar methods. The first encapsulant 140 covers the active surface 131 and the back surface 132 of the chip 130, the first surface 121 and the surrounding surface 123 of the redistribution structure 120a, and the temporary adhesion exposed by the gap G between the redistribution structures 120a. The surface of layer 110. In this embodiment, the orthographic projection of the first encapsulant 140 on the temporary substrate 100 is greater than and completely covers the orthographic projection of the redistribution structure 120 a on the temporary substrate 100 . That is to say, the first encapsulant 140 of this embodiment can be filled in the gap G between the multiple redistribution structures 120a, and can completely cover the surrounding surfaces 123 of the multiple redistribution structures 120a, so as to avoid the The edge of the rewiring structure 120a is cracked and external moisture penetrates into the rewiring structure 120a, thereby affecting the reliability of electrical signals. Here, the material of the first encapsulant 140 may be, for example, molding compound, epoxy or the like, but is not limited thereto.

Next, please refer to FIG. 1F , remove the temporary carrier 100 and the temporary adhesive layer 110 to expose the second surface 122 of the plurality of redistribution structures 120 a and the surface 141 of the first encapsulant 140 (that is, the first encapsulant 140 a surface adjacent to the second surface 122). , continue referring to FIG. 1G , the structure is turned upside down, and a plurality of conductive terminals 150 are formed on the second surface 122 of the plurality of redistribution structures 120a to be electrically connected to the plurality of redistribution structures 120a. Specifically, after the temporary carrier 100 and the temporary adhesive layer 110 are removed, in order to avoid the removal of residual glue on the second surface 122 of the redistribution structure 120a, the second surface 122 is cleaned (or Removal of surface metal) to remove residues for subsequent solder ball bonding, wherein the removal method is, for example, a surface polishing process, but not limited thereto. The conductive terminals 150 can be used as external pins to electrically connect the chip 130 to other external components. Here, the conductive terminals 150 may be, for example, solder balls, bumps, conductive posts or the like, and the material of the conductive terminals 150 may be, for example, copper, tin-copper alloy, tin-silver-copper alloy or other suitable conductive materials. Materials are not limited to this.

After removing the temporary carrier board 100 and the temporary adhesive layer 110, it can be determined whether to use another temporary adhesive layer (not shown) and another temporary carrier board according to the degree of warpage of the overall structure at this stage. (not shown) attached to the surface 142 of the first encapsulant 140 adjacent to the back surface 132 of the chip 130, as a support for the subsequent process (for example, for supporting to form the conductive terminal 150 on the first rewiring structure 120a II surface 122 upper class). In addition, the temporary carrier and the temporary adhesive layer in this step can be removed before the final step (ie removed after the singulation process).

Referring to FIG. 1H, the second encapsulant 160 is formed on the plurality of redistribution structures 120a to cover the second surface 122 of the plurality of redistribution structures 120a and the plurality of conductive terminals 150 connected to the bottom peripheral surfaces of the plurality of redistribution structures 120a. 151. Specifically, the second encapsulant 160 is disposed on the second surface 122 of the plurality of redistribution structures 120 a and directly contacts the surface 141 of the first encapsulant 140 . In this way, the first encapsulant 140 and the second encapsulant 160 completely cover the six side surfaces (ie, the first surface 121 , the second surface 123 and the surrounding surface 123 ) of the plurality of rewiring structures 120a, and rewiring can be performed. Either side of the structure forms complete protection. In addition, since the first encapsulant 140 and the second encapsulant 160 are not formed in the same step, there is an interface between the first encapsulant 140 and the second encapsulant 160 . Here, the material of the second encapsulant 160 may be, for example, molding compound, epoxy, insulating resin or the like, but is not limited thereto. The material of the second encapsulant 160 may be the same as or different from that of the first encapsulant 140 .

In this embodiment, after the conductive terminals 150 are formed on the second surface 202 of the redistribution structure 120a ( FIG. 1G ), the second encapsulant 160 is then formed on the second surface of the redistribution structure 120a, so that the second The encapsulant 160 will cover the bottom peripheral surface 151 ( FIG. 1H ) of a plurality of conductive terminals 160 connected to a plurality of redistribution structures 120a, which can increase the strength of the base of the conductive terminals 150 (that is, the part connected to the redistribution structures 120a), thereby improving the overall The ability of the structure to resist falling.

Next, referring to FIG. 1H and FIG. 1I simultaneously, a singulation process is performed along the dicing line S to form a single chip package structure 10 .

In particular, the redistribution structure 120a of this embodiment exemplarily shows two layers of patterned circuit layers 124, 126 and two layers of dielectric layers 125, 128, but the present invention does not The number of electrical layers is limited. In other embodiments, the number of patterned wiring layers and dielectric layers in the redistribution layer can be increased or decreased according to actual needs, so that the redistribution wiring structure formed by the multi-layer patterned conductive layer and the multi-layer dielectric layer , and cooperate with the flip-chip bonding process of the chip to achieve the purpose of fan-out, and protect the chip packaging structure 10 through the second encapsulant 160 to form a complete six-sided protection effect.

Other embodiments are listed below for illustration. It must be noted here that the following embodiments use the component numbers and part of the content of the previous embodiments, wherein the same numbers are used to denote the same or similar components, and descriptions of the same technical content are omitted. For the description of omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

2A to 2D are cross-sectional flowcharts of a manufacturing method of a chip package structure according to another embodiment of the present invention. FIG. 2A to FIG. 2D are steps continuing FIG. 1F and replacing FIG. 1G to FIG. 1I . The same or similar components in the embodiment of FIG. 2A to FIG. 2D and the embodiment of FIG. 1A to FIG. 1I can be made using the same materials or methods, so the following descriptions of the same and similar in the two embodiments will not be repeated. . The difference between the embodiment shown in FIG. 2A to FIG. 2D and the embodiment shown in FIG. 1A to FIG. The redistribution structure 120a) of 1F and the second redistribution structure 222a. The manufacturing process of the chip package structure 20 will be described below.

Please refer to FIG. 1F and FIG. 2A at the same time, first remove the temporary carrier 100 and the temporary adhesive layer 110 to expose a plurality of first redistribution structures 221a (ie, the redistribution structure 120a in FIG. 1F ) and the first encapsulant 140 , wherein the plurality of first redistribution structures 221a are independent from each other and have a first interval G1 (ie, the interval G in FIG. 1C ). Next, after turning the structure upside down, a second redistribution layer 222 is formed on the plurality of first redistribution structures 221 a and the first encapsulant 140 to be electrically connected to the plurality of first redistribution structures 221 a. Specifically, the first redistribution structure 221a has a first surface 2211 (ie, the first surface 121 in FIG. 1F ), a third surface 2212 opposite to the first surface 2211 (ie, the second surface 122 in FIG. The first peripheral surface 2213 of the first surface 2211 and the third surface 2212 (ie, the peripheral surface 123 in FIG. 1F ). The second redistribution layer 222 has a second surface 2221 and a fourth surface 2222 opposite to each other, and the fourth surface 2222 contacts the third surface 2212 of each first redistribution structure 221a. That is to say, the third surface 2212 of the first redistribution structure 221a, the fourth surface 2222 of the second redistribution layer 222 and the surface 141 of the first encapsulant 140 facing the second redistribution layer 222 are actually coplanar.

In this embodiment, the second redistribution layer 222 includes dielectric layers 2224 , 2227 , a patterned circuit layer 2225 and a plurality of via holes 2226 . The dielectric layer 2224 is disposed on the plurality of first redistribution structures 221 a and the first encapsulant 140 . The patterned circuit layer 2225 is disposed on the dielectric layer 2224 . A plurality of via holes 2226 penetrate through the dielectric layer 2224 . The patterned circuit layer 2225 is electrically connected to the corresponding patterned circuit layer 126 through a plurality of via holes 2226 . The dielectric layer 2227 is disposed on the dielectric layer 2224 and covers the patterned circuit layer 2226 . The materials and formation method of the second redistribution layer 222 are substantially similar to those described in the redistribution layer 120 (as shown in FIG. 1B ), so the details will not be repeated here. In addition, the second redistribution layer 222 exemplarily shows two layers of dielectric layers 2224 , 2227 and one patterned circuit layer 2225 , but the present invention does not limit the number of patterned circuit layers and dielectric layers. In other embodiments, the number of patterned circuit layers and dielectric layers can be increased or decreased according to actual needs.

Next, referring to FIG. 2B , an etching process is performed on the second redistribution layer 222 to expose part of the first encapsulant 140 and form a plurality of second redistribution structures 222 a ( FIG. 2B exemplarily shows two , but not limited to). Specifically, in this step, a part of the dielectric layer 2224, 2227 in the second redistribution layer 222 (that is, a pre-defined cutting area) may be removed by a lithographic etching process to form the second gap G2, And the second redistribution layer 222 is divided into a plurality of independent second redistribution structures 222a. The second gap G2 may expose part of the first encapsulant 140 . The second gap G2 may be located on opposite sides of the second redistribution structure 222a, that is, the second gap G2 may be located between two adjacent second redistribution structures 222a. In this embodiment, there is a second interval G2 between the plurality of second redistribution structures 222a, and the second interval G2 corresponds to the first interval G1 between the plurality of first redistribution structures 221a. In other words, each second redistribution structure 222a is electrically connected to the corresponding first redistribution structure 221a, and the plurality of second redistribution structures 222a are not electrically connected to each other. Therefore, each chip 130 is only electrically connected to the corresponding second redistribution structure 222a through the corresponding first redistribution structure 221a, and there is no electrical connection between the plurality of chips 130 .

Please continue referring to FIG. 2B , an etching process is performed on the plurality of second redistribution structures 222 a to expose the patterned circuit layer 2225 . Next, referring to FIG. 2C , a plurality of conductive terminals 150 are formed on the exposed patterned circuit layer 2225 to be electrically connected to the plurality of second redistribution structures 222a. The types, uses and materials of the conductive terminals 150 have been described above, and will not be repeated here.

Next, please continue to refer to FIG. 2C , forming the second encapsulant 160 on the plurality of second redistribution structures 222a to fill the second gap G2 and cover the second surface 2221 of the plurality of second redistribution structures 222a and the plurality of second redistribution structures 222a. Each conductive terminal 150 is connected to the bottom peripheral surface 151 of the plurality of second redistribution structures 222a. Specifically, the first encapsulant 140 and the second encapsulant 160 can completely cover the surfaces of the multiple redistribution structures 220a formed by the multiple first redistribution structures 221a and the multiple second redistribution circuit structures 222a, In order to form a complete protection for any side of the redistribution structure 222, avoid cracking at the edge of the redistribution circuit structure 222 in the subsequent process, and at the same time prevent external moisture from penetrating into the redistribution structure 222, affecting the reliability of electrical signals . In addition, since the first encapsulant 140 and the second encapsulant 160 are not formed in the same step, there may be an interface between the first encapsulant 140 and the second encapsulant 160 . Here, the material and forming method of the second encapsulant 160 have been described above, and will not be repeated here.

In addition, in this embodiment, the conductive terminals 150 are first formed on the patterned circuit layer 2225 of the second redistribution structure 222a, and then the second encapsulant 160 is formed on the second surface 2221 of the second redistribution structure 222a. As a result, the second encapsulant 160 will cover the bottom peripheral surface 151 ( FIG. 1G ) of the plurality of conductive terminals 150 connected to the plurality of redistribution structures 120a, which can increase the strength of the base of the conductive terminals 160 (that is, the part connected to the redistribution structures 120a), In turn, the drop resistance of the overall structure can be improved.

Next, referring to FIG. 2C and FIG. 2D simultaneously, a singulation process is performed along the dicing line S to form a single chip package structure 20 . So far, the fabrication of the chip package structure 20 has been completed.

3A to 3D are cross-sectional flowcharts of a manufacturing method of a chip package structure according to another embodiment of the present invention. FIG. 3A to FIG. 3D are steps continuing FIG. 1F and replacing FIG. 1G to FIG. 1I . The same or similar components in the embodiment of FIG. 3A to FIG. 3D and the embodiment of FIG. 2A to FIG. 2D can be made by using the same material or method, so the description of the same and similar in the two embodiments will not be repeated below. . The difference between the embodiment shown in FIGS. 3A to 3D and the embodiment shown in FIGS. 2A to 2D is that, in the chip package structure 30 of this embodiment, the rewiring structure 320a includes a first rewiring structure 321a (that is, 2B, the rewiring structure 221a) and the second rewiring structure 322a, wherein at least two chips 130a, 130b with different (or the same) functions can be electrically connected through the second rewiring structure 322a. The manufacturing process of the chip package structure 30 will be described below.

Please refer to FIG. 1F, FIG. 2A and FIG. 3A at the same time. In this embodiment, the temporary carrier 100 and the temporary adhesive layer 110 are removed to expose a plurality of first rewiring structures 321a (that is, the first rewiring structure in FIG. 2A ). The wiring structure 221a) and the first encapsulant 140, wherein the multiple first redistribution structures 321a are independent from each other and have a first interval G1 (that is, the first interval between the multiple first redistribution structures 221a in FIG. 2A ), and each first redistribution structure 321a is electrically connected to a single chip 130a, 130b, wherein the chip 130a and the chip 130b may have different functions. Next, after turning the structure upside down, a second redistribution layer 322 (similar to the second redistribution layer 222 in FIG. a first redistribution structure 321a. Specifically, the first redistribution structure 321a has a first surface 3211 (ie, the first surface 2211 in FIG. 2A ), a third surface 3212 opposite to the first surface 3211 (ie, the third surface 2212 in FIG. The first peripheral surface 3213 of the first surface 2211 and the third surface 3212 (ie, the first peripheral surface 2213 in FIG. 2A ). The second redistribution layer 322 has a second surface 3221 (ie, the second surface 2221 of FIG. 2A ) and a fourth surface 3222 (ie, the fourth surface 2222 of FIG. 2A ) opposite to each other, and the fourth surface 3222 contacts each first The third surface 3212 of the redistribution structure 321a. That is to say, the third surface 2212 of the first redistribution structure 321a, the fourth surface 3222 of the second redistribution layer 322 and the surface of the first encapsulant 140 facing the second redistribution layer 322 are actually coplanar.

Please refer to FIG. 2A and FIG. 3A at the same time. In this embodiment, the second redistribution layer 322 may include dielectric layers 3224 and 3227 , a patterned circuit layer 3225 and a plurality of via holes 3226 . The main difference between the second redistribution layer 322 of this embodiment and the second redistribution layer 222 of FIG. The corresponding at least two first redistribution structures 321a are connected to electrically connect at least two chips 130a and 130b with different functions, but the invention is not limited thereto. In other embodiments, the chip 130a and the chip 130b may also have the same function.

Next, referring to FIG. 3B , an etching process is performed on the second redistribution layer 322 to expose the first encapsulant 140 and form a plurality of second redistribution structures 322 a. In this step, a part of the dielectric layer 3224, 3227 in the second redistribution layer 322 (that is, a pre-defined cutting area) may be removed by a lithographic etching process, thereby dividing the second redistribution layer 322 into The plurality of second redistribution structures 322a are independent from each other. That is, there is a second space between the plurality of second redistribution structures 322a and they are not electrically connected to each other.

In more detail, please refer to FIG. 2B and FIG. 3B at the same time. The main difference between the second redistribution structure 322a of this embodiment and the second redistribution structure 222a of FIG. 2B is that each second redistribution structure of this embodiment 322a is electrically connected to at least two corresponding first redistribution structures 321a. That is to say, each second redistribution structure 322a included in each first sealant 140 is connected to at least two first redistribution structures 321a, and each first redistribution structure 321a is respectively connected to at least one chip. 130. Therefore, the number of chips connected to each first redistribution structure 321a is not limited, and the functions of the chips can be the same or different, which is determined according to actual needs, and is not limited thereto.

Next, please continue referring to FIG. 3B , an etching process is performed on the plurality of second redistribution structures 322 a to expose the patterned circuit layer 3225 . Referring to FIG. 3C , a plurality of conductive terminals 150 are formed on the exposed patterned circuit layer 3225 to be electrically connected to the plurality of second redistribution structures 322a. The types, uses and materials of the conductive terminals 150 have been described above, and will not be repeated here.

Finally, please refer to FIG. 2C to FIG. 2D and FIG. 3C to FIG. 3D at the same time. Since the steps in FIG. 3C to FIG. The second surface 3221 of the redistribution structure 322a and the plurality of conductive terminals 150 are connected to the bottom peripheral surface 151 of the plurality of second redistribution structures 322a. Then, a singulation process is performed to form the chip package structure 30) is substantially the same as that shown in FIG. 2C to 2D, so the details are not repeated here.

To sum up, in the chip packaging structure of the present invention, each surface of the rewiring structure can be completely covered by the first encapsulant and the second encapsulant, so that the rewiring structure can be completely protected, and the entire As far as the package is concerned, it also forms a complete protection of six sides, so it can reduce the cracking of the edge of the rewiring structure in the subsequent process, and also prevent external moisture from penetrating into the rewiring structure or chip connection, thereby improving electrical performance. signal reliability.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10, 20, 30: Chip package structure 100:Temporary carrier board 110: Temporary adhesive layer 120:Rewiring layer 120a, 220a, 320a: rewiring structure 121, 2211, 3211: first surface 122, 2221, 3221: second surface 123: surrounding surface 124, 126, 2225, 3225: patterned circuit layer 125, 128, 2224, 2227, 3224, 3227: dielectric layer 127, 2226, 3226: via hole 130, 130a, 130b: wafer 131: active surface 132: back surface 134: Conductive connector 140: The first packaging colloid 141: surface 150: conductive terminal 151: surface around the bottom 160: Second encapsulation colloid 222, 322: the second rewiring layer 221a, 321a: the first rewiring structure 2212, 3212: third surface 2213, 3213: first surrounding surface 222a, 322a: the second rewiring structure 2222, 3222: the fourth surface 2223, 3223: second surrounding surface S: cutting line OP1: opening G: Interval G1: first interval G2: second interval

1A to 1I are cross-sectional views of the process of a manufacturing method of a chip package structure according to an embodiment of the present invention. 2A to 2D are cross-sectional flowcharts of a manufacturing method of a chip package structure according to another embodiment of the present invention. 3A to 3D are cross-sectional flowcharts of a manufacturing method of a chip package structure according to another embodiment of the present invention.

10: Chip package structure

120a: Rewiring structure

121: first surface

122: second surface

123: surrounding surface

130: chip

134: Conductive connector

140: The first packaging colloid

141: surface

150: conductive terminal

160: Second encapsulation colloid

Claims (10)

A chip packaging structure, comprising: a rewiring structure having a first surface, a second surface opposite to the first surface, and a surrounding surface connecting the first surface and the second surface; a chip disposed on the first surface of the rewiring structure and electrically connected to the rewiring structure; a first encapsulant covering the rewiring structure and the chip, wherein the first encapsulant covers the surrounding surface of the rewiring structure; a plurality of conductive terminals disposed on the second surface of the redistribution structure and electrically connected to the redistribution structure; and The second encapsulant is disposed on the rewiring structure, and covers the second surface of the rewiring structure and the bottom peripheral surface where the plurality of conductive terminals are connected to the rewiring structure. The chip package structure as claimed in item 1, wherein the rewiring structure comprises: a first redistribution structure having the first surface, a third surface opposite to the first surface, and a first peripheral surface connecting the first surface and the third surface; and The second rewiring structure is disposed on the first rewiring structure and is electrically connected to the first rewiring structure, the second rewiring structure has the second surface, opposite to the second a fourth surface of the surface and a second peripheral surface connecting said second surface and said fourth surface; Wherein the third surface is in contact with the fourth surface and is coplanar, the first encapsulant covers the first peripheral surface, and the second encapsulant covers the second peripheral surface. The chip packaging structure according to claim 2, wherein the chip includes at least two chips, and the first rewiring structure includes at least two first rewiring structures, wherein the at least two chips are electrically connected to the corresponding At least two first redistribution structures are electrically connected to each other through the second redistribution structure. The chip packaging structure as claimed in claim 3, wherein the at least two chips include at least two chips with different functions. The chip packaging structure according to claim 3, wherein a first gap is provided between the at least two first redistribution structures, and the first encapsulant is disposed in the first gap. A method for manufacturing a chip package structure, comprising: forming a plurality of rewiring structures having a first surface, a second surface opposite to the first surface, and a surrounding surface connecting the first surface and the second surface; disposing a plurality of chips on the first surface of the corresponding plurality of redistribution structures to be electrically connected to the plurality of redistribution structures; forming a first encapsulant to cover the plurality of redistribution structures and the plurality of chips, wherein the first encapsulant covers the surrounding surfaces of the plurality of redistribution structures; forming a plurality of conductive terminals on the second surface of the plurality of redistribution structures to be electrically connected to the plurality of redistribution structures; forming a second encapsulant on the plurality of rewiring structures to cover the second surface of the plurality of rewiring structures and the bottom peripheral surface of the plurality of conductive terminals connected to the plurality of rewiring structures; as well as A singulation process is performed to form the chip packaging structure. The manufacturing method according to claim 6, wherein the plurality of rewiring structures include a plurality of first rewiring structures, and the step of forming the plurality of first rewiring structures includes: Provide temporary carrier board; forming a temporary adhesive layer on the temporary carrier; forming a first redistribution layer on the temporary adhesive layer; and An etching process is performed on the first rewiring layer to expose the temporary adhesive layer and form the plurality of first rewiring structures. The manufacturing method according to claim 7, wherein there is a first space between the plurality of first redistribution structures, and the first encapsulant is disposed in the first space. The manufacturing method according to claim 7, wherein the rewiring structure further includes a plurality of second rewiring structures, and the forming step of the plurality of second rewiring structures includes: After forming the first encapsulant and before forming the second encapsulant, the temporary carrier and the temporary adhesive layer are removed to expose the plurality of first redistribution structures and the first redistribution structure. a packaging colloid; forming a second redistribution layer on the plurality of first redistribution structures and the first encapsulant to be electrically connected to the plurality of first redistribution structures; An etching process is performed on the second redistribution layer to expose the first encapsulant and form the plurality of second redistribution structures. The manufacturing method according to claim 9, wherein there is a second space between the plurality of second redistribution structures, and the second encapsulant is disposed in the second space.

Images