CN113571496A - Multi-chip package and manufacturing method thereof - Google Patents
Multi-chip package and manufacturing method thereof Download PDFInfo
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- CN113571496A CN113571496A CN202110417910.XA CN202110417910A CN113571496A CN 113571496 A CN113571496 A CN 113571496A CN 202110417910 A CN202110417910 A CN 202110417910A CN 113571496 A CN113571496 A CN 113571496A
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
Abstract
The invention discloses a multi-chip package and a manufacturing method thereof. The multi-chip package includes: an interposer comprising a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via passing through the dielectric body, and a routing structure in each of the plurality of semiconductor bodies; a plurality of semiconductor chips located side by side on the first surface of the interposer and electrically connected to the wiring structure; an encapsulant on the first surface of the interposer and encapsulating at least portions of the plurality of semiconductor chips; and a redistribution structure on a second surface of the interposer opposite the first surface of the interposer, the redistribution structure electrically connected to the plurality of semiconductor chips through the through vias.
Description
Technical Field
The present invention relates to semiconductor packages and methods of manufacturing the same, and more particularly, to a multi-chip package and a method of manufacturing the same.
Background
In order to make a semiconductor Package have both light, thin and high performance, the current packaging technology has attempted to integrate a plurality of semiconductor chips into a single semiconductor Package to form a multi-chip Package or stack a plurality of semiconductor packages by a 3-dimensional stacking technology to form a Package on Package (PoP) or a System in Package (System in Package). However, the signal communication speed between the semiconductor chips in the conventional multi-chip package is limited, and thus the overall performance of the semiconductor package still needs to be further improved.
Disclosure of Invention
The invention aims to provide a multi-chip package with good performance.
The invention provides a multi-chip package, which comprises an interposer, a plurality of semiconductor chips, an encapsulation body and a reconfiguration circuit structure. The interposer includes a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via passing through the dielectric body, and a routing structure in each of the plurality of semiconductor bodies. The plurality of semiconductor chips are located side by side on the first surface of the interposer and electrically connected to the routing structure. The encapsulant is on the first surface of the interposer and encapsulates at least a portion of the plurality of semiconductor chips. The redistribution line structure is on a second surface of the interposer and electrically connected to the plurality of semiconductor dies through the through vias, the second surface of the interposer being opposite the first surface of the interposer.
The invention provides a multi-chip package, which comprises an intermediate layer, a plurality of semiconductor chips and a reconfiguration circuit structure. The interposer includes a dielectric body, a semiconductor body, a through via through the dielectric body, and a routing structure in the semiconductor body, the through via and the routing structure being spaced apart from one another. The plurality of semiconductor chips are located side by side on the first surface of the interposer and each of the plurality of semiconductor chips is electrically connected to both the routing structure and the through via. The redistribution routing structure is on a second surface of the interposer and electrically connected to the through vias, the second surface of the interposer being opposite the first surface of the interposer.
The invention provides a method for manufacturing a multi-chip package, which comprises the following steps. A plurality of semiconductor chips are provided on a first surface of a semiconductor substrate such that each of the plurality of semiconductor chips is electrically connected to a wiring structure in the semiconductor substrate. An encapsulant is formed on the first surface of the semiconductor substrate to encapsulate the plurality of semiconductor chips. Removing at least a portion of the semiconductor substrate from a second surface of the semiconductor substrate opposite the first surface to space remaining portions of the semiconductor substrate from each other. A dielectric body is formed in the space created after the semiconductor substrate is removed. Through vias are formed in the dielectric body that extend through the dielectric body and connect to the plurality of semiconductor chips. Forming a redistribution line structure on the remaining portion of the semiconductor substrate and the dielectric body, the redistribution line structure being electrically connected to the through vias.
Based on the above, the multi-chip package of the invention can improve the overall efficiency of the multi-chip package.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic cross-sectional view of a multi-chip package according to an embodiment of the invention;
FIG. 2 is a schematic plan view along section line I-I' of the multi-chip package of FIG. 1;
FIGS. 3A-3H are schematic cross-sectional views of steps in a manufacturing process for manufacturing a multi-chip package according to an embodiment of the invention;
FIGS. 4A and 4B are schematic cross-sectional views illustrating a method of bonding chips according to an embodiment of the invention;
fig. 5A and 5B are schematic cross-sectional views illustrating a method of bonding chips according to another embodiment of the invention.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
The following examples are described in detail with reference to the accompanying drawings, but the examples are not provided to limit the scope of the present invention. Moreover, the figures are for illustrative purposes only and are not drawn to scale, and various layers or regions may be shown exaggerated or reduced in size in a single figure. Also, although the terms first, second, etc. may be used herein to describe various elements, regions and/or components, these elements, regions and/or components should not be limited by these terms. Rather, these terms are only used to distinguish one element, region or component from another element, region or component. Thus, a first component, region or member discussed below could be termed a second component, region or member without departing from the teachings of the embodiments. The same or similar reference numbers refer to the same or similar components, and the following paragraphs will not be repeated.
Spatially relative terms such as "upper" and "lower" are defined herein with reference to the drawings. Thus, it should be understood that the term "upper surface" may be used interchangeably with the term "lower surface" and that when a component such as a layer or film is described as being disposed on another component, the component may be placed directly on the other component or there may be intervening components between the two components. On the other hand, when a component is described as being directly configured on another component, there are no intervening components between the two components. Similarly, when an element is described as being coupled or engaged with another element, it can be directly coupled or engaged with the other element or intervening elements may be present between the two elements. On the other hand, when an element is described as being directly connected or directly engaged with another element, there are no intervening elements between the two elements.
Fig. 1 shows a cross-sectional schematic view of a multi-chip package according to an embodiment of the invention. Fig. 2 is a plan view schematic along section line I-I' of the multi-chip package of fig. 1.
Referring to fig. 1, a multi-chip package 100 according to an embodiment of the invention includes an interposer 150, a semiconductor chip 120 on a first surface 150A of the interposer 150, and a redistribution routing structure 110 on a second surface 150B of the interposer 150 opposite the first surface 150A. Referring to fig. 2, the body of the interposer 150 may be composed of a dielectric body 150R and a plurality of semiconductor bodies 150S separated by the dielectric body 150R. The dielectric body 150R has a through via 153 formed therein that passes through the dielectric body 150R. A wiring structure 150W is formed in the semiconductor body 150S. The wiring structure 150W may be used to transmit signals, particularly high bandwidth signals, between the side-by-side semiconductor chips 120. The through via 153 may serve as a ground path or a power path between the semiconductor chip 120 and the redistribution wiring structure 110 for transmitting a large current.
In a conventional System in Package (System in Package), signals between semiconductor chips arranged side by side are transmitted using a redistribution circuit structure. However, as the application of high performance computing increases, the transmission requirement for high bandwidth signals is also increasing. The redistribution circuit structure is limited by the line width and line spacing and the exposure and development capability of the organic dielectric layer, and the number of layers for interconnection is not large, so that a connection structure with higher line density is still required to meet the Bandwidth requirement of, for example, a High Bandwidth Memory (HBM). The multi-chip package of the present invention achieves faster signal transmission by transmitting signals between the semiconductor chips 120 using the wiring structure 150W having a higher line density (i.e., a smaller line width and a larger number of layers) compared to the reconfigured wiring structure.
For example, the number of layers of the rcf is typically 3, the line width of the rcf is typically about 2 microns, the pitch of the lines is typically about 2 microns, and the size of the vias (via) is typically about 2 microns, while the number of layers of the routing structure 150W in a multi-chip package according to the present invention may be more than 4, the line width of the routing structure may be in the range of about 0.01 microns to 1 micron (e.g., about 0.2 microns, about 0.4 microns, about 0.6 microns, or about 0.8 microns), the pitch of the routing structure may be in the range of about 0.01 microns to 1 micron (e.g., about 0.2 microns, about 0.4 microns, about 0.6 microns, or about 0.8 microns), and the via (via) of the routing structure may be in the range of about 0.01 microns to 1 micron (e.g., about 0.2 microns, about 0.4 microns, about 0.6 microns, or about 0.8 microns). Since the multi-chip package of the present invention uses the wiring structure 150W having a line width of 1 μm or less to connect the semiconductor chips 120, high-bandwidth signal transmission can be performed between different semiconductor chips 120.
In addition, the interposer 150 in the multi-chip package according to the present invention is composed of the dielectric body 150R and the semiconductor body 150S, and the through via 153 is formed in the dielectric body 150R, so that the interposer 150 in the multi-chip package according to the present invention can save through silicon vias to reduce the cost and improve the yield.
In particular, the body of the interposer 150 may be comprised of a dielectric body 150R and a plurality of semiconductor bodies 150S separated by the dielectric body 150R. The plurality of semiconductor bodies 150S may be physically separated from each other. The material of the semiconductor body 150S may be, for example, a semiconductor material such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. The material of the dielectric body 150R may include polyimide, epoxy, acrylic, phenolic, Bismaleimide-triazine resin (BT resin) or any other suitable polymer-based dielectric material, as well as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer or other suitable silicon dielectric material. In some embodiments, the material of the dielectric body 150R may include an optically sensitive insulating resin. The interface between the dielectric body 150R and the semiconductor body 150S may not be perpendicular to the surface of the interposer 150. For example, the angle α between the sidewall of the semiconductor body 150S and the second surface 150B may be greater than 90 °. In other words, the width of the semiconductor body 150S decreases with increasing distance from the semiconductor chip 120, and the width of the dielectric body 150R increases with increasing distance from the semiconductor chip 120. However, the interface between the dielectric body 150R and the semiconductor body 150S may be perpendicular to the surface of the interposer 150, for example. As used herein, "width" refers to the length of the described components in the horizontal direction in a longitudinal cross-sectional view of a multi-chip package according to the present invention (as in fig. 1).
A wiring structure 150W is formed in the semiconductor body 150S. The wiring structure 150W may be used to transmit signals, particularly high bandwidth signals, between the semiconductor chips 120. The material of the wiring structure 150W may include a conductive material such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), or an alloy thereof, or a metal or an alloy thereof excellent in other electrical characteristics. As described above, the wiring structure 150W has a high line density. In some embodiments, the number of layers of the wiring structure 150W may be, for example, a plurality of layers of 4 or more layers, and the line width size thereof may be in a range of about 0.01 to 1 micron (e.g., about 0.2, about 0.4, about 0.6, or about 0.8 micron), the line pitch size thereof may be in a range of about 0.01 to 1 micron (e.g., about 0.2, about 0.4, about 0.6, or about 0.8 micron), and the via (via) size thereof may be in a range of about 0.01 to 1 micron (e.g., about 0.2, about 0.4, about 0.6, or about 0.8 micron).
The dielectric body 150R has a through via 153 formed therein that extends through the first surface 150A and the second surface 150B. The material of the through via 153 may include a conductive material such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), or an alloy thereof. The through vias 153 may be used to connect the semiconductor chip 120 and the redistribution line structure 110 to each other. The upper width of the through passage 153 may be smaller than the lower width. That is, the width of the through via 153 increases as the distance from the semiconductor chip 120 increases. Since the through via 153 is formed in the dielectric body 150R, the multi-chip package 100 of the present invention can save the process of forming the through-silicon via, thereby reducing the cost and improving the yield.
An interposer connection conductor 150P is formed on the first surface 150A of the interposer 150. The interposer connection conductor 150P is connected to the wiring structure 150W and the through via 153 of the interposer 150. The interposer connection conductors 150P may be used to connect the interposer 150 to other devices. The material of the interposer connection conductor 150P may include a conductive material such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), or an alloy thereof, or a metal or an alloy thereof having excellent electrical characteristics. The shapes of the interposer connection conductors 150P may include various shapes such as pillar-shaped or Stud-shaped bumps (bumps). The intermediate layer connecting conductors 150P may have different sizes. For example, the interposer connection conductors 150P may include a first interposer connection conductor 150P1 having a larger size and a second interposer connection conductor 150P2 having a smaller size. That is, the width DA of the first interposer connection conductor 150P1 is greater than the width DB of the second interposer connection conductor 150P 2. The larger first interposer connection conductor 150P1 may be connected to the through via 153 of the interposer 150, and the smaller second interposer connection conductor 150P2 may be connected to the wiring structure 150W. In other embodiments, the interposer connection conductors 150P may have the same size.
The semiconductor chip 120 may be any suitable Integrated Circuit (IC) chip, such as a memory chip, a logic chip, a digital chip, an analog chip, a sensor chip (sensor chip), an artificial intelligence chip (AI chip), a radio frequency (wireless and radio frequency) chip, or a voltage regulator chip. The sensor chip may be an image sensor chip, and at least includes a Charge Coupled Device (CCD) or a Complementary Metal Oxide Semiconductor (CMOS) image sensor. Although two semiconductor chips 120 are included in the multi-chip package 100 of fig. 1, the present invention is not limited thereto. For example, the multi-chip package of the present invention may include three or more semiconductor chips.
The semiconductor chip 120 has a chip connection conductor 120P on the active surface. The material of the chip connection conductor 120P may include a conductive material such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), or an alloy thereof, or a metal or an alloy thereof having excellent electrical characteristics. The shape of the chip connection conductor 120P may include various shapes such as a pillar-shaped or Stud-shaped bump (bump). The chip connection conductors 120P may have different sizes. For example, chip connection conductor 120P may include a larger sized first chip connection conductor 120P1 and a smaller sized second chip connection conductor 120P 2. That is, width D1 of first chip connection conductor 120P1 is greater than width D2 of second chip connection conductor 120P 2. The chip connection conductor 120P and at least a part of the interposer connection conductor 150P are bonded to each other. In some embodiments, the die connection conductors 120P and the interposer connection conductors 150P, which are correspondingly joined to each other, may have corresponding sizes. For example, a larger first chip connection conductor 120P1 may be bonded to a larger first interposer connection conductor 150P1, and a smaller second chip connection conductor 120P2 may be bonded to a smaller second interposer connection conductor 150P 2. In this case, the larger first chip connection conductor 120P1 and the first interposer connection conductor 150P2 may be used to transmit large currents (e.g., ground), while the smaller second chip connection conductor 120P2 and the second interposer connection conductor 150P2 may be used to transmit high bandwidth signals. The bonding surfaces of the die attach conductors 120P and the interposer attach conductors 150P may be solder-free bonding surfaces. Since the interposer 150 and the semiconductor chip 120 are connected to each other via the chip connection conductor 120P and the interposer connection conductor 150P instead of the redistribution structure, the transmission path of the power and/or signals between the interposer 150 and the semiconductor chip 120 can be shortened, and the transmission speed and quality of the power and/or signals can be improved. In some embodiments, die attach conductors 120P and interposer attach conductors 150P may be bonded using solder of a solder alloy, such as Cu/Sn, Cu/Ni/SnBi, or the like. In some embodiments, bumps (as shown in fig. 4B) may be further included between the chip connection conductors 120P and the interposer connection conductors 150P.
In addition, a plurality of semiconductor chips 120 arranged side by side may be connected to each other via the wiring structure 150W in the interposer 150. As described above, the wiring structure 150W has a line width of 1 μm or less, and the wiring structure 150W can perform transmission of high-bandwidth signals between the semiconductor chips 120. In addition, depending on the signal or current to be transmitted, a high bandwidth signal requiring a faster transmission speed may be transmitted through the second chip connection conductor 120P2, the second interposer connection conductor 150P2 and the wiring structure 150W, and other signals or ground may be transmitted through the first chip connection conductor 120P1, the first interposer connection conductor 150P1, the through via 153 and the redistribution wiring structure 110. That is, in the multi-chip package 100 of the present invention, signal transmission between the semiconductor chips 120 is transmitted through different paths depending on the nature of the signal.
The multi-chip package 100 according to the present invention may include an Underfill (Underfill)170 between the semiconductor chip 120 and the interposer 150. The underfill 170 may fill the space between the semiconductor die 120 and the interposer 150 and encapsulate the interposer connection conductors 150P and the die connection conductors 120P. The primer 170 has inclined sidewalls, and an upper width of the primer 170 may be smaller than a lower width of the primer 170. In some embodiments, the width of the underfill 170 is tapered, and the width of the underfill 170 tapers from one end closer to the interposer 150 to the other end closer to the semiconductor chip 120. The material of the primer 170 is not particularly limited, and may be, for example, an insulating material such as epoxy resin. In other embodiments, the multi-chip package 100 according to the present invention may also have a protective layer 175 between the semiconductor chip 120 and the interposer 150 instead of the underfill 170 (see fig. 5B).
The multi-chip package 100 according to the present invention may include an encapsulant 180 on the interposer 150 to encapsulate the semiconductor chip 120 and the interposer 150. The material of the encapsulant 180 may include a molding compound, a molding underfill, a resin or Epoxy Molding Compound (EMC), and the like. The encapsulant 180 may be doped with an inorganic filler, if necessary. The sidewalls of the encapsulation 180, the interposer 150, and the redistribution structure 110 may be aligned with one another.
The redistribution line structure 110 is located on the second surface 150B of the interposer 150 and may be used to reroute the input and output terminals of the semiconductor chip 120. For example, the redistribution structure 110 may be used for the input/output terminals of the fan-out (fan-out) semiconductor chip 120 to connect the semiconductor chip 120 with a Printed Circuit Board (PCB) (not shown). The rcf 110 includes a plurality of rcc dielectric layers 114 and a plurality of rcc wiring layers 116 embedded in rcc dielectric layers 114 and connected to through vias 153. The material of reconfiguration dielectric layer 114 may include polyimide, epoxy, acrylic, phenolic, Bismaleimide-triazine resin (BT resin) or any other suitable polymer-based dielectric material, as well as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or other suitable silicon dielectric material. In some embodiments, the material of the reconfiguration dielectric layer 114 may include a photosensitive insulating resin. The material of the reconfiguration wiring layer 116 may include a conductive material such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), or an alloy thereof.
The rcf structure 110 may further include rcf vias 118, where the rcf vias 118 may be used to connect rcf wiring layers 116 located at different levels. The material of the reconfiguration vias 118 may include a conductive material such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), or alloys thereof. The upper width W1 of the reconfiguration channel 118 may be less than the lower width W2 of the reconfiguration channel 118. That is, the angle β between the sloped sidewalls of the reconfiguration via 118 and the lower surface of the reconfiguration dielectric layer 114 may be greater than 90 °.
Although the redistribution structure 110 in fig. 1 is illustrated as including three redistribution dielectric layers 114 and three redistribution wiring layers 116, the invention is not limited thereto. A multi-chip package 100 in accordance with the present invention may include more or fewer layers of reconfiguration dielectric layers 114 and reconfiguration wiring layers 116 than are shown in the figures.
The multi-chip package 100 according to the present invention may further include conductive terminals 190. Conductive terminals 190 are partially embedded in the lowermost redistribution dielectric layer 114 to connect to the lowermost redistribution routing layer 116. Conductive terminals 190 may be used to connect multi-chip package 100 to an external device, such as a printed circuit board. The conductive terminals 190 may be solder balls, for example, but the invention is not limited thereto.
In the multi-chip package 100 according to the present invention, the plurality of semiconductor chips 120 arranged side by side may be connected to each other by the wiring structure 150W having high density and high layer count to achieve efficient signal transfer. In addition, the multi-chip package 100 according to the present invention also provides other electrical paths for transmitting high current to improve the reliability of the multi-chip package 100 of the present invention. Meanwhile, the multi-chip package 100 according to the present invention may implement a fan-out type package by re-routing the semiconductor chip 120 through the re-routing structure 110.
Fig. 3A-3H are cross-sectional views of steps of a manufacturing process for manufacturing a multi-chip package according to an embodiment of the invention. Fig. 4A and 4B are schematic cross-sectional views illustrating a method of bonding chips according to an embodiment of the invention. Fig. 5A and 5B are schematic cross-sectional views illustrating a method of bonding chips according to another embodiment of the invention.
Referring to fig. 3A, a semiconductor substrate 15 having a wiring structure 150W is provided. The semiconductor substrate 15 may be a silicon substrate, for example. Although only the process of forming one multi-chip package using the semiconductor substrate 15 is illustrated in the drawings, in some embodiments, a semiconductor substrate 15 having a large size may be used to simultaneously form a plurality of multi-chip packages. For example, a silicon wafer or a panel-level silicon substrate may be used as the semiconductor substrate 15. The semiconductor substrate 15 has an interposer connecting conductor 150P on the first surface 150A, and the interposer connecting conductor 150P is electrically connected to the wiring structure 150W. The interposer connection conductor 150P includes a first interposer connection conductor 150P1 and a second interposer connection conductor 150P2 having different sizes. That is, the width DA of the first interposer connection conductor 150P1 may be greater than the width DB of the second interposer connection conductor 150P 2.
Referring to fig. 3B, a plurality of semiconductor chips 120 are provided on the semiconductor substrate 15 such that the chip connection conductors 120P and the interposer connection conductors 150P are bonded to each other. Chip connection conductor 120P includes first chip connection conductor 120P1 and second chip connection conductor 120P2 having different sizes. That is, width D1 of first chip connection conductor 120P1 may be greater than width D2 of second chip connection conductor 120P 2. In some embodiments, the larger first chip connection conductor 120P1 and the first interposer connection conductor 150P1 are bonded to each other, and the smaller second chip connection conductor 120P2 and the second interposer connection conductor 150P2 are bonded to each other. The bonding method of the chip connection conductors 120P and the interposer connection conductors 150P may be, for example, direct bonding by heat and/or pressure. After the die attach conductors 120P and the interposer attach conductors 150P are bonded, an underfill 170 may be applied over the semiconductor substrate 15 to encapsulate the die attach conductors 120P and the interposer attach conductors 150P.
In some embodiments, the die connection conductors 120P and the interposer connection conductors 150P may be bonded to each other by bumps. Referring to fig. 4A, first bumps 155 may be formed on interposer connection conductors 150P and second bumps 165 may be formed on chip connection conductors 120P. The first bump 155 is then bonded to the second bump 165 using heat and/or pressure. The material of the first bump 155 and the second bump 165 may be, for example, a solder alloy (e.g., Cu/Sn, Cu/Ni/SnBi), copper, gold, silver, indium, palladium, titanium, manganese, cobalt, or a bonding metal alloy thereof (e.g., Ni/Au, Cu/Ni/In). The materials of the first bump 155 and the second bump 165 may be different from each other. For example, the material of the first bump 155 may be pure copper, Ni/Au alloy, Cu/Ni/In alloy, or the like that is surface-treated, and the material of the second bump 165 may be Cu/Sn, Cu/Ni/SnBi alloy, or the like. In some embodiments, the material of the first bump 155 and the second bump 165 is free of solder components. In some embodiments, the material of the first bump 155 and the second bump 165 may be a low temperature bonding metal having a melting point below 200 ℃. For example, the low temperature bonding metal may include twinned copper, twinned silver or other nano-twinned materials, indium tin alloys, tin bismuth alloys, porous gold, or combinations thereof. Compared with the reflow temperature required by the traditional solder ball or solder which is more than or equal to 250 ℃, the low-temperature bonding metal can enable the connection structure to achieve stable bonding at a relatively low heating temperature (for example, at a temperature lower than 200 ℃ or lower than 150 ℃) and meet the reliability requirement of the electrical connection requirement. In some embodiments, only one of the first and second bumps 155 and 165 may be formed. For example, the first bump 155 may be formed only on the interposer connection conductor 150P and the first bump 155 may be bonded with the chip connection conductor 120P.
Referring next to fig. 4B, after the first bumps 155 and the second bumps 165 are bonded, an underfill 170 may be applied on the semiconductor substrate 15 to encapsulate the chip connection conductors 120P, the interposer connection conductors 150P, the first bumps 155, and the second bumps 165. The underfill 170 may fill the space between the semiconductor chip 120 and the semiconductor substrate 15 and encapsulate the interposer connection conductor 150P, the chip connection conductor 120P, the first bump 155, and the second bump 165.
Referring to fig. 5A and 5B, in some embodiments, a protective layer 175 may be formed on the semiconductor chip 120. The material of the protection layer 175 may be an organic material such as resin, non-conductive adhesive film, dielectric material, etc. The surface of the chip connection conductor 120P and the surface of the protective layer 175 between the semiconductor chips 120 may be coplanar. When the die connection conductors 120P and the interposer connection conductors 150P are bonded to each other, the die connection conductors 120P are encapsulated by the passivation layer 175 and only the surface thereof is exposed for connection, so that damage caused by external force impact can be prevented, and thus, yield can be improved.
Referring back to fig. 3C, an encapsulant 180 is formed on the semiconductor substrate 15. The method of forming the encapsulant 180 includes the following steps. An encapsulating material layer covering the semiconductor substrate 15 and the semiconductor chip 120 is formed on the semiconductor substrate 15 by a suitable process (e.g., a molding process or a deposition process), and thereafter, a surface grinding process (grinding) or a surface planarization process (surface planarization) is performed to expose the upper surface of the semiconductor chip 120.
Referring to fig. 3C and 3D together, the structure of fig. 3C is turned upside down, and a thinning process such as a grinding process or an etching process is performed on the back surface of the semiconductor substrate 15 to reduce the thickness of the semiconductor substrate 15. The purpose of reducing the thickness of the semiconductor substrate 15 is to miniaturize and thin the final multi-chip package. In addition, the reduced thickness of the semiconductor substrate 15 also facilitates the subsequent formation of the dielectric body 150R. This step may be omitted, if desired.
Referring to fig. 3E, a portion of the semiconductor substrate 15 is removed, for example, by an etching process, to form a plurality of semiconductor bodies 150S physically separated from each other and to expose portions of the interposer connection conductors 150P, the underfill 170, and/or the encapsulant 180. The at least one semiconductor body 150S simultaneously overlaps at least portions of the at least 2 semiconductor chips 120 in a direction perpendicular to the first surface 150A to simultaneously connect to the at least 2 semiconductor chips 120. The other semiconductor body 150S may not overlap the semiconductor chip 120 in a direction perpendicular to the first surface 150A. In some embodiments, the other semiconductor bodies 150S may partially overlap the semiconductor chip 120 in a direction perpendicular to the first surface 150A, but each of the semiconductor bodies 150S is physically spaced apart from each other.
Referring to fig. 3F, a dielectric body 150R may be formed between the semiconductor bodies 150S on the encapsulant 180 using any suitable means, such as spin coating. The dielectric body 150R may be formed beyond the second surface 150B of the semiconductor body 150S, and then a planarization process may be used to remove a portion of the dielectric body 150R such that the surface of the dielectric body 150R is substantially coplanar with the surface of the semiconductor body 150S to complete the fabrication of the body of the interposer 150. Next, through vias 153 may be formed in the dielectric body 150R and redistribution routing layer 116 may be formed on the second surface 150B of the interposer 150. First, through via holes are formed in the dielectric body 150R through the second surface 150B and the first surface 150A of the interposer to expose the interposer connection conductors 150P, wherein the method of forming the via holes in the dielectric body 150R may employ different processes depending on the material of the dielectric body 150R. When the dielectric body 150R is a photosensitive insulating layer comprising a photosensitive insulating resin, the dielectric body 150R can be patterned by a photolithography process to form a through via hole. When the dielectric body 150R is a non-photosensitive insulating layer, a through via hole can be formed in the dielectric body 150R by a photolithography/etching process, a laser drilling process, or a mechanical drilling process. The redistribution wiring layer 116 and the through via 153 may be integrally formed. For example, the process of forming the redistribution layer 116 and the through via 153 includes the following steps. A seed layer, which may be a conductive material such as ti/cu, is first sputtered or deposited on the second surface 150B of the interposer 150 and the surface of the through via hole. Then, a patterned photoresist layer is formed on the seed layer to expose the seed layer. A conductive material, which may include copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), or an alloy thereof, is formed on the seed layer exposed by the patterned photoresist layer through an electroplating process. Then, the photoresist layer and the portion of the seed layer not covered by the conductive material are removed to form the redistribution layer 116 and the through via 153.
Referring to FIG. 3G, the redistribution dielectric layer 114 may be formed on the redistribution layer 116 and on the through vias 153 in a similar manner as the formation of the dielectric body 150R, thereby forming the redistribution circuit structure 110.
The rcf structure 110 may include multiple or single layers of rcf routing layers 116. When the rcf structure 110 includes multiple reconfiguration wiring layers 116, the process of forming the upper reconfiguration wiring layer 116 includes the following steps. First, a via hole is formed in the reconfiguration dielectric layer 114 to expose the reconfiguration wiring layer 116 thereunder, wherein the method of forming the via hole in the reconfiguration dielectric layer 114 may employ different processes depending on the material of the reconfiguration dielectric layer 114. When the redistribution dielectric layer 114 is a photosensitive insulating layer comprising a photosensitive insulating resin, the redistribution dielectric layer 114 may be patterned by a photolithography process to form via holes. When the reconfiguration dielectric layer 114 is a non-photosensitive insulating layer, the reconfiguration dielectric layer 114 may be patterned by a photolithography/etching process, a laser drilling process, or a mechanical drilling process to form via holes. Then, an upper redistribution layer 116 and a redistribution via 118 filling the via hole are formed to connect to the redistribution layer 116 exposed through the via hole in the same manner as the above-described method for forming the redistribution layer 116. Although the redistribution structure 110 is illustrated as including three redistribution dielectric layers 114 and three redistribution wiring layers 116 in the drawings, the present invention is not limited thereto, and the redistribution structure 110 may include more or less redistribution dielectric layers 114 and redistribution wiring layers 116 than those shown in the drawings.
Referring to fig. 3H, a plurality of conductive terminals 190 may be formed on the redistribution trace structure 110 to complete the multi-chip package 100 of the present invention as shown in fig. 1. A plurality of multi-chip packages 100 of the present invention may be simultaneously formed using a large-sized semiconductor substrate 15, and then the individual multi-chip packages 100 may be separated by a process such as dicing. The sidewalls of the interposer 150 and the encapsulant 180 in the multi-chip package 100 of the present invention may be aligned with the sidewalls of the redistribution routing structures 110.
In summary, the present invention provides a multi-chip package and a method for manufacturing the same. The multi-chip package can shorten the transmission path of power supply and/or signal in the multi-chip package to improve the overall efficiency of the multi-chip package, and meanwhile, the multi-chip package also has a heavy wiring structure and has the design freedom of fan-out type package.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (21)
1. A multi-chip package, comprising:
an interposer comprising a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via passing through the dielectric body, and a routing structure in each of the plurality of semiconductor bodies;
a plurality of semiconductor chips located side by side on the first surface of the interposer and electrically connected to the wiring structure;
an encapsulant on the first surface of the interposer and encapsulating at least portions of the plurality of semiconductor chips; and
a redistribution structure on a second surface of the interposer opposite the first surface of the interposer, the redistribution structure electrically connected to the plurality of semiconductor chips through the through vias.
2. The multi-chip package of claim 1, wherein the wire width of the routing structure is less than 1 micron.
3. The multichip package according to claim 1, wherein interposer connection conductors are arranged on the first surface of the interposer, chip connection conductors are arranged on a surface of each of the plurality of semiconductor chips immediately adjacent to the interposer, the interposer connection conductors and the chip connection conductors being bonded to each other.
4. The multi-chip package of claim 3, wherein a joint between the interposer connection conductors and the chip connection conductors is a solderless joint.
5. The multi-chip package of claim 3, wherein the interposer connection conductors and the chip connection conductors are bonded by solder.
6. The multi-chip package of claim 3, wherein the interposer connection conductors and the chip connection conductors are bonded by a bonding metal having a melting point below 200 ℃.
7. The multi-chip package of claim 3, further comprising first bumps between the interposer connection conductors and the chip connection conductors.
8. The multi-chip package of claim 7, further comprising a second bump between the first bump and the chip connection conductor.
9. The multi-chip package of claim 3, further comprising:
a protective layer disposed between the interposer and the plurality of semiconductor chips and encapsulating the interposer connection conductors and the chip connection conductors.
10. The multichip package according to claim 3, wherein the interposer connection conductors comprise first interposer connection conductors and second interposer connection conductors, the first interposer connection conductors having a width greater than a width of the second interposer connection conductors.
11. The multi-chip package of claim 10, wherein the chip attach conductors include a first chip attach conductor and a second chip attach conductor, the first chip attach conductor having a width greater than a width of the second chip attach conductor.
12. The multi-chip package of claim 11, wherein the first interposer connection conductor and the first chip connection conductor are bonded to each other, and the second interposer connection conductor and the second chip connection conductor are bonded to each other.
13. The multi-chip package of claim 10, wherein the through vias connect to the first interposer connection conductors and the routing structures connect to the second interposer connection conductors.
14. The multi-chip package of claim 1, wherein a width of the dielectric body increases with distance from the plurality of semiconductor chips.
15. The multi-chip package of claim 1, wherein the reconfiguration line structure includes a reconfiguration dielectric layer and a reconfiguration wiring layer, and a line width of the reconfiguration wiring layer is greater than a line width of the wiring structure.
16. The multichip package according to claim 1, wherein side walls of the encapsulation, the interposer, and the redistribution routing structure are aligned with one another.
17. The multi-chip package of claim 1, further comprising:
an underfill disposed between the interposer and the plurality of semiconductor chips, wherein a width of the underfill increases with increasing distance from the plurality of semiconductor chips.
18. The multi-chip package of claim 1, wherein at least one of the plurality of semiconductor bodies overlaps at least two of the plurality of semiconductor chips in a direction perpendicular to the first surface.
19. A multi-chip package, comprising:
an interposer comprising a dielectric body, a semiconductor body, a through via through the dielectric body, and a routing structure in the semiconductor body, the through via and the routing structure being spaced apart from each other;
a plurality of semiconductor chips located side by side on the first surface of the interposer and each of the plurality of semiconductor chips being electrically connected to the routing structure and the through via at the same time; and
a redistribution structure on a second surface of the interposer and electrically connected to the through vias, the second surface of the interposer opposite the first surface of the interposer.
20. The multi-chip package of claim 19, wherein the wire width of the routing structure is less than 1 micron.
21. A method of manufacturing a multi-chip package, comprising:
providing a plurality of semiconductor chips on a first surface of a semiconductor substrate to electrically connect each of the plurality of semiconductor chips to a wiring structure in the semiconductor substrate;
forming an encapsulant on the first surface of the semiconductor substrate to encapsulate the plurality of semiconductor chips;
removing at least a portion of the semiconductor substrate from a second surface of the semiconductor substrate opposite the first surface to space remaining portions of the semiconductor substrate from each other;
forming a dielectric body in a space generated after the semiconductor substrate is removed;
forming through vias in the dielectric body that extend through the dielectric body and connect to the plurality of semiconductor chips; and
forming a redistribution line structure on the remaining portion of the semiconductor substrate and the dielectric body, the redistribution line structure being electrically connected to the through vias.
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| TW109114287 | 2020-04-29 | ||
| TW109114287A TWI734455B (en) | 2019-10-09 | 2020-04-29 | Multi-chip package and manufacture method thereof |
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