TW202137342A - Chip embedded substrate structure, chip package structure and methods of manufacture thereof - Google Patents

Abstract

A chip embedded substrate structure includes an encapsulant, a plurality of first pads and a plurality of second pads, a chip, a plurality of conductive connecting members and a redistribution layer. The encapsulant has a first surface and a second surface opposite to the first surface. The first pads and the second pads are embedded in the encapsulant and exposed on the first surface. The chip is embedded in the encapsulant and is connected to the first pads with an active surface. The conductive connecting members are embedded in the encapsulant and is located on the second pads. The second surface exposes the top surfaces of the conductive connecting members. The redistribution layer is located on the second surface and is connected to the top surfaces of the conductive connecting members. A manufacturing method of the chip embedded substrate structure, a chip package structure and a manufacturing method of the chip package structure are also provided.

Description

Chip embedded substrate structure and chip packaging structure and manufacturing method thereof

The invention relates to a substrate structure and a packaging structure and a manufacturing method thereof, and more particularly to a chip embedded substrate structure and a chip packaging structure and a manufacturing method thereof.

In recent years, terminal consumer electronic products have all adopted lightness, thinness, shortness, and smallness as their design requirements. This has led to the development of chip packaging in the direction of high density and thinness. In order to achieve thinness, the design of embedded substrates is often used at present. However, the substrates of these embedded substrates are mostly composed of BT resin containing glass fiber, which is expensive in material cost, which is not conducive to reducing manufacturing costs. In addition, embedding the wafer into the aforementioned substrate is also time-consuming and labor-intensive, which is not conducive to improving manufacturing efficiency. Therefore, how to achieve a thinner chip package structure while also reducing manufacturing costs and improving manufacturing efficiency is an important issue to be solved urgently.

The invention provides a chip embedded substrate structure and a chip packaging structure and a manufacturing method thereof, which can reduce the manufacturing cost and improve the manufacturing efficiency while realizing a thinner chip packaging structure.

The invention provides a chip embedded substrate structure, which includes a packaging glue, a plurality of first pads and a plurality of second pads, a chip, a plurality of conductive connectors, and a redistributed circuit layer. The packaging glue has a first surface and a second surface opposite to the first surface. A plurality of first pads and a plurality of second pads are embedded in the packaging compound and exposed on the first surface. The chip is embedded in the packaging compound and is connected to a plurality of first pads through an active surface. A plurality of conductive connecting elements are embedded in the packaging compound and located on the plurality of second pads. The second surface exposes the top surfaces of the plurality of conductive connections. The redistributed circuit layer is located on the second surface and connected to the top surfaces of the plurality of conductive connectors.

The present invention provides a manufacturing method of a wafer embedded substrate structure, which at least includes the following steps. A metal carrier is provided, wherein the metal carrier has a bearing surface. A plurality of first pads and a plurality of second pads are formed on the carrying surface. The chip is arranged on the carrying surface, wherein the active surface of the chip faces the carrying surface and is electrically connected to a plurality of first pads. A plurality of conductive connections are formed on the plurality of second pads. A packaging compound is formed to cover the plurality of first pads, the plurality of second pads, the chip and the plurality of conductive connections. The encapsulant has a first surface adjacent to the carrying surface and a second surface opposite to the first surface and exposing the top surfaces of the plurality of conductive connectors. The metal carrier is removed to expose the plurality of first pads, the plurality of second pads and the first surface. A redistributed circuit layer is formed on the second surface, so that the redistributed circuit layer is connected to the top surfaces of the plurality of conductive connectors.

The present invention provides a chip packaging structure, which includes the above-mentioned chip embedded substrate structure, electronic components, and a plurality of conductive terminals. The electronic component is arranged on the chip embedded substrate structure and electrically connected to the plurality of first pads and the plurality of second pads. A plurality of conductive terminals are connected to the redistributed circuit layer.

The present invention provides a method for manufacturing a chip package structure, which includes at least the following steps. Provided is a wafer embedded substrate structure manufactured by the above-mentioned method for manufacturing a wafer embedded substrate structure. The electronic component is arranged on the chip embedded substrate structure, and the electronic component is electrically connected to the plurality of first pads and the plurality of second pads. A plurality of conductive terminals are formed to connect the redistributed circuit layer.

Based on the above, since the chip-embedded substrate structure can omit the use of high-cost substrates, the manufacturing cost of the chip-embedded substrate structure can be reduced, and with the application of the metal carrier, it can be manufactured in a simpler manner. The manufacturing efficiency of the chip embedded substrate structure can be improved. Therefore, the chip package structure using the chip embedded substrate structure can realize a thinner chip package structure while reducing the manufacturing cost and improving the manufacturing efficiency.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The directional terms used herein (for example, up, down, right, left, front, back, top, bottom) are only used as a reference drawing and are not intended to imply absolute orientation.

Unless expressly stated otherwise, any method described herein is in no way intended to be construed as requiring its steps to be performed in a specific order.

The present invention will be explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The thickness, size or size of the layers or regions in the drawings will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

1A to 1E are schematic cross-sectional views of a chip embedded substrate structure in different stages of the manufacturing process according to an embodiment of the present invention. In this embodiment, the manufacturing method of the wafer embedded substrate structure 110 may include the following steps.

Please refer to FIG. 1A. First, a metal carrier 10 is provided, wherein the metal carrier 10 has a carrying surface 10a. Then, a plurality of first pads 12 and a plurality of second pads 14 are formed on the supporting surface 10a of the metal carrier board 10. For example, the plurality of second pads 14 may surround the plurality of first pads 12. In other words, the plurality of second pads 14 may be located on both sides or around the plurality of first pads 12. Here, the present invention does not limit the materials and forming methods of the metal carrier 10, the first pad 12, and the second pad 14 to be adjusted according to actual needs.

Please continue to refer to FIG. 1A, the chip 20 is arranged on the carrying surface 10 a of the metal carrier 10 and a plurality of conductive connections 30 are formed. For example, the chip 20 may be arranged on the plurality of first pads 12 and a plurality of conductive connections 30 may be formed on the plurality of second pads 14, wherein the plurality of conductive connections 30 may surround the chip 20. In this embodiment, the plurality of conductive connecting members 30 may be formed on the plurality of second pads 14 in a one-to-one manner. It should be noted that the present invention does not limit the process sequence of disposing the wafer 20 and forming the plurality of conductive connectors 30. For example, the chip 20 may be arranged first and then a plurality of conductive connections 30 may be formed, or a plurality of conductive connections 30 may be formed first and then the chip 20 may be arranged.

Furthermore, the chip 20 may have the active surface 20a facing the carrying surface 10a and electrically connected to the plurality of first pads 12. For example, the active surface 20 a of the chip 20 may have a plurality of conductive portions 22, and the chip 20 is bonded to the plurality of first pads 12 by flip chip bonding of the plurality of conductive portions 22. In some embodiments, the conductive part 22 may be a solder ball or a bump, but the present invention is not limited thereto. On the other hand, the plurality of conductive connectors 30 can be electrically connected to the plurality of second pads 14. In some embodiments, the conductive connection member 30 may include solder balls and solder pillars, but the present invention is not limited thereto. In addition, in order to enhance the bonding between the conductive connector 30 and the second pad 14 and/or between the chip 20 and the first pad 12, a soldering process and a reflow process can be selectively performed.

In this embodiment, as shown in FIG. 1A, the height 30h of the conductive connecting member 30 relative to the carrying surface 10a may not be lower than the height 20h of the wafer 20 relative to the carrying surface 10a. The height 30h may be the distance from the top surface 30a of the conductive connector 30 to the bearing surface 10a, and the height 20h of the chip 20 relative to the bearing surface 10a may be the distance from the back 20b of the chip 20 relative to the active surface 20a to the bearing surface 10a. In other words, the top surface 30a of the conductive connector 30 may be higher than the back surface 20b of the chip 20, but the present invention is not limited thereto.

1B, a packaging compound 40 is formed to cover the plurality of first pads 12, the plurality of second pads 14, the chip 20 and the plurality of conductive connectors 30, so that the plurality of first pads 12 and the plurality of second pads The second pad 14, the chip 20 and the plurality of conductive connectors 30 may be embedded in the packaging compound 40. For example, the height 40h of the encapsulant 40 may be greater than the height 30h of the conductive connector 30 relative to the carrying surface 10a and the height 20h of the chip 20 relative to the carrying surface 10a. On the other hand, the encapsulant 40 can be filled into the gap between the chip 20 and the metal carrier 10. The material of the encapsulant 40 is, for example, Epoxy Molding Compound (EMC), and the encapsulant 40 is formed by, for example, a molding process, but the present invention is not limited thereto.

Please refer to FIG. 1B and FIG. 1C at the same time. Then, the encapsulant 40 may be thinned to expose the top surface 30 a of the conductive connection member 30. In other words, after thinning the encapsulant 40, the height of the encapsulant 40 and the height of the conductive connector 30 relative to the bearing surface 10a can be reduced, so that the encapsulant 40 is reduced from the height 40h in FIG. 1B to the height 40h1 in FIG. 1C. And the conductive connecting member 30 is reduced from the height 30h in FIG. 1B relative to the carrying surface 10a to the height 30h1 in FIG. Furthermore, as shown in FIG. 1C, part of the conductive connector 30 can be removed in the process of thinning the encapsulant 40, so that the top surface 30a of the conductive connector 30 is flattened, so that the exposed conductive connector 30 The top surface 30a has a relatively large exposed area to reduce the probability of poor electrical connection between the subsequent conductive connector 30 and other components, but the present invention is not limited to this. In addition, the encapsulant 40 can be thinned by any suitable process. In addition, in one embodiment, as shown in FIG. 1C, the back surface 20b of the chip 20 may not be removed during the thinning process, so that the back surface 20b of the chip 20 is covered by the encapsulant 40, but the present invention is not limited to this. In an embodiment not shown, part of the back surface 20b of the wafer 20 can be further removed during the thinning process, so that the back surface 20b of the wafer 20 is exposed.

In this embodiment, the encapsulant 40 has a first surface 40a adjacent to the carrying surface 10a and a second surface 40b opposite to the first surface 40a and exposing the top surface 30a of the conductive connector 30. The height of the conductive connector 30 relative to the first surface 40a may not be lower than the height of the chip 20 relative to the first surface 40a, wherein the height of the conductive connector 30 relative to the first surface 40a corresponds to the aforementioned thinned encapsulant 40 after conductive connection The height 30h1 of the component 30 relative to the bearing surface 10a, and the height of the wafer 20 relative to the first surface 40a corresponds to the height 20h of the aforementioned wafer 20 relative to the bearing surface 10a.

1D, then, the metal carrier 10 is removed to expose the plurality of first pads 12, the plurality of second pads 14 and the first surface 40a. In other words, the plurality of first pads 12 and the plurality of second pads 14 are exposed on the first surface 40a. In this embodiment, the material of the metal carrier 10 may be different from the material of the first pad 12 and the second pad 14. Furthermore, the material of the metal carrier 10 and the materials of the first pad 12 and the second pad 14 may have a selective etching ratio, so that the metal carrier 10 can be directly removed by an etching process. For example, the material of the metal carrier 10 is copper, and the material of the first pad 12 and the second pad 14 is gold, palladium or a combination thereof, so as to have a good selective etching ratio, but the present invention is not limited to this. .

1E, after the metal carrier 10 is removed, a redistributed circuit layer 50 is formed on the second surface 40b, so that the redistributed circuit layer 50 is connected to the top surface 30a of the conductive connector 30. Furthermore, the redistributed circuit layer 50 may include a plurality of circuits 52 and an insulating layer 54, the circuit 52 is electrically connected to the conductive connector 30, and the insulating layer 54 covers the circuit 52 and has a plurality of openings 540 respectively exposing the plurality of circuits 52. Partial. It should be noted that the present invention does not limit the number of the wiring 52 and the insulating layer 54. The number of the wiring 52 and the insulating layer 54 in FIG. 1E is only shown as an example.

The material of the circuit 52 is, for example, copper, aluminum, gold, silver, or a combination thereof, and is formed, for example, by an electroplating process, and the material of the insulating layer 54 may include non-organic or organic dielectric materials, for example, the insulating layer 54 Examples of materials are silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (benezocyclobutene, BCB), Epoxy or its combination is formed by a deposition process, for example, but the invention is not limited thereto.

After the above-mentioned manufacturing process, the fabrication of the chip embedded substrate structure 110 of this embodiment can be substantially completed. The chip-embedded substrate structure 110 of this embodiment can omit the use of high-cost substrates, so the manufacturing cost of the chip-embedded substrate structure 110 can be reduced, and by the application of the metal carrier board 10, it can be implemented in a simpler manner. Therefore, the manufacturing efficiency of the wafer-embedded substrate structure 110 can be improved.

It must be noted here that the following embodiments follow the component numbers and part of the content of the above embodiments, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted, and the description of the omitted parts is omitted. Reference may be made to the foregoing embodiments, and the descriptions of the following embodiments will not be repeated.

2 is a schematic cross-sectional view of a chip package structure according to an embodiment of the invention. In this embodiment, the manufacturing method of the chip package structure 100 may include the following steps. Please refer to FIG. 2, a chip embedded substrate structure 110 is provided. Here, the chip-embedded substrate structure 110 can be manufactured by the method shown in FIG. 1A to FIG. 1E, which will not be repeated here. Next, a plurality of conductive terminals 120 are formed to connect to the redistributed circuit layer 50. The plurality of conductive terminals 120 may be electrically connected to the redistributed circuit layer 50, so a vertical conductive path can be formed between the plurality of second pads 14, the plurality of conductive connectors 30, the redistributed circuit layer 50, and the plurality of conductive terminals 120 . The plurality of conductive terminals 120 may be formed in the plurality of openings 540 of the insulating layer 54 in the redistributed wiring layer 50.

Since the wafer-embedded substrate structure 110 can omit the use of high-cost substrates, the manufacturing cost of the wafer-embedded substrate structure 110 can be reduced, and the metal carrier 10 can be manufactured in a simpler manner. The manufacturing efficiency of the chip-embedded substrate structure 110 can be improved. Therefore, the chip package structure 100 using the chip-embedded substrate structure 110 can realize a thinner chip package structure 100 while reducing the manufacturing cost and improving the manufacturing efficiency.

3 is a schematic cross-sectional view of a chip package structure according to another embodiment of the invention. 3, the difference between the chip package structure 200a of this embodiment and the chip package structure 100 is that the chip package structure 200a further includes an electronic component 230 disposed on the chip embedded substrate structure 110, and the electronic component 230 is electrically connected to a plurality of One pad 12 and a plurality of second pads 14. For example, the electronic component 230 may be disposed on the first surface 40a of the encapsulant 40. Therefore, the plurality of first pads 12 and the plurality of second pads 14 exposed in the chip-embedded substrate structure 110 can be further electrically connected with other electronic components 230, thereby achieving the high height of the chip package structure 200a. Densification.

Furthermore, in this embodiment, the electronic component 230 is a chip 232, wherein the chip 232 can be encapsulated by the encapsulant 240, but the invention is not limited to this. In an embodiment not shown, in addition to encapsulating the chip 232 by the encapsulant 240, the gap between the chip 232 and the chip-embedded substrate structure 110 can also be filled with an underfill. In another embodiment not shown, the chip 232 may not be encapsulated by the encapsulant 240, and only the gap between the chip 232 and the chip-embedded substrate structure 110 may be filled with primer. The packaging glue 240 may be similar to the packaging glue 40, and will not be repeated here.

4 is a schematic cross-sectional view of a chip package structure according to another embodiment of the present invention. 4, the difference between the chip package structure 200b and the chip package structure 200a of this embodiment is that the electronic component 230 is a chip package 234, and the chip package 234 can have a plurality of conductive terminals 250 and a chip embedded substrate structure. 110 electrical connection. For example, the chip package 234 may include a circuit substrate 2341, a chip 2342, a chip 2343, and a packaging compound 2344. The circuit substrate 2341 is, for example, a printed circuit board or a multilayer substrate made of other suitable materials. The chip 2342 and the chip 2343 can be sequentially stacked on the circuit substrate 2341, and can be electrically connected to the circuit substrate 2341 by wire bonding. In other words, the chip 2342 and the chip 2343 may have their back faces facing the circuit substrate 2341, but the invention is not limited to this. The encapsulant 2344 may be located on the circuit substrate 2341 and encapsulate the chip 2342 and the chip 2343. The packaging glue 2344 may be similar to the packaging glue 240 and the packaging glue 40, and will not be described here. In addition, the present invention does not limit the types of chip 20, chip 232, chip 2342, and chip 2343, which may be determined according to actual design requirements.

In summary, since the chip embedded substrate structure can omit the use of high-cost substrates, the manufacturing cost of the chip embedded substrate structure can be reduced, and the application of the metal carrier can be manufactured in a simpler manner Therefore, the manufacturing efficiency of the chip embedded substrate structure can be improved. Therefore, the chip package structure using the chip embedded substrate structure can realize a thinner chip package structure while reducing the manufacturing cost and improving the manufacturing efficiency. In addition, the plurality of first pads and the plurality of second pads exposed in the chip embedded substrate structure can be further electrically connected with other electronic components, thereby achieving a high density of the chip package structure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

10: Metal carrier board 10a: bearing surface 12: The first pad 14: The second pad 20, 232, 2342, 2343: chip 20a: active side 20b: back 20h, 30h, 30h1, 40h, 40h1: height 22: Conductive part 230: electronic components 234: chip package 2341: circuit board 30: Conductive connector 30a: Top surface 40, 240, 2344: encapsulation gel 40a: first surface 40b: second surface 50: Re-layout the circuit layer 52: Line 54: Insulation layer 540: open 100, 200a, 200b: chip package structure 110: Chip embedded substrate structure 120, 250: conductive terminals

1A to 1E are schematic cross-sectional views of a chip embedded substrate structure in different stages of the manufacturing process according to an embodiment of the present invention. 2 is a schematic cross-sectional view of a chip package structure according to an embodiment of the invention. 3 is a schematic cross-sectional view of a chip package structure according to another embodiment of the invention. 4 is a schematic cross-sectional view of a chip package structure according to another embodiment of the present invention.

12: The first pad

14: The second pad

20: chip

30: Conductive connector

30a: Top surface

40: Encapsulation colloid

40a: first surface

40b: second surface

50: Re-layout the circuit layer

52: Line

54: Insulation layer

540: open

110: Chip embedded substrate structure

Claims (12)

A chip embedded substrate structure includes: An encapsulant having a first surface and a second surface opposite to the first surface; A plurality of first pads and a plurality of second pads are embedded in the packaging compound and exposed to the first surface; A chip embedded in the packaging compound and connected to the plurality of first pads through an active surface; A plurality of conductive connectors, which are embedded in the packaging compound and located on the plurality of second pads, wherein the second surface exposes the top surfaces of the plurality of conductive connectors; and The redistributed circuit layer is located on the second surface and connected to the top surface of the plurality of conductive connectors. The chip embedded substrate structure according to claim 1, wherein the height of the plurality of conductive connections relative to the first surface is not lower than the height of the chip relative to the first surface. The chip embedded substrate structure according to claim 1, wherein the redistributed circuit layer includes a plurality of circuits and an insulating layer, the plurality of circuits are electrically connected to the plurality of conductive connectors, and the insulating layer covers all The plurality of circuits have a plurality of openings respectively exposing parts of the plurality of circuits. The chip embedded substrate structure according to claim 1, wherein the plurality of conductive connections include solder balls and solder pillars. A method for manufacturing a wafer embedded substrate structure includes: Providing a metal carrier board, wherein the metal carrier board has a bearing surface; Forming a plurality of first pads and a plurality of second pads on the carrying surface; Disposing a chip on the carrying surface, wherein the chip has an active surface facing the carrying surface and is electrically connected to the plurality of first pads; Forming a plurality of conductive connections on the plurality of second pads; A packaging glue is formed to cover the plurality of first pads, the plurality of second pads, the chip and the plurality of conductive connectors, wherein the packaging glue has a first contact adjacent to the carrying surface A surface and a second surface opposite to the first surface and exposing the top surface of the plurality of conductive connectors; Removing the metal carrier board to expose the plurality of first pads, the plurality of second pads and the first surface; and A redistributed circuit layer is formed on the second surface, so that the redistributed circuit layer is connected to the top surfaces of the plurality of conductive connectors. The method for manufacturing a chip embedded substrate structure according to claim 5, further comprising thinning the packaging compound to expose the top surface of the plurality of conductive connectors. The method for manufacturing a chip embedded substrate structure according to claim 5, wherein the height of the plurality of conductive connectors relative to the carrying surface is not lower than the height of the chip relative to the carrying surface. The manufacturing method of the chip embedded substrate structure according to claim 5, wherein the material of the metal carrier is different from the materials of the plurality of first pads and the plurality of second pads. A chip packaging structure, including: The chip embedded substrate structure according to any one of claim 1 to claim 4; Electronic components are arranged on the chip embedded substrate structure and electrically connected to the plurality of first pads and the plurality of second pads; and A plurality of conductive terminals are connected to the redistributed circuit layer. The chip package structure according to claim 9, wherein the electronic component includes a chip and a chip package. A method for manufacturing a chip packaging structure includes: Provide a wafer-embedded substrate structure manufactured by the method for manufacturing a wafer-embedded substrate structure according to any one of Claims 5 to 8; Disposing an electronic component on the chip embedded substrate structure, and the electronic component is electrically connected to the plurality of first pads and the plurality of second pads; and A plurality of conductive terminals are formed to connect the redistributed circuit layer. The method for manufacturing a chip package structure according to claim 11, wherein the electronic component includes a chip and a chip package.

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