CN106158772B - Plate grade embedded packaging structure and preparation method thereof - Google Patents
Plate grade embedded packaging structure and preparation method thereof Download PDFInfo
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- CN106158772B CN106158772B CN201510140205.4A CN201510140205A CN106158772B CN 106158772 B CN106158772 B CN 106158772B CN 201510140205 A CN201510140205 A CN 201510140205A CN 106158772 B CN106158772 B CN 106158772B
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- circuit board
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Abstract
The invention discloses a kind of plate grade embedded packaging structures, comprising: circuit board；Opening in circuit board, to accommodate semiconductor chip or cavity；It is respectively arranged at first and second line layer on the first and second surface of circuit board, and the first and second line layer passes through the conductive path electrical connection through circuit board, the first and second route layer surface respectively corresponds the highest of circuit board, minimum surface；Semiconductor chip in opening or cavity, the chip are electrically connected through the second line layer with first line layer, and the I/O bond pad surface of the chip is at least exposed from the second route layer surface, and is in same plane with the minimum surface of circuit board；Encapsulating material, to the space not occupied by chip in the first surface of covering board, first line layer and filling opening or cavity.The present invention also provides the methods for making the plate grade embedded packaging structure.The packaging cost of sensor can be greatly reduced by the present invention, reduce encapsulation volume, and effectively promote the performance of sensor.
Description
Technical field
The present invention relates to a kind of circuit board package structure, especially a kind of plate grade embedded packaging structure and its production side
Method can be applied to the sensor cores such as semiconductor chip, especially capacitive fingerprint sensing device, cmos image sensor (CIS)
The encapsulation of piece.
Background technique
Currently, Wire Bonding Technology is generally applied in the encapsulation process of capacitance type sensor or CIS chip.For example,
Existing capacitance type sensor IC/CIS encapsulation generally use Wire Bonding Technology realize on chip tactile disk and encapsulate internal cabling it
Between interconnection.Then in place of these technologies all Shortcomings.
I.e. by taking encapsulating structure shown in FIG. 1 as an example, at least there is following deficiency:
1, Wire Bonding Technology is the line bonding connection based on single-chip, and for I/O pad more on single-chip (I/O weldering
Disk) number multi-thread bonding be it is asynchronous, process speed is slow.
2, line forms comparable height with the combination technology that is bonded of line on chip.It is packed in fingerprint sensor chip
Afterwards, this will lead to fingerprint and exists at a distance from quite remote between chip, to seriously affect the sensitivity of sensor.
3, the technology on support plate is placed in using wire-bond technology and chip, the thickness of finally formed encapsulating structure is larger.
4, this packing forms is at high cost.
Summary of the invention
The main purpose of the present invention is to provide plate grade embedded packaging structure of a kind of improvement and preparation method thereof, with gram
Take deficiency in the prior art.
For realization aforementioned invention purpose, the technical solution adopted by the present invention includes:
In one embodiment of this invention, a kind of plate grade embedded packaging structure includes:
Circuit board；
Opening in the circuit board, to accommodate semiconductor chip or cavity,
It is respectively arranged at the first line layer and the second line layer of the first surface and second surface of the circuit board, and institute
The conductive path that first line layer and the second line layer are passed through through the circuit board is stated to be electrically connected, the first line layer surface with
Second route layer surface respectively corresponds the highest face temperature and minimum surface of the circuit board；
The semiconductor chip being set in the opening or cavity, the chip are electrically connected through the second route and first line layer
It connects, and surface I/O pad (I/O pad) of the chip is at least exposed from the second route layer surface, and with described second
The minimum surface of route layer surface or the circuit board is in same plane；
Encapsulating material, to cover first surface, first line layer and the filling opening or cavity of the circuit board
The space not occupied by the chip inside.
As more one of preferred embodiment, module register guide is additionally provided on the first surface of the circuit board
Know, at least for assisting the chip precisely to place.
As more one of preferred embodiment, the first line layer includes module contraposition mark.
Further, all or part of module contraposition mark can be as connection line and offer conducting function.
As more one of preferred embodiment, the opening or cavity highest face temperature in the vertical direction and minimum
Surface is respectively the highest face temperature of the circuit board or the minimum surface or institute of the first line layer surface and the circuit board
State the second route layer surface, and the boundary of the opening or cavity in the horizontal direction is the circuit board in first surface and the
The side wall of opening or cavity between two surfaces, while the opening or cavity include that the first space, second space and third are empty
Between, wherein first spatial distribution, between the first surface and second surface of the circuit board, the second space is distributed
Between the first surface and the first line layer surface of the circuit board, the third spatial distribution is in the circuit board
Between second surface and the second route layer surface.
Further, circuit board of the side wall in first space between the circuit board first surface and second surface
Continuous section, and the second space and third space are without side wall.
Further, the semiconductor chip is sensor chip, the sensitive face and I/O pad table of the sensor chip
Face and the minimum surface of the second route layer surface or the circuit board are coplanar.
Further, the encapsulating material also may extend to the second surface of covering board.
Further, the plate grade embedded packaging structure further includes tertiary circuit layer, and setting on top of the encapsulation material, and passes through
Conductive path through encapsulating material is electrically connected with first line layer.
As more one of preferred embodiment, the plate grade embedded packaging structure further includes solder mask, to
Cover the second surface and second, third described line layer and encapsulating material of the circuit board, but the sensitive face of the chip
Expose from the solder mask for covering second line layer.
As more one of preferred embodiment, the plate grade embedded packaging structure further includes protective layer, at least
The sensitive face of the sensor chip is continuously covered, or at least continuously covers solder mask and the institute of the circuit board second surface
State the sensitive face of sensor chip.
Further, the plate grade embedded packaging structure further includes pad array, and setting is covering the third line
It is electrically connected in road floor and the solder mask on encapsulating material surface opening and with the tertiary circuit floor, the pad array includes ball
Grid array or contact array.
In one embodiment of this invention, the production method of the plate grade embedded packaging structure includes:
(1) circuit board is provided, the first surface and second surface of the circuit board are respectively arranged with first line layer and the
Two line layers, the first line layer and the second line layer pass through the conductive path electrical connection through the circuit board, and the electricity
The opening or cavity for accommodating semiconductor chip are provided on the plate of road；
(2) adhesive film is attached in the second route layer surface, and the chip upside down is entered into the opening or cavity,
And the sensitive face of the chip is made to be adhesively fixed with adhesive film；
(3) it is at least applied on the first surface of the circuit board, the first line layer surface and the opening or cavity
Package material is sealed up, so that the first surface of the circuit board, the first line layer is packaged material covering, and make the opening
Or cavity is packaged material and the chip is filled up completely；
(4) adhesive film is removed, and is arranged in the second route layer surface and reroutes, thus by sensor chip
It is electrically connected with the second line layer, and forms tertiary circuit layer on the encapsulating material, and make tertiary circuit layer and First Line
The electrical connection of road floor；
(5) solder mask is set in the both side surface of step (4) obtained device, but covers the sensitive face of the chip certainly
It covers in the circuit board second surface and the solder mask of the second route layer surface and exposes, and covering the tertiary circuit layer
Pad array is set in the solder mask opening on encapsulating material surface, and the pad array is made to be electrically connected with tertiary circuit layer
It connects；
As more one of preferred embodiment, the production method of the plate grade embedded packaging structure may also include that
(6) masking structures of the setting with protective effect at least on the sensitive face of the chip.
Further, the masking structures may include the protective layer.
As one of preferred embodiment, the masking structures may also include the sapphire glass being covered on the protective layer
Glass.
As one of preferred embodiment, the masking structures may also include infrared glass, described at least continuous cover
The sensitive face of the solder mask of circuit board second surface and the sensor chip, and the infrared glass and the sensor
There are gap between the sensitive face of chip, the light through the infrared glass is enable to shine directly into the sensor chip
Sensitive face on.
Compared with prior art, the present invention at least has the advantages that
1, the plate grade embedded packaging structure has high production efficiency and excellent performance, and low in cost；
2, the manufacturing process of the plate grade embedded packaging structure is the Board level packaging process of high production speed, hence it is evident that is better than base
In the inefficient production process of single-chip bonding connecting line technics；
3, in the plate grade embedded packaging structure, the distance between surface of fingerprint sensor and chip is very small, thus
The sensitivity of sensor can effectively be promoted；
4, using the plate grade embedded packaging structure, it can be achieved that the small size of sensor encapsulates.
Detailed description of the invention
Fig. 1 is the schematic diagram for the sensor core chip package realized using Wire Bonding Technology；
Fig. 2 is the vertical view of the substrate with first line layer, opening or cavity and wiring board in one embodiment of the invention
Figure；
Fig. 3 a is a kind of substrate with first line layer, opening or cavity and wiring board in one embodiment of the invention
Transverse sectional view；
Fig. 3 b is a kind of with first line layer, the substrate of opening or cavity and wiring board in another embodiment of the present invention
Transverse sectional view；
Fig. 4 a is a kind of substrate with first line layer, opening or cavity and wiring board in one embodiment of the invention
Longitudinal sectional view；
Fig. 4 b is a kind of with first line layer, the substrate of opening or cavity and wiring board in another embodiment of the present invention
Longitudinal sectional view；
Fig. 5 a- Fig. 5 b be in one embodiment of the invention sensor chip with the face-down state merging opening of sensitive face or empty
Schematic diagram in chamber；
Fig. 6 a- Fig. 6 b be with device shown in encapsulating material package drawing 5b and the adhesive film in removal devices and by it is inverted
Schematic diagram；
Fig. 7 is the schematic diagram that route is arranged on the device shown in Fig. 6 b；
Fig. 8 is the schematic diagram that solder mask and BGA are arranged on device shown in Fig. 7；
Fig. 9 is a kind of capacitive fingerprint sensor chip-packaging structure schematic diagram in one embodiment of the invention；
Figure 10 is a kind of CIS sensor chip package structure diagram in one embodiment of the invention；
Description of symbols: encapsulating structure 100, package substrate 110, the semiconductor chip 120, half of fingerprint sensor chip
Conductor chip sensitive face 121, semiconductor chip sensitive face 123, conductive connecting line 130, packing colloid 140, upper surface of base plate 150,
Circuit board 1, first surface 101, second surface 102, opening or the side wall 103 of cavity, the side wall 104 of opening or cavity, opening
Or cavity 2, the first space 201, second space 202, third space 203, module contraposition mark 3, module contraposition mark connecting plate
4, landing chassis (landing pad) 5, encapsulating material 6, first line layer 7, first line layer surface 701, the second line layer 8,
Two line layers surface 801, conductive path 9, adhesive film 10, sensing chip 11, sensitive face 111, I/O pad 112, reroute 12,
Tertiary circuit layer 13, conductive path 14, solder mask 15, BGA 16, protective layer 17, sapphire glass 18, IR glass 19, gap
20, L- is lateral, V- is longitudinal.
Specific embodiment
With reference to embodiments and attached drawing more specifically illustrates technical solution of the present invention.
In one embodiment of this invention, a kind of basic structure of plate grade embedded packaging structure may include:
Circuit board 1, especially PCB circuit board；
First line layer 7 and the second line layer 8 are respectively arranged at the first surface 101 and second surface of the circuit board 1
102, and the first line layer and the second line layer pass through the electrical connection of conductive path 9 through the circuit board；
In sensor chip 11, the opening being set on the circuit board or cavity 2, and the sensor chip 11 and
Two line layers 8 are electrically connected, and are especially directly electrically connected；
Encapsulating material 6, to cover the first surface 101 of the circuit board 1, first line layer and the filling opening or
The space not occupied by the chip in cavity, further, the encapsulating material also may extend to the second of covering board 1
Surface 102；
Tertiary circuit layer 13 is arranged on encapsulating material 6, and conductive path 14 and first line through running through encapsulating material
Layer electrical connection.
Wherein, the sensitive face 111 of the sensor chip 11 at least exposes from 8 surface 801 of the second line layer, especially
It is to be directly exposed in air.
Further, protection structure can be also set in the encapsulating structure, to cover and protect the biography of sensor chip
Sense face.
Further, the protection structure may include protective layer, at least cover the sensitive face of the sensor chip.
Further, in I/O pad (I/O pad) 112 via lines of the sensor chip 11 and the second line layer 8
Route (Trace) electrical connection.Further, the surface I/O pad of the chip and the second route layer surface 801 or the electricity
The minimum surface of road plate is in same plane.
Further, 1 surface of circuit board is especially additionally provided with module contraposition mark on circuit board first surface 101,
To realize accurate flip-chip arrangement and conducting wire interconnection.
Further, the first line layer 7 is precisely placed containing module contraposition mark for companion chip.
Further, the first line layer 7 is precisely placed, all containing module contraposition mark 3 for companion chip
Mark or portion identification become connection line simultaneously and provide conducting function.
And for the opening or cavity 2 for accommodating the chip, highest face temperature and minimum table in the vertical direction
Face is respectively first line layer surface 701 and the second route layer surface 801, i.e. respectively the highest face temperature of circuit board and minimum table
Face.Meanwhile the boundary of the opening or cavity 2 in the horizontal direction is the circuit board 1 in first surface 101 and the second table
The side wall 103,104 of opening or cavity between 102 faces.
It further says, the space of the opening or cavity 2 includes:
Opening or void space between first space 201, i.e. circuit board first surface 101 and second surface 102,
Second space 202, the i.e. sky of the first space above surface to first line layer surface 701 (circuit board highest face temperature)
Between,
And third space 203, i.e. the first space underlying surfaces to (the minimum table of circuit board of second layer route layer surface 801
Face) space.
Further, the side wall in first space 201 is between circuit board first surface 101 and second surface 102
The continuous section of circuit board, and the second space and third space are without side wall.
Further, the plate grade embedded packaging structure further includes solder mask 15, continuously to cover the circuit
The second surface 102 of plate 1 and second, third described line layer 8,13 and encapsulating material 6, but the sensitive face of sensor chip 11
111 expose from the solder mask for covering the circuit board second surface 102.
First line layer 7 and the second line layer 8 are respectively arranged on the first, second surface 101,102 of the circuit board 1,
And the first line layer surface 701 and the second route layer surface 801 respectively and correspond to the upper and lower of the opening or cavity 2
End face that is to say the highest face temperature and minimum surface of the circuit board.
In one more specifically case study on implementation, the first line layer also may include module contraposition mark, to realize
Accurate chip layout, module contraposition mark include alignment mark with connection, and the route is via conducting path and the
The route of two line layers interconnects, and/or, module contraposition mark is the contraposition mark to realize precise die arrangement.
Further, referring to Fig.2, module contraposition mark may include module contraposition mark 3, module contraposition mark connection
Plate 4, landing chassis 5 etc..
Preferably, the sensitive face 111 of the sensor chip 11 and the second circuit surface 801, that is, the opening or sky
The bottom face of chamber is coplanar.
Wherein, first, second, third line layer is preferably formed by materials such as Cu.
Wherein, the tertiary circuit layer 13 is also referred to as RDL (rerouting layer), mutual with the route on the second line layer
Even.
Further, the conducting path that sensor chip encapsulation is interconnected comprising RDL and with the route of first line layer.
Further, RDL route is connect with encapsulation accumulation layer surface.
Further, the route on RDL route and first line layer passes through the conducting path interconnection across encapsulating material.
Further, encapsulating material is filled in remaining in addition to the region occupied by sensor chip in opening or cavity
Region more than space, opening or cavity, not by the region of route and module contraposition mark covering.
Further, the region of first line layer, opening or cavity or more is covered, not by route and alignment mark covering
The encapsulating material in region be an accumulated layers.
Further, solder mask layer covers the RDL in accumulated layers and accumulated layers, but has reserved the region BGA or LGA.
Further, solder mask layer covers the second line layer, connects the route on I/O pad and the second line layer, not
The board area covered by the second line layer, but sensing chip face is not covered.
Further, each conducting path above-mentioned can be conductive blind hole (blind via) or conduction PTH (heavy copper hole,
Plating Through Hole), but not limited to this.
Further, the plate grade embedded packaging structure further includes protective layer, at least continuously covers the sensor
The sensitive face of chip, it is preferred that its solder mask at least continuously covering the circuit board second surface and the sensor core
The sensitive face of piece.
In one more specifically case study on implementation, the protection structure further comprises the indigo plant being covered on the protective layer
Cameo glass.
In another more specifically case study on implementation, the further infrared glass of the protection structure is at least continuous to cover
The solder mask of the circuit board second surface and the sensitive face of the sensor chip, and the infrared glass and the biography
There are gap between the sensitive face of sensor chip, the light through the infrared glass is enable to shine directly into the sensor
On the sensitive face of chip.
Further, the plate grade embedded packaging structure further includes pad array, and setting is covering the third line
It is electrically connected in road floor and the solder mask on encapsulating material surface opening and with tertiary circuit floor, the pad array includes BGA
(Ball Grid Array) array or LGA (Land Grid Array) array.
And in one embodiment of this invention, a kind of production method of plate grade embedded packaging structure may include:
(1) circuit board 1 is provided, the first surface 101 and second surface 102 of the circuit board are respectively arranged with first line
Layer 7 and the second line layer 8, the first line layer 7 and the second line layer 8 are electrically connected through the conductive path 9 through the circuit board
It connects, and is provided with the opening or cavity 2 that can accommodate sensor chip 11 on the circuit board 1, please refer to Fig. 2, Fig. 3 a- figure
3b, Fig. 4 a- Fig. 4 b；
(2) adhesive film 10 is attached in the second route layer surface 801 of the circuit board 1, and by sensor chip to fall
The form merging opening or cavity 2 are set, and the sensitive face 111 of sensor chip 11 is made to be adhesively fixed with adhesive film 10, please be join
Read Fig. 5 a and Fig. 5 b；
(3) at least apply encapsulating material 6 on the first surface 101 of the circuit board 1 and the opening or cavity 2, make
The first surface 101 and first line layer 7 of circuit board 1 are packaged the covering of material 6, and keep the opening or cavity 2 packed
Material 6 and sensor chip 11 are filled up completely, and the encapsulating material 6 filled also may extend to the second surface of covering board
102, please refer to Fig. 6 a；
In this step, can also planarizing process be carried out to encapsulating material.
Wherein, encapsulating material can be molding compounds (Molding compound), and epoxy resin or epoxy resin/
Filler compound etc. is filled into cavity and covers first line layer as a flat stack layer.
(4), Fig. 6 b is please referred to, the adhesive film 10 is removed, device is overturn, and in the second route of the circuit board 1
Setting reroutes 12 in layer surface 801, so that the I/O pad 112 of sensor chip 11 is electrically connected with the second line layer 8, with
And tertiary circuit layer 13, such as Cu RDL are formed on the encapsulating material 6, and make tertiary circuit layer 13 and first line layer 7
Electrical connection, please refers to Fig. 7；
Wherein, the aforementioned Cu RDL with the I/O pad 112 of chip, the circuit link on 8 surface of the second route is to pass through metal
Change, upper photoresist, photoetching, etching and removing photoresistance are formed.
Further, blind hole can be formed by laser boring, then copper facing forms Cu layers, finally upper photoresist, photoetching, erosion
Carve and removing photoresistance and form pattern and route.
(5) solder mask 15 is set in the both side surface of step (4) obtained device, but makes the sensing of sensor chip 11
Face 111 is exposed from the solder mask for covering 1 second surface 102 of circuit board, and is covering first table of circuit board
Ball grid array 16 or contact array are set on the solder mask in face 101, and make the ball grid array or contact array and third line
Road floor 13 is electrically connected, and please refers to Fig. 8；
Wherein, solder mask can be formed by coating or compound, photoetching and annealing, and cover both side surface except sensor core
The sensitive face 111 of piece 11 and corresponding to the region except the opening of BGA or LGA.
(6) masking structures of the setting with protective effect at least on the sensitive face 111 of the sensor chip 11；
For example, referring to Fig. 9, protective layer 17 is arranged in device surface, making its at least continuous cover in a case study on implementation
The solder mask 15 of the circuit board second surface 102 and the sensitive face 111 of the sensor chip 11, and in the protection
Sapphire glass 18 or other similar materials are covered on layer.The encapsulating structure is suitable for the encapsulation of capacitive fingerprint sensor etc..
In another example in another case study on implementation, referring to Fig. 10, at least continuously covering the circuit using infrared glass 19
The solder mask 15 of plate second surface 102 and the sensitive face 111 of the sensor chip, and the infrared glass and the biography
There are gap 20 between the sensitive face of sensor chip, the light through the infrared glass is enable to shine directly into the sensing
On the sensitive face 111 of device chip.The encapsulating structure is suitable for the encapsulation of CIS (CMOS Image Sensor) sensor etc..
The packaging cost of sensor can be greatly reduced using design of the invention, reduce encapsulation volume, and can also have
Effect promotes the performance of sensor, for example, its sensitivity is substantially improved.
It should be appreciated that the technical concepts and features of above-described embodiment only to illustrate the invention, its object is to allow be familiar with this
The personage of item technology cans understand the content of the present invention and implement it accordingly, and it is not intended to limit the scope of the present invention.It is all
Equivalent change or modification made by Spirit Essence according to the present invention, should be covered by the protection scope of the present invention.
Claims (13)
1. a kind of plate grade embedded packaging structure, characterized by comprising:
Circuit board；
It is in the circuit board, at least to the opening or cavity that accommodate semiconductor chip,
It is respectively arranged at the first surface of the circuit board, the first line layer of second surface, the second line layer, and described first
Line layer and the second line layer pass through the conductive path electrical connection through the circuit board, and the first line layer is far from circuit board
One side surface, second line layer respectively correspond the highest face temperature, minimum of the circuit board far from a side surface of circuit board
Surface；
The semiconductor chip being set in the opening or cavity, the chip are sensor chip, and the chip is through the second line
Road floor is electrically connected with first line floor, and the sensitive face of the chip and I/O bond pad surface are at least from the second line layer table
It shows out, and is in same plane with the minimum surface of the second route layer surface or the circuit board；
Encapsulating material, at least first surface, first line layer and the filling opening or cavity to cover the circuit board
The space not occupied by the chip inside.
2. plate grade embedded packaging structure according to claim 1, it is characterised in that: on the first surface of the circuit board
It is additionally provided with module contraposition mark, at least for assisting the chip precisely to place.
3. plate grade embedded packaging structure according to claim 2, it is characterised in that: the first line layer includes described
Module contraposition mark.
4. plate grade embedded packaging structure according to claim 2 or 3, it is characterised in that: all or part of mould
Block contraposition mark can be as connection line and offer conducting function.
5. plate grade embedded packaging structure according to claim 1, it is characterised in that: the opening or cavity are in vertical side
Upward highest face temperature, minimum surface are respectively the highest face temperature or the first line layer surface, the electricity of the circuit board
The minimum surface of road plate or the second route layer surface, and the boundary of the opening or cavity in the horizontal direction is the electricity
The side wall of opening or cavity of the road plate between first surface and second surface, while the opening or cavity include first empty
Between, second space and third space, wherein first spatial distribution the circuit board first surface and second surface it
Between, the second space is distributed between the first surface of the circuit board and the first line layer surface, and the third is empty
Between be distributed between the second surface of the circuit board and the second route layer surface.
6. plate grade embedded packaging structure according to claim 5, it is characterised in that: the side wall in first space is institute
The continuous section of circuit board between circuit board first surface and second surface is stated, and the second space and third space are without side
Wall.
7. plate grade embedded packaging structure according to claim 1, it is characterised in that: the encapsulating material, which also extends to, to be covered
Cover the second surface of the circuit board.
8. according to claim 1-3, plate grade embedded packaging structure described in any one of 5-6, it is characterised in that further include
Three line layers, setting on top of the encapsulation material, and are electrically connected through the conductive path through encapsulating material with first line layer.
9. plate grade embedded packaging structure according to claim 8, it is characterised in that further include solder mask, to cover
The second surface of the circuit board and second, third described line layer and encapsulating material, but the sensitive face of the chip covers certainly
It covers in the solder mask of second line layer and exposes.
10. plate grade embedded packaging structure according to claim 9, it is characterised in that further include protective layer, at least connect
The continuous sensitive face for covering the sensor chip.
11. plate grade embedded packaging structure according to claim 9, it is characterised in that it further include pad array, setting
It is electrically connected in the solder mask opening for covering the tertiary circuit layer and encapsulating material surface and with the tertiary circuit layer, institute
Stating pad array includes ball grid array or contact array.
12. the production method of plate grade embedded packaging structure described in any one of claim 1-11, characterized by comprising:
(1) circuit board is provided, first surface, the second surface of the circuit board are respectively arranged with first line layer, the second route
Layer, the first line layer and the second line layer pass through the conductive path electrical connection through the circuit board, and on the circuit board
It is provided at least for accommodating the opening or cavity of semiconductor chip；
(2) adhesive film is attached in the second route layer surface, and the chip is placed in the opening or cavity, and make institute
The sensitive face and adhesive film for stating chip are adhesively fixed；
(3) at least apply envelope on the first surface of the circuit board, the first line layer surface and the opening or cavity
Package material makes the first surface of the circuit board, first line layer be packaged material covering, and makes the opening or cavity quilt
Encapsulating material and the chip are filled up completely；
(4) remove the adhesive film, and be arranged on the second surface of the circuit board and reroute, thus by sensor chip with
The electrical connection of second line layer, and tertiary circuit layer is formed on the encapsulating material, and make tertiary circuit layer and first line
Layer electrical connection；
(5) solder mask is set in the both side surface of step (4) obtained device, but the sensitive face of the chip is made to cover institute certainly
It states and exposes in circuit board second surface and the solder mask of the second route layer surface, and covering the tertiary circuit layer and envelope
Pad array is set in the solder mask opening on package material surface, and is electrically connected the pad array with tertiary circuit layer.
13. the production method of plate grade embedded packaging structure described in claim 12, it is characterised in that further include:
(6) masking structures of the setting with protective effect at least on the sensitive face of the chip.
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| CN106449554B (en) * | 2016-12-06 | 2019-12-17 | 苏州源戍微电子科技有限公司 | chip embedded packaging structure with closed cavity and manufacturing method thereof |
| CN106531711B (en) * | 2016-12-07 | 2019-03-05 | 华进半导体封装先导技术研发中心有限公司 | A kind of the Board level packaging structure and production method of chip |
| US10644046B2 (en) | 2017-04-07 | 2020-05-05 | Samsung Electronics Co., Ltd. | Fan-out sensor package and optical fingerprint sensor module including the same |
| KR102019353B1 (en) * | 2017-04-07 | 2019-09-09 | 삼성전자주식회사 | Fan-out sensor package and optical-type fingerprint sensor module |
| EP3454363A4 (en) * | 2017-07-20 | 2019-08-21 | Shenzhen Goodix Technology Co., Ltd. | Chip package structure, chip module, and electronic terminal |
| CN108649041B (en) * | 2018-04-16 | 2021-01-26 | 复旦大学 | Chip packaging structure based on composite interconnection substrate and method thereof |
| CN108831875B (en) * | 2018-08-10 | 2024-03-05 | 浙江熔城半导体有限公司 | Packaging structure with embedded filter chip and external electrode and manufacturing method thereof |
| CN109494163A (en) * | 2018-11-20 | 2019-03-19 | 苏州晶方半导体科技股份有限公司 | The encapsulating structure and packaging method of chip |
| CN109768026B (en) * | 2018-12-20 | 2021-06-15 | 西安华为技术有限公司 | Embedded substrate and manufacturing method thereof |
| WO2021016838A1 (en) * | 2019-07-30 | 2021-02-04 | 深圳市汇顶科技股份有限公司 | Image sensor and manufacturing method therefor, chip, and handheld apparatus |
| CN111261526A (en) * | 2020-01-19 | 2020-06-09 | 华为技术有限公司 | Packaging structure and preparation method thereof |
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Effective date of registration: 20200612 Address after: 313200 No. 926 Changhong East Street, Fuxi Street, Deqing County, Huzhou City, Zhejiang Province (Mogan Mountain National High-tech Zone) Patentee after: Zhejiang Rongcheng Semiconductor Co., Ltd Address before: Suzhou City, Jiangsu province 215000 Suzhou Industrial Park South Pavilion rain Street No. 18 building 6 room 1503 apartment essence Patentee before: Cai Qinjia |