CN204424252U - The embedding formula Board level packaging structure of semiconductor chip - Google Patents
The embedding formula Board level packaging structure of semiconductor chip Download PDFInfo
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- CN204424252U CN204424252U CN201520179649.4U CN201520179649U CN204424252U CN 204424252 U CN204424252 U CN 204424252U CN 201520179649 U CN201520179649 U CN 201520179649U CN 204424252 U CN204424252 U CN 204424252U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Abstract
The utility model discloses a kind of embedding formula Board level packaging structure of semiconductor chip, comprising: circuit board; Be located in circuit board, in order to the opening of accommodating semiconductor chip or cavity; Be arranged at first and second line layer on first and second surface of circuit board respectively, and first and second line layer is through running through the conductive path electrical connection of circuit board, the highest, the minimum surface of first and second line layer surface difference corresponding circuits plate; Be located at the semiconductor chip in opening or cavity, this chip is electrically connected with first line layer through the second line layer, and the I/O bond pad surface of this chip is at least exposed from the second line layer surface, and is in same plane with the minimum surface of circuit board; Encapsulating material, in order to the first surface of covering board, first line layer and to fill in opening or cavity not by space that chip occupies.Significantly can reduce the packaging cost of transducer by design of the present utility model, reduce encapsulation volume, and effectively promote the performance of transducer.
Description
Technical field
The utility model relates to a kind of circuit board package structure, particularly a kind of embedding formula Board level packaging structure and preparation method thereof of semiconductor chip, it can be applicable to semiconductor chip, especially the encapsulation of the sensor chip such as capacitive fingerprint sensing device, cmos image sensor (CIS).
Background technology
At present, Wire Bonding Technology is generally applied in the encapsulation process of capacitance type sensor or CIS chip.Such as, existing capacitance type sensor IC/CIS encapsulates the interconnection usually adopting Wire Bonding Technology to realize tactile disk on chip and encapsulate between inner cabling.Then these technology are Shortcomings part all.
Namely for the encapsulating structure shown in Fig. 1, it at least has following deficiency:
1, Wire Bonding Technology is connect based on the line bonding of single-chip, and is asynchronous for the multi-thread bonding of many I/O pad on single-chip (I/O pad) number, and process speed is slow.
2, the bonding combination technology of line and line defines suitable height on chip.After fingerprint sensor chip is packed, there is distance quite far away by causing in this, thus has a strong impact on the sensitivity of transducer between fingerprint and chip.
3, employing wire-bond technology and chip are placed in the technology on support plate, and the thickness of the final encapsulating structure formed is larger.
4, the cost of this packing forms is high.
Utility model content
Main purpose of the present utility model is the embedding formula Board level packaging structure of the semiconductor chip providing a kind of improvement, to overcome deficiency of the prior art.
For realizing aforementioned utility model object, the technical solution adopted in the utility model comprises:
In an embodiment of the present utility model, a kind of embedding formula Board level packaging structure of semiconductor chip comprises:
Circuit board;
Be located in described circuit board, in order to the opening of accommodating semiconductor chip or cavity,
Be arranged at the first surface of described circuit board and the first line layer of second surface and the second line layer respectively, and described first line layer and the second line layer are through running through the conductive path electrical connection of described circuit board, the highest face temperature of described first line layer surface and the corresponding described circuit board of the second line layer surface difference and minimum surface;
Be arranged at the semiconductor chip in described opening or cavity, described chip is electrically connected with first line layer through the second circuit, and the I/O pad of described chip (I/O pad) surface is at least exposed from described second line layer surface, and be in same plane with the minimum surface of described second line layer surface or described circuit board;
Encapsulating material, in order to cover the first surface of described circuit board, first line layer and to fill in described opening or cavity not by space that described chip occupies.
As one of comparatively preferred embodiment, the first surface of described circuit board is also provided with module contraposition mark, at least precisely places for auxiliary described chip.
As one of comparatively preferred embodiment, described first line layer comprises described module contraposition mark.
Further, part or all of described module contraposition mark as connection line and can provide conducting function.
As one of comparatively preferred embodiment, it is surperficial that the highest face temperature of described opening or cavity in the vertical direction and minimum surface are respectively the highest face temperature of described circuit board or the minimum surface of described first line layer surface and described circuit board or described second line layer, and described opening or cavity border is in the horizontal direction the opening of described circuit board between first surface and second surface or the sidewall of cavity, described opening or cavity comprise the first space simultaneously, second space and the 3rd space, wherein said first spatial distribution is between the first surface and second surface of described circuit board, described second space is distributed between the first surface of described circuit board and described first line layer surface, described 3rd spatial distribution is between the second surface and described second line layer surface of described circuit board.
Further, the sidewall in described first space is the continuous cross section of circuit board between described circuit board first surface and second surface, and described second space and the 3rd space are without sidewall.
Further, described semiconductor chip is sensor chip, the minimum surface copline of the sensitive face of described sensor chip and I/O bond pad surface and described second line layer surface or described circuit board.
Further, described encapsulating material also may extend to the second surface of covering board.
Further, the embedding formula Board level packaging structure of described semiconductor chip also comprises tertiary circuit layer, arrange on top of the encapsulation material, and the conductive path through running through encapsulating material is electrically connected with first line layer.
As one of comparatively preferred embodiment, the embedding formula Board level packaging structure of described semiconductor chip also comprises solder mask, in order to cover the second surface of described circuit board and second, third line layer described and encapsulating material, but the sensitive face of described chip exposes in the solder mask covering described second line layer.
As one of comparatively preferred embodiment; the embedding formula Board level packaging structure of described semiconductor chip also comprises protective layer; it covers the sensitive face of described sensor chip at least continuously, or covers the solder mask of described circuit board second surface and the sensitive face of described sensor chip at least continuously.
Further, the embedding formula Board level packaging structure of described semiconductor chip also comprises pad array, it to be arranged in the solder mask opening covering described tertiary circuit layer and encapsulating material surface and to be electrically connected with described tertiary circuit layer, and described pad array comprises ball grid array or contact array.
In an embodiment of the present utility model, additionally provide a kind of manufacture method of embedding formula Board level packaging structure of semiconductor chip, it comprises:
(1) circuit board is provided, the first surface of described circuit board and second surface are respectively arranged with first line layer and the second line layer, described first line layer and the second line layer are through running through the conductive path electrical connection of described circuit board, and the opening described circuit board is provided with for accommodating semiconductor chip or cavity;
(2) attach adhesive film on the surface at described second line layer, and described chip upside down is entered described opening or cavity, and the sensitive face of described chip and adhesive film are adhesively fixed;
(3) at least on the first surface of described circuit board, described first line layer surface and described opening or cavity, encapsulating material is applied, the packed material of the first surface of described circuit board, described first line layer is covered, and described opening or the packed material of cavity and described chip are filled completely;
(4) described adhesive film is removed, and arrange on the surface at described second line layer and reroute, thus sensor chip is electrically connected with the second line layer, and tertiary circuit layer is formed on described encapsulating material, and tertiary circuit layer is electrically connected with first line layer;
(5) step (4) obtain device both side surface on solder mask is set, but the sensitive face of described chip is exposed in the solder mask covering described circuit board second surface and the second line layer surface, and pad array is set in the solder mask opening covering described tertiary circuit layer and encapsulating material surface, and described pad array is electrically connected with tertiary circuit layer;
As one of comparatively preferred embodiment, the manufacture method of the embedding formula Board level packaging structure of described semiconductor chip also can comprise:
(6) masking structures with protective effect is at least set on the sensitive face of described chip.
Further, described masking structures can comprise described protective layer.
As one of better embodiment, described masking structures also can comprise the sapphire glass be covered on described protective layer.
As one of better embodiment, described masking structures also can comprise infrared glass, it covers the solder mask of described circuit board second surface and the sensitive face of described sensor chip at least continuously, and leave gap between the sensitive face of described infrared glass and described sensor chip, the light through described infrared glass is shone directly on the sensitive face of described sensor chip.
Compared with prior art, the utility model at least tool have the following advantages:
1, the embedding formula Board level packaging structure of this semiconductor chip has high production efficiency and premium properties, and with low cost;
2, the manufacturing process of the embedding formula Board level packaging structure of this semiconductor chip is the Board level packaging process of high production speed, is obviously better than the inefficient production process based on single-chip bonding connecting line technics;
In the embedding formula Board level packaging structure of 3, this semiconductor chip, the distance between fingerprint sensor and the surface of chip is very little, thus effectively can promote the sensitivity of transducer;
4, utilize the embedding formula Board level packaging structure of this semiconductor chip, the small size encapsulation of transducer can be realized.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the sensor chip encapsulating structure adopting Wire Bonding Technology to realize;
Fig. 2 has first line layer, the vertical view of the substrate of opening or cavity and wiring board in the utility model one embodiment;
Fig. 3 a is that in the utility model one embodiment, one has first line layer, the transverse sectional view of the substrate of opening or cavity and wiring board;
Fig. 3 b is that in another embodiment of the utility model, one has first line layer, the transverse sectional view of the substrate of opening or cavity and wiring board;
Fig. 4 a is that in the utility model one embodiment, one has first line layer, the longitudinal sectional view of the substrate of opening or cavity and wiring board;
Fig. 4 b is that in another embodiment of the utility model, one has first line layer, the longitudinal sectional view of the substrate of opening or cavity and wiring board;
Fig. 5 a-Fig. 5 b is that in the utility model one embodiment, sensor chip inserts the schematic diagram in opening or cavity with the ventricumbent state of sensitive face;
Fig. 6 a-Fig. 6 b encapsulates adhesive film in device shown in Fig. 5 b and removal devices with encapsulating material and by it inverted schematic diagram;
Fig. 7 is the schematic diagram arranging circuit on device shown in Fig. 6 b;
Fig. 8 is the schematic diagram arranging solder mask and BGA on device shown in Fig. 7;
Fig. 9 is a kind of capacitive fingerprint sensor chip-packaging structure schematic diagram in the utility model one embodiment;
Figure 10 is a kind of CIS sensor chip encapsulating structure schematic diagram in the utility model one embodiment;
Description of reference numerals: the encapsulating structure 100 of fingerprint sensor chip, base plate for packaging 110, semiconductor chip 120, semiconductor chip sensitive face 121, semiconductor chip sensitive face 123, conductive connecting line 130, packing colloid 140, upper surface of base plate 150, circuit board 1, first surface 101, second surface 102, the sidewall 103 of opening or cavity, the sidewall 104 of opening or cavity, opening or cavity 2, first space 201, second space 202, 3rd space 203, module contraposition mark 3, module contraposition mark connecting plate 4, landing chassis (landing pad) 5, encapsulating material 6, first line layer 7, first line layer surface 701, second line layer 8, second line layer surface 801, conductive path 9, adhesive film 10, sensing chip 11, sensitive face 111, I/O pad 112, reroute 12, tertiary circuit layer 13, conductive path 14, solder mask 15, BGA 16, protective layer 17, sapphire glass 18, IR glass 19, gap 20, L-laterally, V-longitudinally.
Embodiment
Below in conjunction with embodiment and accompanying drawing, more specifically explanation is explained to the technical solution of the utility model.
In an embodiment of the present utility model, a kind of basic structure of embedding formula Board level packaging structure of semiconductor chip can comprise:
Circuit board 1, particularly PCB;
First line layer 7 and the second line layer 8, be arranged at first surface 101 and the second surface 102 of described circuit board 1 respectively, and described first line layer and the conductive path 9 of the second line layer through running through described circuit board are electrically connected;
Sensor chip 11, be arranged in opening on described circuit board or cavity 2, and described sensor chip 11 is electrically connected with the second line layer 8, is particularly directly electrically connected;
Encapsulating material 6, in order to cover first surface 101, the first line layer of described circuit board 1 and to fill not by the space that described chip occupies in described opening or cavity, further, described encapsulating material also may extend to the second surface 102 of covering board 1;
Tertiary circuit layer 13, is arranged on encapsulating material 6, and the conductive path 14 through running through encapsulating material is electrically connected with first line layer.
Wherein, the sensitive face 111 of described sensor chip 11 at least exposes from described second line layer 8 surface 801, particularly, is directly exposed in air.
Further, also operator guards can be set in described encapsulating structure, to cover and to protect the sensitive face of sensor chip.
Further, described operator guards can comprise protective layer, and it at least covers the sensitive face of described sensor chip.
Further, I/O pad (I/O pad) 112 via line of described sensor chip 11 are electrically connected with the circuit (Trace) on the second line layer 8.Further, the I/O pad surface of described chip is in same plane with the minimum surface of the second line layer surface 801 or described circuit board.
Further, described circuit board 1 surface, particularly circuit board first surface 101 is also provided with module contraposition mark, arranges and conducting wire interconnection in order to realize accurate flip-chip.
Further, described first line layer 7, containing module contraposition mark, is precisely placed for companion chip.
Further, described first line layer 7, containing module contraposition mark 3, is precisely placed for companion chip, and all mark or portion identification become connection line simultaneously and provide conducting function.
And for for the opening of accommodating described chip or cavity 2, the highest face temperature of its in the vertical direction and minimum surface are respectively first line layer surface 701 and the second line layer surface 801, are namely respectively highest face temperature and the minimum surface of circuit board.Meanwhile, the sidewall 103,104 of described opening or the cavity 2 border in the horizontal direction opening that is described circuit board 1 between first surface 101 and the second table 102 or cavity.
Further say, the space of described opening or cavity 2 comprises:
First space 201, the opening namely between circuit board first surface 101 and second surface 102 or void space,
Second space 202, namely the first space overhead surface is to the space on first line layer surface 701 (circuit board highest face temperature),
And the 3rd space 203, namely the first space underlying surfaces is to the space on second layer line layer surface 801 (circuit board minimum surface).
Further, the sidewall in described first space 201 is the continuous cross section of circuit board between circuit board first surface 101 and second surface 102, and described second space and the 3rd space are without sidewall.
Further, the embedding formula Board level packaging structure of described semiconductor chip also comprises solder mask 15, in order to cover the second surface 102 of described circuit board 1 and described second, third line layer 8,13 and encapsulating material 6 continuously, but the sensitive face 111 of sensor chip 11 exposes in the solder mask covering described circuit board second surface 102.
First line layer 7 and the second line layer 8 are located on first, second surface 101,102 of described circuit board 1 respectively, and described first line layer surface 701 and the second line layer surface 801 are distinguished and correspond to the upper and lower end face of described opening or cavity 2, that is to say highest face temperature and the minimum surface of described circuit board.
In one more specifically case study on implementation, described first line layer also can comprise module contraposition mark, in order to realize accurate chip layout, this module contraposition mark comprises the alignment mark with connection, this circuit is interconnected via the circuit of conducting path and the second line layer, and/or module contraposition mark is the contraposition mark realizing precise die layout.
Further, consult Fig. 2, described module contraposition mark can comprise module contraposition mark 3, module contraposition mark connecting plate 4, landing chassis 5 etc.
Preferably, the sensitive face 111 of described sensor chip 11 and the second circuit surface 801, that is the bottom face copline of described opening or cavity.
Wherein, described first, second, third line layer can preferably be formed by materials such as Cu.
Wherein, described tertiary circuit layer 13 also can be described as RDL (reroute layer), the interconnect on itself and the second line layer.
Further, sensor chip wrapper is containing RDL and the conducting path interconnected with the circuit of first line layer.
Further, RDL circuit is connected with encapsulation accumulated layers surface.
Further, the circuit on RDL circuit and first line layer is interconnected through the conducting path through encapsulating material.
Further, encapsulating material is filled in the region of more than its complementary space, opening or the cavity in opening or cavity except the region occupied by sensor chip, is not identified by circuit and module contraposition the region covered.
Further, cover the region of more than first line layer, opening or cavity, the encapsulating material in region that do not covered by circuit and alignment mark is an accumulated layers.
Further, solder mask layer covers the RDL in accumulated layers and accumulated layers, but has reserved BGA or LGA region.
Further, solder mask layer covers the second line layer, connects the circuit on I/O pad and the second line layer, not by the board area that the second line layer covers, but does not cover sensing chip face.
Further, aforesaid each conducting path can be conductive blind hole (blind via) or conduction PTH (heavy copper hole, PlatingThrough Hole), but is not limited thereto.
Further; the embedding formula Board level packaging structure of described semiconductor chip also comprises protective layer; it covers the sensitive face of described sensor chip at least continuously, and preferably, it covers the solder mask of described circuit board second surface and the sensitive face of described sensor chip at least continuously.
In one more specifically case study on implementation, described operator guards comprises the sapphire glass be covered on described protective layer further.
In another more specifically case study on implementation; the further infrared glass of described operator guards; it covers the solder mask of described circuit board second surface and the sensitive face of described sensor chip at least continuously; and leave gap between the sensitive face of described infrared glass and described sensor chip, the light through described infrared glass is shone directly on the sensitive face of described sensor chip.
Further, the embedding formula Board level packaging structure of described semiconductor chip also comprises pad array, it to be arranged in the solder mask opening covering described tertiary circuit layer and encapsulating material surface and to be electrically connected with tertiary circuit layer, and described pad array comprises BGA (Ball Grid Array) array or LGA (Land Grid Array) array.
And in an embodiment of the present utility model, a kind of manufacture method of embedding formula Board level packaging structure of semiconductor chip can comprise:
(1) circuit board 1 is provided, the first surface 101 of described circuit board and second surface 102 are respectively arranged with first line layer 7 and the second line layer 8, described first line layer 7 and the conductive path 9 of the second line layer 8 through running through described circuit board are electrically connected, and described circuit board 1 is provided with can the opening of accommodating sensor chip 11 or cavity 2, refer to Fig. 2, Fig. 3 a-Fig. 3 b, Fig. 4 a-Fig. 4 b;
(2) on the second line layer surface 801 of described circuit board 1, adhesive film 10 is attached, and sensor chip is inserted described opening or cavity 2 with reversion form, and the sensitive face 111 of sensor chip 11 is adhesively fixed with adhesive film 10, refer to Fig. 5 a and Fig. 5 b;
(3) at least on the first surface 101 of described circuit board 1 and described opening or cavity 2, encapsulating material 6 is applied, the first surface 101 of circuit board 1 and the packed material 6 of first line layer 7 are covered, and described opening or the packed material 6 of cavity 2 and sensor chip 11 are filled completely, and the encapsulating material 6 of filling also may extend to the second surface 102 of covering board, refers to Fig. 6 a;
In this step, also planarizing process can be carried out to encapsulating material.
Wherein, encapsulating material can be molding compounds (Molding compound), epoxy resin, or epoxy resin/filler compound etc., it is filled into cavity and covers first line layer as a smooth accumulation horizon.
(4), refer to Fig. 6 b, remove described adhesive film 10, device is overturn, and setting reroutes 12 on the second line layer surface 801 of described circuit board 1, thus the I/O pad 112 of sensor chip 11 is electrically connected with the second line layer 8, and tertiary circuit layer 13 is formed on described encapsulating material 6, such as Cu RDL, and tertiary circuit layer 13 is electrically connected with first line layer 7, refer to Fig. 7;
Wherein, with the aforementioned Cu RDL of the circuit link on I/O pad 112, second circuit 8 surface of chip be by metallizing, upper photoresistance, photoetching, etching and removing photoresistance formation.
Further, form blind hole by laser drilling, then copper facing forms Cu layer, finally go up photoresistance, photoetching, etches and removing photoresistance and form pattern and circuit.
(5) step (4) obtain device both side surface on solder mask 15 is set, but the sensitive face 111 of sensor chip 11 is exposed in the solder mask covering described circuit board 1 second surface 102, and ball grid array 16 or contact array are set on the solder mask covering described circuit board first surface 101, and described ball grid array or contact array are electrically connected with tertiary circuit layer 13, refer to Fig. 8;
Wherein, solder mask is formed by coating or compound, photoetching and annealing, and covers both side surface except the sensitive face 111 of sensor chip 11 with corresponding to the region except the opening of BGA or LGA.
(6) masking structures with protective effect is at least set on the sensitive face 111 of described sensor chip 11;
Such as; in a case study on implementation; refer to Fig. 9; at device surface, protective layer 17 is set; make it cover the solder mask 15 of described circuit board second surface 102 and the sensitive face 111 of described sensor chip 11 at least continuously, and on described protective layer, cover sapphire glass 18 or other similar material.This encapsulating structure is suitable for the encapsulation of capacitive fingerprint sensor etc.
Again such as, in another case study on implementation, refer to Figure 10, infrared glass 19 is adopted to cover the solder mask 15 of described circuit board second surface 102 and the sensitive face 111 of described sensor chip at least continuously, and leave gap 20 between the sensitive face of described infrared glass and described sensor chip, the light through described infrared glass is shone directly on the sensitive face 111 of described sensor chip.This encapsulating structure is suitable for the encapsulation of CIS (CMOS Image Sensor) sensor.
Utilize design of the present utility model significantly can reduce the packaging cost of transducer, reduce encapsulation volume, and also effectively can promote the performance of transducer, such as, significantly promote its sensitivity.
Should be appreciated that above-described embodiment is only and technical conceive of the present utility model and feature are described, its object is to person skilled in the art can be understood content of the present utility model and implement according to this, protection range of the present utility model can not be limited with this.All equivalences done according to the utility model Spirit Essence change or modify, and all should be encompassed within protection range of the present utility model.
Claims (12)
1. an embedding formula Board level packaging structure for semiconductor chip, is characterized in that comprising:
Circuit board;
Be located in described circuit board, at least in order to opening or the cavity of accommodating semiconductor chip,
Be arranged at the first surface of described circuit board and the first line layer of second surface and the second line layer respectively, and described first line layer and the second line layer are through running through the conductive path electrical connection of described circuit board, the highest face temperature of described first line layer surface and the corresponding described circuit board of the second line layer surface difference and minimum surface;
Be arranged at the semiconductor chip in described opening or cavity, described chip is electrically connected with first line layer through the second line layer, and the I/O bond pad surface of described chip is at least exposed from described second line layer surface, and be in same plane with the minimum surface of described second line layer surface or described circuit board;
Encapsulating material, at least in order to cover the first surface of described circuit board, first line layer and to fill in described opening or cavity not by space that described chip occupies.
2. the embedding formula Board level packaging structure of semiconductor chip according to claim 1, the first surface that it is characterized in that described circuit board is also provided with module contraposition mark, at least precisely places for auxiliary described chip.
3. the embedding formula Board level packaging structure of semiconductor chip according to claim 2, is characterized in that described first line layer comprises described module contraposition mark.
4. the embedding formula Board level packaging structure of the semiconductor chip according to Claims 2 or 3, is characterized in that part or all of described module contraposition mark as connection line and can provide conducting function.
5. the embedding formula Board level packaging structure of semiconductor chip according to claim 1, it is characterized in that the highest face temperature of described opening or cavity in the vertical direction and minimum surface are respectively the highest face temperature of described circuit board or the minimum surface of described first line layer surface and described circuit board or described second line layer surperficial, and described opening or cavity border is in the horizontal direction the opening of described circuit board between first surface and second surface or the sidewall of cavity, described opening or cavity comprise the first space simultaneously, second space and the 3rd space, wherein said first spatial distribution is between the first surface and second surface of described circuit board, described second space is distributed between the first surface of described circuit board and described first line layer surface, described 3rd spatial distribution is between the second surface and described second line layer surface of described circuit board.
6. the embedding formula Board level packaging structure of semiconductor chip according to claim 5, it is characterized in that the sidewall in described first space is the continuous cross section of circuit board between described circuit board first surface and second surface, and described second space and the 3rd space are without sidewall.
7. the embedding formula Board level packaging structure of the semiconductor chip according to any one of claim 1-3,5-6, it is characterized in that described semiconductor chip is sensor chip, the minimum surface copline of the sensitive face of described sensor chip and I/O bond pad surface and described second line layer surface or described circuit board.
8. the embedding formula Board level packaging structure of semiconductor chip according to claim 1, is characterized in that described encapsulating material also extends to the second surface covering described circuit board.
9. the embedding formula Board level packaging structure of the semiconductor chip according to any one of claim 1-3,5-6, characterized by further comprising tertiary circuit layer, it is arranged on top of the encapsulation material, and the conductive path through running through encapsulating material is electrically connected with first line layer.
10. the embedding formula Board level packaging structure of semiconductor chip according to claim 9, characterized by further comprising solder mask, in order to cover the second surface of described circuit board and second, third line layer described and encapsulating material, but the sensitive face of described chip exposes in the solder mask covering described second line layer.
The embedding formula Board level packaging structure of 11. semiconductor chips according to claim 10, characterized by further comprising protective layer, it covers the sensitive face of described sensor chip at least continuously.
The embedding formula Board level packaging structure of 12. semiconductor chips according to claim 10, characterized by further comprising pad array, it to be arranged in the solder mask opening covering described tertiary circuit layer and encapsulating material surface and to be electrically connected with described tertiary circuit layer, and described pad array comprises ball grid array or contact array.
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| CN (1) | CN204424252U (en) |
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Effective date of registration: 20200619 Address after: 313200 No. 926 Changhong East Street, Fuxi Street, Deqing County, Huzhou City, Zhejiang Province (Mogan Mountain National High-tech Zone) Patentee after: Zhejiang Rongcheng Semiconductor Co., Ltd Address before: Suzhou City, Jiangsu province 215000 Suzhou Industrial Park South Pavilion rain Street No. 18 building 6 room 1503 apartment essence Patentee before: Cai Qinjia |
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