KR100608611B1 - Wafer level chip scale package using via hole and manufacturing method for the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer level chip scale package (WL-CSP) and a method of manufacturing the same, and more particularly, to a wafer level chip scale for forming external connection terminals such as solder balls on opposite surfaces of an active surface. The present invention relates to a package and a method of manufacturing the same, and for this purpose, a plurality of via holes penetrating the wafer at the wafer level are formed along the scribing line. And a method for manufacturing a wafer level chip scale package using a via hole, wherein a conductive line is electrically connected to the ball pads of the ball pads, and solder balls are formed on the ball pads of the lower surface after the semiconductor chips are individually separated. Through this structure and method, solder balls are formed on a lower surface of a semiconductor chip, thereby forming a chip scale package. Layer, or the application and scope of the chip scale package, such as that can be applied to a charge-coupled device can be extended, and it has a characteristic excellent in mass productivity, most of the process due to the carried out at the wafer level.

Description

Wafer level chip scale package using via hole and manufacturing method therefor {wafer level chip scale package using via hole and manufacturing method for the same}

1 is a cross-sectional view showing a conventional vijay package,

2 is a partial cutaway perspective view of a wafer level chip scale package using via holes in accordance with an embodiment of the present invention;

3a and 3b are a plan view and a rear view of FIG.

4 is a flowchart sequentially illustrating a method of manufacturing a wafer level chip scale package according to another embodiment of the present invention;

5A to 5F are process diagrams schematically illustrating the processes of FIG. 4.

Description of the main parts of the drawing

10, 110, 210: semiconductor chip 20: substrate

30, 260: via hole 40, 130, 230: sealing means

50, 150, 250: Solder Ball 100: Vigie This Package

112, 212: bonding pads 114, 214: active surface

116: lower surface 120, 220: conductive line

140, 240: metal wiring 200, 300: chip scale package

242: ball pad 270: wafer

272: Scribing Line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer level chip scale package (WL-CSP) and a method of manufacturing the same. More specifically, the present invention relates to an active surface of a semiconductor chip using via holes penetrating through a wafer. The present invention relates to a wafer level chip scale package using a via hole and a method of manufacturing the same, wherein an external connection terminal such as a solder ball is formed on the opposite side.

As semiconductor device manufacturing technology develops, traditional plastic packages tend to be light and short. Part of the plastic package using the lead frame has been developed into a ball grid array (BGA) package using a substrate and solder balls, and again a chip scale package that is almost similar in size to a semiconductor chip. It was developed in the form of CSP (Chip Scale Package).

In addition, by forming conductive via holes penetrating the substrate, the upper and lower surfaces of the substrate (such as metal wirings and ball pads formed on the upper and lower surfaces) may be electrically connected, or multilayer metal wirings may be formed.

1 is a cross-sectional view illustrating a conventional BG package 100 using a via hole. Referring to Figure 1 will be described as follows.

In the conventional BG package 100, a semiconductor chip 10 is mounted on an upper surface of a substrate 20 on which metal wires are formed and electrically connected through a bonding wire, and soldered to ball pads on a lower surface of the substrate 20, respectively. The balls 50 are attached.

An encapsulation means 40 such as epoxy is encapsulated above the upper surface of the substrate 20 including the semiconductor chip 10 to protect the electrical connection from the external environment. Electrically connected through the hole 30, the semiconductor chip is connected to the outside through the solder balls, which are external connection terminals.

As described above, the conventional via hole is formed in a member on which a semiconductor chip such as a substrate is mounted, and the package mounting area may be minimized by electrically connecting the upper and lower surfaces using the via hole.

Recently, a technique for directly manufacturing a chip scale package through a wafer fabrication process has been developed, and a package manufactured through such a technique is called a wafer level chip scale package (WL-CSP).

In the wafer level chip scale package, solder balls are generally formed on the active surface of the semiconductor chip, and according to the structure, a wafer package may be stacked or a sensor package (such as a charge coupled device (CCD)). When applied to fabrication of sensor package, etc., considerable structural difficulties have been followed.

Disclosure of Invention An object of the present invention is to provide a wafer level chip scale package and a method of manufacturing the same, wherein solder balls are formed on a lower surface of a semiconductor chip on which a bonding pad is not formed, and the bonding pad and the solder balls are electrically connected.

In order to achieve the above object, the present invention provides a semiconductor chip comprising a bottom surface opposite to an active surface on which bonding pads are formed; Conductive lines electrically connecting the active surface and the bottom surface, the conductive lines being formed along side surfaces of the semiconductor chip; A metal wire electrically connected to any bonding pad through a conductive line and forming a ball pad at a lower surface corresponding to the bonding pad; Encapsulation means for encapsulating bonding pads, metal lines and conductive lines; And solder balls respectively formed on the ball pads, wherein the conductive lines are formed by using via holes formed along the scribing line at the wafer level where the semiconductor chips are provided. Chip scale packages are available.

In addition, to achieve the above object, the present invention provides a method for manufacturing a wafer-level chip scale package as described above, comprising the steps of: preparing a wafer with semiconductor chips; Forming metal wires respectively connected to the bonding pads and the ball pads; Forming a plurality of via holes along the scribing line of the wafer; Forming a conductive line in the via hole; Separating the semiconductor chips along the scribing line; Encapsulating the semiconductor chip except for the ball pads; And forming solder balls on the ball pads, respectively.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a partial cutaway perspective view of a wafer level chip scale package 200 using via holes in accordance with one embodiment of the present invention, and FIGS. 3A and 3B illustrate the wafer level chip scale package 200 of FIG. 2. One top view and one rear view. 2 to 3B, a wafer level chip scale package 200 according to the present invention will be described.

In the wafer level chip scale package 200 according to the present invention, metal wires 140 connected to the bonding pads 112 are formed on the active surface 114 of the semiconductor chip 110 on which the bonding pads 112 are formed. Ball pads (not shown) are formed on the bottom surface 116, which is the opposite surface of the active surface 114, and solder balls 150 are formed on the respective ball pads.

Conductive lines 120 are formed along the side surfaces of the semiconductor chip 110 to electrically connect the metal wire 140 of the active surface 114 and the ball pads of the bottom surface 116. 110 is encapsulated with a sealing means 230 such as a photosensitive material-Photo Solder Resist (PSR) in the photolithography process.

In this case, the conductive line 120 is formed by using via holes formed along the scribing line at the wafer level where the semiconductor chips are provided. As such, the technique of forming via holes penetrating through the semiconductor chip at the wafer level can be achieved through a microelectromechanical system called MEMS (MicroElectroMechanical Systems).

In more detail, via holes such as laser drills or conventional etching techniques may be used to form via holes of a desired shape.

In this case, it is advantageous to form the thickness of the wafer to be smaller than about 320 μm, which is the thickness of a general wafer, and for actual processing, it is preferable to form the thickness of about 50 μm to 100 μm. For example, a thickness of a wafer for directly stacking semiconductor chips may be formed to about 50 μm.

The wafer level chip scale package of this structure has a degree of freedom in solder ball placement compared to a structure in which the solder balls are mounted after rearranging the wiring on the existing active surface, which is advantageous in applying a wafer level chip scale package.

4 is a flowchart sequentially illustrating a method for manufacturing a wafer level chip scale package according to another embodiment of the present invention, and FIGS. 5A to 5F are process diagrams briefly illustrating respective processes of FIG. 4. This will be described below with reference to FIGS. 4 to 5F.

Referring to FIG. 4, a method of manufacturing a wafer level chip scale package using via holes according to the present invention includes preparing a wafer having semiconductor chips (180), forming metal wiring (182), and a plurality of vias. Forming holes 184, forming conductive lines in the via holes 186, separating them into individual semiconductor chips 188, encapsulating 190 and bottom surfaces of the semiconductor chips. Step 192 of forming solder balls.

Such a manufacturing process will be described with reference to FIGS. 5A to 5F.

First, a wafer 270 in which the semiconductor chips 210 having the bonding pads 212 formed on the active surface 214 are separated through the scribing line 272 is prepared (FIG. 5A). Metal wires 240 and ball pads 242 connected to the bonding pads are formed over the semiconductor chip 210 (FIG. 5B) and a plurality of vias along the scribing line 272 of the wafer 270. Holes 260 are formed (FIG. 5C).

Via holes 260 may be formed through the wafer 270 through a so-called MEMS technique, and after the conductive lines 220 such as copper (Cu) are formed in each via hole 260, a photosensitive material-photo It is filled with sealing means 230, such as solder resist PSR (FIG. 5D). In this case, the thickness of the wafer 270 is preferably formed in the range of about 50 μm to 100 μm, and the via holes may be formed using laser drilling or etching technology.

As such, the semiconductor chips 210 having the bonding pads 212, the metal wires 240, the conductive lines 220, and the ball pads 242 electrically connected to each other are individually separated from the wafer through a sawing process. 5E, the separated semiconductor chip 210 is encapsulated with an encapsulation means 230 such as a photosensitive material PSR on a surface except the ball pad, and finally the ball pad exposed from the encapsulation means 230. Wafer level chip scale package 300 is fabricated by forming solder balls 250 over each of them (FIG. 5F).

In the above manufacturing method, the process of filling the photosensitive material into the via hole in which the conductive line is formed may be performed through a dotting process, and the process of encapsulating the surface of the separated semiconductor chip with the photosensitive material is dipping. It is generally carried out through a dipping process. Here, the dipping step is a step of encapsulating the individual semiconductor chips by immersing them in a container containing a liquid photosensitive material.

As described above, by using the via hole, a chip scale package having solder balls on the lower surface of the semiconductor chip can be manufactured at the wafer level, and in particular, the process until separation into individual semiconductor chips is performed at the wafer level. As a result, it is possible to manufacture a chip scale package having excellent mass productivity.

Wafer-level chip scale package and a method of manufacturing the same according to the present invention is characterized in that the via hole penetrating the wafer during the wafer manufacturing process, and the solder ball formed on the lower surface of the semiconductor chip using the formed via hole According to such a feature, the application range of the chip scale package can be extended, such as stacking the chip scale package, and the via hole is formed at the scribe line which is the boundary of the semiconductor chips. As most of the manufacturing processes are performed at the wafer level, it is possible to produce high volume chip scale packages.

Claims (6)

A semiconductor chip having ball pads formed on a bottom surface opposite to an active surface, bonding pads formed on the active surface, and metal wires connected to the bonding pads; Sealing means for sealing the semiconductor chip except for the ball pads; And Solder balls are formed on each of the ball pads, The semiconductor chip is formed in via holes formed along the scribing line while penetrating the active surface and the lower surface in a wafer state in which a plurality of the semiconductor chips are provided and a scribing line is formed between the semiconductor chips. A wafer level chip scale package comprising a conductive line electrically separating the bonding pad and the ball pad from the side of the semiconductor chip by being separated along an ice line. The wafer level chip scale package of claim 1, wherein the via hole is formed using a laser drill. The wafer level chip scale package of claim 2, wherein the wafer has a thickness of 50 to 100 μm. Preparing a wafer having semiconductor chips having bonding pads formed on an active surface and having scribing lines formed between the semiconductor chips; Forming ball pads on the active surface of the metal wiring connected to the bonding pads and on a bottom surface opposite to the active surface; Forming a plurality of via holes along the scribing line to penetrate the semiconductor chip; Forming conductive lines in the via holes to electrically connect the bonding pads of the active surface and the ball pads of the lower surface of the via holes; Separating the semiconductor chips along the scribing line such that the conductive line is exposed on the sides of the semiconductor chips; Encapsulating the semiconductor chip except for the ball pads; And Forming solder balls on the ball pads, respectively. The method of claim 4, wherein the via hole is formed using a laser drill. The method of claim 5, wherein the wafer has a thickness of 50 to 100 μm.

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