CN1303678C - Chip carrier holed semiconductor package element and mfg. method thereof - Google Patents
Chip carrier holed semiconductor package element and mfg. method thereof Download PDFInfo
- Publication number
- CN1303678C CN1303678C CNB02123194XA CN02123194A CN1303678C CN 1303678 C CN1303678 C CN 1303678C CN B02123194X A CNB02123194X A CN B02123194XA CN 02123194 A CN02123194 A CN 02123194A CN 1303678 C CN1303678 C CN 1303678C
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- China
- Prior art keywords
- chip
- perforate
- chip carrier
- semiconductor package
- coating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention relates to a semiconductor encapsulation member with openings of a chip seat and a manufacture method thereof. A lead frame composed of a chip seat and a plurality of base pins is provided with a chip in a sticking mode, and the chip is arranged on the chip seat which is provided with at least an opening; the bottom surface of the chip covers the openings of the chip seat and is exposed out of the openings of the chip seat; then, the bottom surface of the chip exposed out of the openings of the chip seat is coated with a coating layer; the coating layer is completely filled in the chip and the interspaces of the chip seat among the circumferential sides of the openings of the chip seat. After the wire solder operation of electrically connecting the chip and the base pins and the molding operation of forming an encapsulation colloid used for covering the chip and the chip seat are completed, because no interspace exists between the chip and the chip seat, the problem of generating void between the chip and the chip seat during the solidification shaping of the encapsulation colloid; the finished product completing encapsulation can not have the phenomenon of chip chipping (Die Crack) or generate the phenomenon of gas explosion (Popcorn).
Description
Technical field
The invention relates to a kind of semiconductor package part, is the semiconductor package part that chip bearing member and this chip carrier are formed with perforate about a kind of chip carrier with lead frame particularly.
Background technology
With lead frame (Lead Frame) is that the area of the common problem of semiconductor package part of the chip bearing member chip carrier (Die Pad) that is lead frame is big, and it is relatively poor in order to coat the cementability that glues between the packing colloid of being located at the chip on this chip carrier, make between this chip carrier and packing colloid in reliability testing or real work, because of variations in temperature produces layering (Delamination), cause the reliability of this semiconductor package part and quality to be affected.And the chip carrier of this semiconductor package part and the bond area of chip chamber are bigger, make the thermal stress effects that can be subjected to bigger chip carrier under the temperature cycles of chip in manufacture process and come, very easily cause producing between chip and chip carrier layering or the cracked situation generation of chip.
For addressing the above problem, United States Patent (USP) the 5th, 233, No. 222 case proposes a kind of chip carrier holed semiconductor package part, shown in accompanying drawing 3A.The chip carrier 30 of this kind semiconductor package part 3 is formed with a perforate 300, after being bonded on this chip carrier 30 by elargol (Silver Paste) 32 at a chip 31, the bottom surface 310 that this chip 31 must cover this perforate 300 and chip 31 must partly expose outside this perforate 300, the bond area of 30 of this chip 31 and chip carriers is significantly reduced, so can effectively reduce the thermal stress effects that 30 pairs of chips of chip carrier 31 produce, thereby avoid between the two layering and the cracked situation of chip to take place, simultaneously, borrow the formation of this perforate 300, can further promote cementability in order to 30 of the packing colloid 33 that coats this chip 31 and chip carriers.In like manner, United States Patent (USP) the 5th, 327, No. 008 case also proposes the semiconductor package part that a kind of chip carrier roughly is the X type, and its purpose is to reduce the bond area between chip and chip carrier, because its effect that can reach is analogous to the former, so refuse icon.
Though above-mentioned two United States Patent (USP)s have some advantages, during in order to the elargol of adhering chip to chip carrier, must strictly control the coating weight of elargol in coating.Therefore when the excessive coating of elargol, shown in accompanying drawing 3B, the situation of excessive elargol 32 by the past underflow stream in perforate 300 edges of chip carrier 30 can take place; In case elargol 32 is toward underflow stream, except that meeting is polluted to equipment and product itself, more because of the thermal coefficient of expansion (Coefficient of Thermal Expansion:CTE) of elargol 32 up to about 80ppm, make the interface of 32 of packing colloid 33 and elargol tend to produce layering because of bigger thermal expansion coefficient difference (CTE Dismatch); But when the coating of elargol is not enough, shown in accompanying drawing 3C, then be easy near the edge's leaving gap 301 30 perforates of chip 31 and chip carrier 300, when forming the molding operation of packing colloid 33, potting resin can't be fills up to 301 in gap fully, to gas hole (Voids) is produced; After the gas hole produces, in subsequent manufacturing processes, can make chip 31 rhegma (Crack) take place in formation place of gas hole.Thereby, no matter be that layering or gas hole form, all can influence reliability and acceptance rate to manufactured goods, yet, if strictly control the coating weight of elargol, then can cause the increase of manufacturing cost and the complexity of raising manufacture process, and often can't avoid the generation of the not enough or excessive problem of elargol coating weight fully.
In view of this, United States Patent (USP) the 4th, 942, No. 452 cases and the 5th, 150, No. 193 cases successively propose a kind of semiconductor package part that forms groove on chip carrier, with effective solution foregoing problems.As shown in Figure 4, the chip carrier 40 of this semiconductor package part 4 offers groove 401 in nearly perforate 400 places, after elargol 42 is coated on the chip carrier 40, this groove 401 can avoid causing because of elargol is excessive the appearance of excessive glue problem, though can effectively stop elargol 42 overflows like this to perforate 400, but when the coating weight of elargol 42 was not enough, the gas hole still can be formed in the uncoated gap 402 that elargol 42 arranged of 40 of chip 41 and chip carriers, and can't solve the puzzlement of gas hole formation.
Summary of the invention
Purpose of the present invention is promptly providing a kind of semiconductor package part of effectively avoiding the problem of formation of gas hole and elargol generation overflow.Another object of the present invention then is to provide a kind of manufacture method of effectively avoiding the semiconductor package part of formation of gas hole and elargol generation overflow problem.
For reaching above-mentioned and other purpose, semiconductor package part of the present invention is to comprise that one has the lead frame of a chip carrier and many pins, and this chip carrier also offers at least one perforate; The one glutinous chip of establishing to this chip carrier after this chip and chip carrier are bonding, makes this chip cover an end of this perforate, and in form between the two one with this perforate in succession gap mutually; Lay a coating layer on this chip exposes outside surface in the perforate, this chip is exposed outside surface coverage and the gap of filling between this chip and chip carrier fully in the perforate; Many in order to be electrically conducted the bonding wire of this chip and pin; And one in order to coat this chip, chip carrier, bonding wire, coating layer and pin packing colloid partly.
The method for making of semiconductor package part of the present invention then comprises the following steps: to prepare one by a chip carrier and many lead frames that lead constitutes, and makes this chip carrier be formed with at least one perforate; Borrow an adhesive with a die bonding to this chip carrier, cover with a end this perforate, and nearly this tapping forms a gap of leading to this perforate between this chip and chip carrier, via this perforate one coating layer is coated this chip and expose on the surface in this perforate, with the surface coverage of this chip and fully in the gap of filling between this chip and chip carrier; Be electrically conducted this chip and pin; And form a packing colloid, to coat this chip, chip carrier and this coating layer airtightly.
The perforate size and shape of this chip carrier does not have specific limited, as long as can make the bond area minimizing between chip and chip carrier and provide this chip to support fully.
Formation as for the gap between this chip and chip carrier, then as long as the consumption in order to the adhesive of adhering chip to the chip carrier is coated on the chip carrier in control, make this adhesive in die bonding to chip carrier on after, on the position of the nearly perforate in the surface of chip carrier, do not have adhesive and cover.
This coating layer then can use the resin compound of more flowability, as Polyimide resin etc., so that this coating layer is fills up in the gap between this chip and chip carrier fully, and the air that it is inner is discharged fully, when guaranteeing that molding operation is finished, the packing colloid in perforate does not have the gas hole and exists.
Description of drawings
Below be described in further detail characteristics of the present invention and effect with the preferred embodiment conjunction with figs.:
Accompanying drawing 1 is the cutaway view of semiconductor package part of the present invention;
Accompanying drawing 2A is the manufacturing flow chart of semiconductor package part of the present invention to accompanying drawing 2G;
Accompanying drawing 3A figure is the cutaway view of an existing semiconductor package part; And accompanying drawing 3B is in order to adhering chip in the semiconductor package part of expression accompanying drawing 3A and the excessive glue of the elargol of the chip carrier schematic diagram to the chip carrier perforate; Accompanying drawing 3C is in order to there to be the schematic diagram in gap between adhering chip and chip carrier in the semiconductor package part of expression accompanying drawing 3A; And
Accompanying drawing 4 is cutaway views of another existing semiconductor package part.
Symbol description
1 semiconductor package part, 10 lead frames
100 chip carrier 100a perforate 100b end faces
110 bottom surfaces, 100c bottom surface
101 pin ones, 1 chip
12 bonding wires, 13 packing colloids, 14 adhesives
15 gaps, 16 coating layers
3 semiconductor package parts, 30 chip carriers
300 perforates, 301 gaps
31 chips, 310 bottom surfaces
32 elargol, 33 packing colloids
4 semiconductor package parts, 40 chip carriers
400 perforates, 401 grooves, 42 elargol
Embodiment
As shown in Figure 1, semiconductor package part 1 of the present invention is by a lead frame 10, one is bonded to the chip 11 on this lead frame 10, many connect the bonding wires 12 of this chip 11 and lead frame 10 in order to conduction, and one in order to coat this chip 11, bonding wire 12 and partly the packing colloid 13 of lead frame 10 constitute.
This lead frame 10 is to have a chip carrier 100 and many pin ones 01 of being located at these chip carrier 100 outsides.This chip carrier 100 also is formed with a perforate 100a, makes this perforate 100a run through the end face 100b and the bottom surface 100c of this chip carrier 100 respectively; Simultaneously, this chip carrier 100 can form a plurality of perforates, and shape does not have specific limited, as long as can make this chip 11 utilize existing adhesive 14 to be bonded on the end face 100b of this chip carrier 100 as elargol etc., afterwards, this chip 11 cover nose end on the end face 100b that perforate 100a is positioned at chip carrier 100 fully, and the position that makes the bottom surface 110 of chip 11 correspond to this perforate 100a exposes among this perforate 100a and gets final product.
Be controlled at this chip 11 after 14 coatings of this adhesive when being bonded on the chip carrier 100, the unlikely adhesive 14 that is stained with on the position of the nearly perforate 100a of end face 100b of chip carrier 100, after making this chip 11 and chip carrier 100 bonding, in closely forming a gap 15 on the position of perforate 100a between the two, with the formation in this gap 15, can effectively avoid adhesive 14 in glutinous brilliant process (DieBonding) from the edge of this perforate 100a to underflow stream and contaminated equipment and the generation of half-finished problem; And because of adhesive 14 unlikely excessive glue in the hole wall of perforate 100a, therefore, packaging part can not appear at the situation of layering at this position.
Exposing outside at this chip 11 on the bottom surface 110 of perforate 100a also is coating one coating layer 16, can be made of Polyimide resin or other similar material.This coating layer 16 is to be used for this gap 15 of complete filling, so that the air in the gap 15 is discharged, after packing colloid 13 moulding, does not have the gas hole and is formed in this gap 15, does not take place so do not have the problem of gas explosion.The thickness of this coating layer 16 there is no specific limited, if its have enough flowabilities with complete filling in this gap 15.
The manufacture method of this semiconductor package part 1 is to shown in the accompanying drawing 2G as accompanying drawing 2A.In accompanying drawing 2A, prepare earlier one by chip carrier 100 and many lead frames 10 that pin one 01 is constituted, this chip carrier 100 also offers one and runs through the end face 100b of this chip carrier 100 and the perforate 100a of bottom surface 100c.This lead frame 10 is identical with existing lead frame, so will not further narrate at this.
Shown in accompanying drawing 2B, go up the adhesive 14 that constitutes by elargol with an amount of coating one of existing mode in the end face 100b of this chip carrier 100, during these adhesive 14 coatings, it should be controlled on the zone outside the nearly perforate 100a of the end face 100b edge;
Shown in accompanying drawing 2C, one chip 11 is placed on the end face 100b of this chip carrier 100, make this chip 11 borrow this adhesive 14 and be bonded on the chip carrier 100, and make the bottom surface 110 of chip 11 expose among the perforate 100a and cover the nose end that this perforate 100a is positioned at the end face 100b of chip carrier 100; Because the coating of no adhesive 14 on the position at the nearly perforate 100a of the end face 100b edge of this chip carrier 100, after so chip 11 and chip carrier 100 are bonding, be positioned between the two on the position at nearly perforate 100a edge and promptly form a gap 15, with avoid adhesive 14 in this glutinous brilliant (last slice) manufacture process overflow to perforate 100a, glutinous crystalline substance of the present invention (last slice) manufacture process is finished after no equipment or semi-finished product suffer the anxiety of adhesive 14 pollutions.
Shown in accompanying drawing 2D, after glutinous brilliant (last slice) manufacture process finishes, promptly the existing mode that is suitable for a glue or other is injected via this perforate 100a Polyimide resin that flowability is good and is applied on the bottom surface 110 of the chip 11 that exposes to this perforate 100a, to form a coating layer 16 that is covered in order to this gap 15 of complete filling on chip 11 bottom surfaces 110 by this Polyimide resin, the formation of this coating layer 16, air in the gap 15 gets fully and discharges, and does not have the formation in gas hole.
Shown in accompanying drawing 2E, after coating layer 16 forms,, this coating layer 16 is carried out baking-curing (Curing) handle for making its stable and curing.This kind baking-curing is treated to prior art, so do not give unnecessary details in addition at this.
Shown in accompanying drawing 2F, the lead frame 10 that is bonded with chip 11 is carried out bonding wire operation (WireBonging), electrically connect this chip 11 to each corresponding pin one 01 with gold thread 12.Because the enforcement of this bonding wire operation is prior art also, so do not repeat them here.
At last, shown in accompanying drawing 2G, the semi-finished product of finishing the bonding wire operation are inserted in the mould 17, form a packing colloid 13 to coat this chip 11, chip carrier 100 and gold thread 12 by potting resin.After this packing colloid 13 forms, respectively this pin one 01 part exposes outside this packing colloid 13 for its coating another part, be connected with external device (ED) (not icon) for the exposed parts of this pin one 01, but and make chip 11 itself and external device (ED) form the relation that is electrically conducted as printed circuit board (PCB).The carrying out of this molding operation (Molding) is prior art also, so do not repeat them here.
After these packing colloid 13 moulding, give baking-curing and form the semiconductor package part of the present invention 1 shown in the accompanying drawing 1.Remove slag (Trimming), impress (Marking) and clubfoot moulding steps such as (Forming) all is as good as with prior art, so do not give unnecessary details for literary composition in addition thereafter.
It is above-mentioned to combine institute, because the use of coating layer 16, the air in the gap of 100 of chip 11 and chip carriers can be discharged fully, can not form the gas hole and make to finish in the packing colloid 13 that encapsulates finished product, thus semiconductor package part of the present invention, the anxiety of no gas explosion generation; And owing to take place in order to the problem of the excessive glue of adhesive 14 nothings in the perforate 100a of chip carrier 100 of adhering chip 11 with chip carrier 100, so also do not have adhesive 14 because of 13 situations that produce layering of glue and packing colloid of overflowing.Thereby semiconductor package part 1 of the present invention has the acceptance rate of enhancement and reliability.
The above only is specific embodiments of the invention, and other is any not to break away from the equivalence of being done under spirit of the present invention and the technology and change or modify, and all should be included in claims.
Claims (11)
1. a chip carrier holed semiconductor package part is characterized in that, this semiconductor package part is to comprise:
One lead frame, its tool one chip carrier and many pins, wherein, this chip carrier offers at least one perforate;
One chip, it is to borrow an adhesive to be bonded on this chip carrier, covers and make the part surface of this chip to expose outside this perforate with the nose end with this perforate, and is formation one gap that is communicated with this perforate on this chip carrier and nearly this perforate position of chip chamber;
One coating layer, it is that perforate via this chip carrier exposes on the surface of this perforate to be formed at this chip, in this gap, the air in this gap is got rid of with complete filling fully;
Many conductive components connect this chip and pin in order to conduction; And
One packing colloid is in order to coat the part of this chip, chip carrier, conductive component and pin.
2. semiconductor package part as claimed in claim 1 is characterized in that, this coating layer is to be made by the good resin material of flowability.
3. semiconductor package part as claimed in claim 2 is characterized in that, this resin material is the Polyimide resin.
4. semiconductor package part as claimed in claim 1 is characterized in that this conductive component is a bonding wire.
5. semiconductor package part as claimed in claim 4 is characterized in that this bonding wire is a gold thread.
6. the manufacture method of a chip carrier holed semiconductor package part is characterized in that, this manufacture method comprises the following steps:
Prepare one by chip carrier and many lead frames that pin constitutes, this chip carrier is to be formed with at least one perforate;
, to this chip carrier, the surface portion of this chip is exposed outside in this perforate and a nose end of this perforate is covered with the bonding chip of an adhesive, simultaneously, then be formed with a gap of leading to this perforate between this chip and chip carrier on the position of nearly perforate;
Perforate via this chip carrier exposes outside in this chip on the surface of perforate to be coated with a coating layer, so that the air in it is discharged in the complete filling in this gap;
Weld many conductive components between this chip and pin, so that this chip and pin electrically connect; And
Form a packing colloid to coat the part of this chip, chip carrier, conductive component, coating layer and pin.
7. manufacture method as claimed in claim 6 is characterized in that, this coating layer is to be made by the good resin material of flowability.
8. manufacture method as claimed in claim 7 is characterized in that, this coating layer is the Polyimide resin.
9. manufacture method as claimed in claim 6 is characterized in that this conductive component is a bonding wire.
10. manufacture method as claimed in claim 9 is characterized in that this conductive component is a gold thread.
11. manufacture method as claimed in claim 6 is characterized in that, it also comprises the processing procedure of a baking-curing, so that coating layer is solidified after coating is finished.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB02123194XA CN1303678C (en) | 2002-06-28 | 2002-06-28 | Chip carrier holed semiconductor package element and mfg. method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB02123194XA CN1303678C (en) | 2002-06-28 | 2002-06-28 | Chip carrier holed semiconductor package element and mfg. method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1466199A CN1466199A (en) | 2004-01-07 |
| CN1303678C true CN1303678C (en) | 2007-03-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB02123194XA Expired - Fee Related CN1303678C (en) | 2002-06-28 | 2002-06-28 | Chip carrier holed semiconductor package element and mfg. method thereof |
Country Status (1)
| Country | Link |
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| CN (1) | CN1303678C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1997261B (en) * | 2006-01-05 | 2010-08-18 | 矽品精密工业股份有限公司 | Electronic carrier board and its packaging structure |
| CN101144886B (en) * | 2006-09-12 | 2012-06-06 | 乙太精密有限公司 | Focusing-free mini optical lens and its method |
| CN108493169A (en) * | 2018-05-31 | 2018-09-04 | 江苏长电科技股份有限公司 | Packaging structure without base island frame and process method thereof |
| CN110745772B (en) * | 2019-10-21 | 2023-10-20 | 重庆大学 | MEMS stress isolation packaging structure and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11284104A (en) * | 1998-03-27 | 1999-10-15 | Shindo Denshi Kogyo Kk | Integrated circuit package and manufacture thereof |
| JP2000294682A (en) * | 1999-04-08 | 2000-10-20 | Toshiba Corp | Semiconductor device |
| JP2000332167A (en) * | 1999-05-25 | 2000-11-30 | Denso Corp | Mounting method of electronic part |
-
2002
- 2002-06-28 CN CNB02123194XA patent/CN1303678C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11284104A (en) * | 1998-03-27 | 1999-10-15 | Shindo Denshi Kogyo Kk | Integrated circuit package and manufacture thereof |
| JP2000294682A (en) * | 1999-04-08 | 2000-10-20 | Toshiba Corp | Semiconductor device |
| JP2000332167A (en) * | 1999-05-25 | 2000-11-30 | Denso Corp | Mounting method of electronic part |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1466199A (en) | 2004-01-07 |
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Granted publication date: 20070307 |