CN108376674A - A kind of anti-layered warping structure of VDMOS power devices plastic packaging - Google Patents
A kind of anti-layered warping structure of VDMOS power devices plastic packaging Download PDFInfo
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- CN108376674A CN108376674A CN201810419400.4A CN201810419400A CN108376674A CN 108376674 A CN108376674 A CN 108376674A CN 201810419400 A CN201810419400 A CN 201810419400A CN 108376674 A CN108376674 A CN 108376674A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 48
- 239000004033 plastic Substances 0.000 title claims abstract description 36
- 229920003023 plastic Polymers 0.000 title claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 286
- 229910052751 metal Inorganic materials 0.000 claims abstract description 286
- 239000000758 substrate Substances 0.000 claims abstract description 106
- 239000000463 material Substances 0.000 claims description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 abstract description 11
- 238000013461 design Methods 0.000 abstract description 2
- 238000012545 processing Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 15
- 238000007747 plating Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 230000035882 stress Effects 0.000 description 6
- 238000003466 welding Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000005336 cracking Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000003384 imaging method Methods 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004587 chromatography analysis Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000010148 water-pollination Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A kind of anti-layered warping structure of VDMOS power devices plastic packaging.It is related to technical field of electronic encapsulation more particularly to VDMOS power devices plastic packaging with anti-layered warping structure.It is simple in structure to provide one kind, facilitates processing, improves the anti-layered warping structure of VDMOS power device plastic packagings of product quality.Including rectangular substrate, rectangular dies adhesion zone is equipped among the top surface of the substrate, substrate top surface quadrangle end is respectively equipped with the first metal pillar group, it is respectively equipped with the second metal pillar group on the outside of the die bonding area quadrangle of substrate top surface, substrate bottom surface is equipped with third metal pillar group and the 4th metal pillar group, and plastic-sealed body is covered in the substrate and the first ~ tetra- metal pillar group；The first metal pillar group is located at the surface of third metal pillar group, and the second metal pillar group is located at the surface of the 4th metal pillar group.The anti-layered warping structure design of VDMOS power devices of the present invention is unique, simple in structure, easy to make.
Description
Technical field
The present invention relates to technical field of electronic encapsulation more particularly to the anti-layered warping structures of VDMOS power devices plastic packaging.
Background technology
With VDMOS（Vertical double diffused metal-oxide semiconductor field effect transistor）It is partly led for the power of Typical Representative
Body device is the mainstream component of field of power electronics, is had a wide range of applications in fields such as high power switch, power conversions.Modeling
Material encapsulation is one of the predominant package form of current VDMOS power devices in the advantage of cost, technique etc. because of it.But plastics
The non-airtight of encapsulation can bring potential integrity problem, and packaging body layering is exactly a kind of failure mode of one of the most common.
Plastic packaging body layering refer to be happened at plastic-sealed body and packaging frame or substrate, chip, pin bonding area interface cracking and
Warping phenomenon.The layering of plastic-sealed body can lead to the damaged wherein fracture of metal interconnection, passivation layer, soldered ball offset and ambiance
Intrusion and make chip and packaging frame material corrosion etc., and thus bring the degeneration and failure of VDMOS chip electric property.
Studies have shown that plastic packaging body is coefficient of thermal expansion difference institute between different materials in packaging body the main reason for layering
Wet stress effect coefficient result of the steam adsorbed in caused thermal stress effects and packaging body under high/low-temperature impact.
Plastic-sealed body with relatively large coefficient of thermal expansion, the thermal mismatching with packaging frame and chip are easy to produce under warm varying load
Heat mechanical stress, and the hydrophily and porosity of high polymer plastic-sealed body so that packaging body easily absorbs the steam in environment,
During high-temperature soldering, the effect for the wet stressed bond thermal and mechanical stress that moisture expantion generates makes packaging body be layered.Into one
Step studies have shown that moisture content is the external cause of plastic-sealed body cracking, and packaging frame, chip, bonding agent in plastic package structure and
Existing thermal mismatch stress is then the decisive internal cause for causing plastic-sealed body to be layered between plastic-sealed body.（Wang Xiaozhen etc., military plastic packaging electricity
Road is layered and reliability method research, electronics manufacturing engineering, Vol.37, No.6, pp.316-329, and 2016；Li Lanxia, surface peace
Problem of Cracking and its countermeasure caused by dress plastic-sealed body hygroscopicity, electronics and encapsulation, Vol.5, No.10, pp.14-16,2005）
The layering failure of power semiconductor plastic-sealed body take place mostly in the bonding part of plastic-sealed body and packaging frame, plastic-sealed body with
The bonding part of chip surface and the abutting edge of plastic-sealed body and pin bonding area, are particularly present in the tip of packaging frame, chip
Edge.During electrical over-stress (EOS) or reflow welding, plastic-sealed body undergoes multiple thermal cycle, due to plastic-sealed body, substrate and core
The difference of the coefficient of thermal expansion of sheet material, generates shearforce between plastic-sealed body and chip or chip substrate；Cause between them
The degree of interface debonding, layering can be because of moisture content level in the strength difference of thermal stress, the difference of plastic package structure and encapsulation
It is different and change.The source of thermal stress is also depended on simultaneously, in the case that electrical over-stress (EOS) acts on, heat source is generated by chip,
And during reflow welding, heat source is applied by outside, and two kinds of heat sources can lead to different interface debonding in encapsulation, produced by the former
Layering mostly between chip and packaging body, layering caused by the latter mostly packaging body and substrate or lead frame it
Between.（Gu Guanhua, the encapsulation chromatographic analysis of plastic device is carried out with scanning acoustic microscope, and electronic product reliability is tried with environment
It tests, the 2nd phase, pp.14-16,2004）
The approaches and methods for conventionally reducing plastic package structure layered warping have：1. the improvement of material is selected high moisture-proof, low is answered
The high-purity plastic-sealed body of power, high thermoconductivity, and be properly added inorganic filler and stress suction release agent；2. structure is improved, increase envelope
Frame up frame, chip adhesive surface roughness, to increase the binding force between plastic-sealed body and packaging frame, between chip；③
Sufficient plasma cleaning is carried out to the semi-finished product before encapsulation, enhances the interface binding power, etc. of plastic-sealed body and packaging frame.
（The segmentation of Xu little Ping, plastic packaging power device are inquired into, electronics manufacturing engineering, and 2016, Vol37,2, pp.103-105；Li Lan
Chivalrous, problem of Cracking and its countermeasure caused by plastic-sealed body hygroscopicity, electronics and encapsulation, Vol.5, No.10, pp.14- are installed in surface
16,2005）But since power semiconductor plastic-sealed body is layered the complexity of genesis mechanism and is layered initial generation position
Randomness, current methods can only prevent the generation of plastic package structure layered warping phenomenon to a certain extent.
Invention content
The present invention facilitates processing, improves the VDMOS work(of product quality in view of the above problems, provide a kind of simple in structure
The anti-layered warping structure of rate device plastic packaging.
The technical scheme is that：Including rectangular substrate, rectangular dies adhesion zone is equipped among the top surface of the substrate,
Substrate top surface quadrangle end is respectively equipped with the first metal pillar group, and second is respectively equipped on the outside of the die bonding area quadrangle of substrate top surface
Metal pillar group, substrate bottom surface are equipped with third metal pillar group and the 4th metal pillar group, and the substrate and the first ~ tetra- metal are convex
It is covered with plastic-sealed body in column group；
The first metal pillar group is located at the surface of third metal pillar group, and it is convex that the second metal pillar group is located at the 4th metal
The surface of column group；
The first ~ tetra- metal pillar group includes several metal pillars, wherein is equipped with spacing between metal pillar two-by-two.
Several metal pillars in the first metal pillar group are arranged into several metal pillar row one, several metal pillars
Row one are arranged in order and length gradually increases, and the spacing between metal pillar row one is identical two-by-two；
Several metal pillar row one constitute isosceles right triangle, and two right-angle sides of the first metal pillar group are respectively parallel to
The angle end both sides of substrate.
Several metal pillars in the second metal pillar group are arranged into several metal pillar row two, several metal pillars
Two row are arranged in order and length gradually increases, and the spacing between metal pillar row two is identical two-by-two；
Several metal pillar row two constitute isosceles right triangle, and two right-angle sides of the second metal pillar group are respectively parallel to
The angle end both sides in die bonding area.
Several metal pillars in the third metal pillar group form at least two rectangular metal pillar rings one, Ge Geju
For the four of shape metal pillar ring one when being respectively parallel to the four of substrate, each rectangular metal pillar ring one is successively embedding from inside to outside
It covers, the spacing between adjacent rectangle metal pillar ring one is identical；
Several metal pillars in the 4th metal pillar group form at least two rectangular metal pillar rings two, each rectangle gold
For the four of category pillar ring two when being respectively parallel to the four of die bonding area, each rectangular metal pillar ring two is successively embedding from inside to outside
It covers, the spacing between adjacent rectangle metal pillar ring two is identical.
The height of metal pillar in top surface quadrangle end the first metal pillar group of the substrate is covering substrate top surface
The 1/3~1/2 of plastic packaging body thickness.
The height of metal pillar on the outside of the quadrangle in the die bonding area of the substrate in the second metal pillar group is not higher than
It is bonded in the height of the chip top surface on substrate.
The height of metal pillar in third and fourth metal pillar group of the bottom surface of the substrate is to cover the modeling of substrate bottom surface
Seal the 1/4~1/3 of the thickness of body.
The metal pillar is cylinder.
The diameter of the metal pillar and the ratio of height are less than 1/2.
The material identical of the material and substrate of the metal pillar, material are copper or copper alloy.
The present invention at substrate top surface quadrangle end by being respectively equipped with the first metal pillar group, the die bonding area of substrate top surface
The second metal pillar group is respectively equipped on the outside of quadrangle, substrate bottom surface is equipped with third metal pillar group and the 4th metal pillar group, modeling
Feng Shi is embedded in coated in the plastic packaging material on substrate among the spacing of each metal pillar, is increased between plastic-sealed body and package substrate
Bonding force, while the metal pillar in embedded plastic-sealed body can effectively export the heat assembled in plastic-sealed body, when VDMOS power devices
When part bears certain temperature cycles and power cycle in welding or the course of work, it can effectively slow down plastic-sealed body and encapsulation base
The generation and expansion of lamination between plate improve the reliability of VDMOS power devices, reduce the crash rate of device.This hair
The anti-layered warping structure design of bright VDMOS power devices is unique, simple in structure, easy to make.
Description of the drawings
Fig. 1 is the top surface structure schematic diagram of anti-layered warping structure in the present invention；
Fig. 2 is the bottom surface structure schematic diagram of anti-layered warping structure in the present invention；
Fig. 3 is the side view of anti-layered warping structure in the present invention；
Fig. 4 is the plastic packaging substrate higher slice warpage situation schematic diagram for not using the anti-layered warping structure of the present invention, on the upside of chip and
It is the situation for layering cavity occur on the left of substrate, is the case where warpage gap occur on the right side of substrate；
Fig. 5 is using the anti-layered warping effect structure schematic diagram of the present invention, the layered warping phenomenon Yin Benfa of plastic packaging substrate interface
The presence of several metal pillars in bright and substantially be suppressed；
Fig. 6 is the TO-247 type lead frame top surface structure schematic diagrames for including anti-layered warping structure in the embodiment of the present invention；
In figure 1 be substrate, 11 be die bonding area,
It is the second metal pillar group, 2-3 be third metal pillar group, 2-4 is the 4th metal that 2-1, which is the first metal pillar group, 2-2,
Pillar group, 21 are that the first metal pillar arranges, 22 be that the second metal pillar arranges, 23 be that third metal pillar arranges, 24 be rectangular metal
Pillar ring one, 25 be rectangular metal pillar ring two, 26 be metal pillar, 27 be top metal pillar,
3 be plastic-sealed body, 4 be layering cavity, 5 be warpage gap, 6 be chip, 7 be welding layer, 8 be TO-247 types lead frame,
81 be chassis base.
Specific implementation mode
The present invention as shown in figures 1 to 6, including rectangular substrate 1, substrate top surface quadrangle end, substrate top surface die bonding area
It is convex that 11 4 jiaos of outsides and substrate bottom surface are respectively equipped with the first metal pillar group 2-1, the second metal pillar group 2-2, third metal
Column group 2-3 and the 4th metal pillar group 2-4 is covered with plastic-sealed body 3 in the substrate 1 and each metal pillar group；
Each metal pillar group includes several metal pillars 26, if several metal pillars 26 in each metal pillar group are arranged into
Dry metal pillar arranges, and spacing is equipped between the pillar of metal two-by-two 26 in each metal pillar row.
Several metal pillars row in the first metal pillar group 2-1 at substrate top surface quadrangle end are arranged in order and length
It gradually increases, constitutes the metal pillar array of isosceles right triangle, two right-angle sides of metal pillar group are respectively parallel to substrate 1
Angle end both sides, the spacing between each metal pillar row is identical, between the adjacent metal pillar 26 in each metal pillar row
Spacing it is identical.
Isosceles right triangle with the quadrangle similar shape of substrate, uniformly fills the substrate top surface four for being also easy to produce layered warping just
Angular zone ensures substrate and the good adhesive effect of packaging body.
Several metal pillars row in the second metal pillar group 2-2 on the outside of 11 4 jiaos of substrate top surface die bonding area
It is arranged in order and length gradually increases, constitute the metal pillar array of isosceles right triangle, two right-angle sides of metal pillar group
The angle end both sides in die bonding area 11 are respectively parallel to, the spacing between each metal pillar row is identical, each metal pillar row
In adjacent metal pillar 26 between spacing it is identical.
Several metal pillars in the third metal pillar group 2-3 form at least two rectangular metal pillar rings 1,
The four of each rectangular metal pillar ring one when being respectively parallel to the four of substrate, each rectangular metal pillar ring one from inside to outside by
Layer is nested, and the spacing between adjacent rectangle metal pillar ring one is identical；
Several metal pillars in the 4th metal pillar group 2-4 form at least two rectangular metal pillar rings 2 25, each
For the four of rectangular metal pillar ring two when being respectively parallel to the four of die bonding area, each rectangular metal pillar ring two is from inside to outside
Successively nested, the spacing between adjacent rectangle metal pillar ring two is identical.
It is separately included positioned at the third metal pillar group 2-3 and the 4th metal pillar group 2-4 of substrate bottom surface several by four
Metal pillar arranges the rectangular metal pillar ring of end to end composition to differ in size（It is respectively：It is in third metal pillar group
Rectangular metal pillar ring 1 is rectangular metal pillar ring 2 25 in the 4th metal pillar group）, each rectangular metal pillar ring
Four when being respectively parallel to the four of substrate 1, each rectangular metal pillar ring from small to large, it is successively nested from inside to outside, described the
Three metal pillar group 2-3 are located at the outside of substrate bottom surface, institute opposite with the first metal pillar group 2-1 at substrate top surface quadrangle end
The middle part that the 4th metal pillar group 2-4 is located at substrate bottom surface is stated, with the second gold medal on the outside of 11 4 jiaos of substrate top surface die bonding area
Category pillar group 2-2 is opposite, and the spacing between each rectangular metal pillar ring in each metal pillar group is identical, Ge Geju
The spacing between each metal pillar 26 in shape metal pillar ring is identical.
The height of each metal pillar 26 in the first metal pillar group 2-1 of substrate top surface quadrangle end is covering substrate
The 1/3~1/2 of 3 thickness of plastic-sealed body of top surface.
Each metal pillar 26 on the outside of the quadrangle in the die bonding area 11 of the substrate in the second metal pillar group 2-2 is not
Higher than the top surface of the chip 6 of bonding on substrate 1.
The substrate bottom surface third metal pillar group 2-3 and each metal pillar 26 in the 4th metal pillar group 2-4
Height is the 1/4~1/3 of the thickness of the plastic-sealed body 3 of covering substrate bottom surface.
The metal pillar 26 is cylinder.
The diameter of the metal pillar 26 and the ratio of height are less than 1/2.
The material identical of the material and substrate 1 of the metal pillar 26, material are copper or copper alloy.
In concrete application, the first metal pillar group 2-1 and the second metal pillar group 2-2 separately include several metals
Pillar 26 is arranged into several metal pillars row（That is metal pillar row one and metal pillar row two）, each metal pillar row institute
Including metal pillar number differ, length is also unequal, each metal pillar arrange by it metal pillar number for being included or
Length is arranged in order, and the metal pillar array of an isosceles right triangle is constituted, with place substrate angle or die bonding area
The shape at angle is consistent；
Several metal pillars arrange：First metal pillar row 21 only include top metal pillar 27, the second metal pillar row
22 are located at the inside of top metal pillar 27, including 2 metal pillars 26, third metal pillar row 23 are located at the second metal pillar
The inside of row 22, including 3 metal pillars 26 ... ..., the n-th metal pillar row are located at the inside of the (n-1)th metal pillar row, including
N metal pillar 26；N >=3, n are positive integer；
Each metal pillar 26 in second metal pillar row 22 is distributed relative to 27 crossed-symmetrical of top metal pillar, third gold
Belong to each metal pillar 26 in pillar row 23 relative to each 26 crossed-symmetrical of metal pillar in the second metal pillar row 22
Distribution ... ..., each metal pillar 26 during the n-th metal pillar arranges are convex relative to each metal in the (n-1)th metal pillar row
26 crossed-symmetrical of column is distributed；
Top metal pillar 27, the first metal pillar row 21, the second metal pillar row 22 ..., the n-th metal pillar row between
Spacing is equal；
The spacing between each metal pillar 26 in each metal pillar row is equal.
The third metal pillar group 2-3 and the 4th metal pillar group 2-4 positioned at substrate bottom surface separately includes several by 4
A metal pillar arranges the rectangular metal pillar ring of end to end composition to differ in size, four sides point of each rectangular metal pillar ring
Be not parallel to four sides of substrate 1, each rectangular metal pillar ring from small to large, it is successively nested from inside to outside；
Metal in each rectangular metal pillar ring of the third metal pillar group 2-3 or the 4th metal pillar group 2-4 is convex
Column 26 intersects symmetrical；
The third metal pillar group 2-3 is located at the outside of 1 bottom surface of substrate, the first metal pillar with 1 top surface quadrangle end of substrate
Group 2-1 is opposite；
The 4th metal pillar group 2-4 is located at the middle part of 1 bottom surface of substrate, with 11 4 jiaos of 1 top surface die bonding area of substrate outside
The second metal pillar group 2-2 it is opposite；
The spacing between each rectangular metal pillar ring in each metal pillar group is identical, each rectangular metal pillar ring
In each metal pillar 26 between spacing it is identical.
The operation principle of the present invention：
When carrying out VDMOS 6 plastic packagings of power device chip using common package substrate or packaging frame, chip 6 passes through welding layer 7
On substrate 1, the plastic-sealed body being covered on substrate or frame is only bonding with the surface of substrate or frame, due to plastic packaging layer for connection
Interface between substrate or frame belongs to glued construction, and two on interface kind material is combined by molecular force, rather than
It dissolves each other, the form of counterdiffusion or chemical combination, thus binding force is not strong.In this way, it is appearance layering cavity 4 to generate left side in Fig. 4
Situation, right side are the case where warpage gap 5 occur.
And when using the package substrate comprising anti-layered warping structure of the invention or frame progress VDMOS power device modelings
Feng Shi, as shown in figure 5, when coating plastic-sealed body on substrate 1 or frame, coated in the plastic-sealed body on substrate or chassis base 81
Among the gap of embedded each metal pillar, plastic-sealed body is not only closed with the surface station of substrate or chassis base, and with each gold
The side for belonging to pillar also forms more close combination, and due to each metal pillar in the anti-layered warping structure of the present invention
Elongated profile, specific area is larger, thus generally, plastic-sealed body and the substrate or frame in the anti-layered warping structure of the present invention
The binding force of frame bottom plate is stronger.
It is wherein produced on the metal pillar group at 1 top surface quadrangle end of substrate, the height of metal pillar 26 is set as plastic-sealed body 3
The 1/3~1/2 of thickness is longest metal pillar in each metal pillar group, most strong with the binding force of plastic-sealed body 3, is made in base
In the case that plate top surface is there are a variety of different thermal expansion coefficient material boundary such as substrate 1, plastic-sealed body 3, chip 6, avoids or reduce
Layered warping between plastic-sealed body 3 and substrate 1 or plastic-sealed body 3 and chip 6；
And it is wherein produced on the metal pillar group on the outside of 11 4 jiaos of substrate top surface die bonding area, the height of metal pillar 26 is set
Not higher than the top surface for pasting chip 6 on substrate 1, the metal pillar 26 of protrusion to be avoided to be contacted with the bonding wire of chip 6,
Lead to the electric short circuit of chip 6；
And wherein in the third of 1 bottom surface of substrate, the 4th metal pillar group, because there is only the letters of substrate 1 and plastic-sealed body 3 for substrate bottom surface
Single boundary, the height of metal pillar 26 are set as the 1/4~1/3 of the thickness of plastic-sealed body 3, and between being arranged between metal pillar 26
Away from reducing structure while avoiding or reducing the layered warping between plastic-sealed body 3 and substrate 1 more than above-mentioned two situations
Complexity.
Thus, when the package substrate or frame of anti-layered warping structure using the present invention carry out the VDMOS power of plastic packaging
When device bears certain temperature cycles and power cycle in welding or the course of work, if because of thermal stress or wet stress
Occur initial crack or bubble in plastic-sealed body, stronger tangential viscous force prevents plastic packaging between plastic-sealed body and each metal pillar
Separation between body and substrate or chassis base, meanwhile, each metal pillar being embedded in plastic-sealed body is led because of its excellent metal
It is hot, gathering for heat in the poor plastic-sealed body of thermal conductivity is reduced, plastic-sealed body layered warping can be prevented to a certain extent
Generation or expansion.
The present invention implementation method be：
Preferably, the distributed architecture based on above-mentioned metal pillar, in the preparation process of package substrate or frame, using mold or
The method of person's punching press is completed at the same time the making of each metal pillar on substrate or chassis base；
Alternatively, the preparation method of the anti-layered warping structure on above-mentioned 8 substrate of TO-247 types lead frame, includes the following steps：
(1) packaging frame is cleaned；
(2) packaging frame bottom plate dual coating photoresist and exposure imaging, go the photoetching of metal pillar position unless each
Glue；
(3) sputtering metal membrane；
(4) remove photoresist, together with the metal film on removal photoresist, obtain the plating seed layer of each metal pillar；
(5) plate top surface coats thick photoresist glue-line, the height phase of bondline thickness and metal pillar in the first metal pillar group again
Together, exposure imaging, removes the photoresist of each metal pillar position in the first metal pillar group, and keeps above-mentioned metal convex
Column plating seed layer is exposed；
(6) it is electroplated, fills the cavity above the plating seed layer on above-mentioned thick photoresist glue-line；
(7) remove photoresist, obtain each metal pillar of the first metal pillar group；
(8) plate top surface coats thick photoresist glue-line, the height phase of bondline thickness and metal pillar in the second metal pillar group again
Together, exposure imaging, removes the photoresist of each metal pillar position in the second metal pillar group, and keeps above-mentioned metal convex
Column plating seed layer is exposed；
(9) it is electroplated, fills the cavity above the plating seed layer on above-mentioned thick photoresist glue-line；
(10) remove photoresist, obtain each metal pillar of the second metal pillar group；
(11) bottom plate bottom surface coats thick photoresist glue-line again, bondline thickness in third metal pillar group and the 4th metal pillar group
The height of metal pillar is identical, exposure imaging, removes third metal pillar group and each metal pillar institute of the 4th metal pillar group
Photoresist at position, and keep above-mentioned metal pillar plating seed layer exposed；
(12) it is electroplated, fills the cavity above the plating seed layer on above-mentioned thick photoresist glue-line；
(13) remove photoresist, obtain each metal pillar of third metal pillar group and the 4th metal pillar group.
Claims (10)
1. a kind of anti-layered warping structure of VDMOS power devices plastic packaging, which is characterized in that including rectangular substrate, the substrate
Rectangular dies adhesion zone is equipped among top surface, substrate top surface quadrangle end is respectively equipped with the first metal pillar group, the core of substrate top surface
The second metal pillar group is respectively equipped on the outside of the quadrangle of piece adhesion zone, substrate bottom surface is equipped with third metal pillar group and the 4th metal is convex
It is covered with plastic-sealed body in column group, the substrate and the first ~ tetra- metal pillar group；
The first metal pillar group is located at the surface of third metal pillar group, and it is convex that the second metal pillar group is located at the 4th metal
The surface of column group；
The first ~ tetra- metal pillar group includes several metal pillars, wherein is equipped with spacing between metal pillar two-by-two.
2. the anti-layered warping structure of a kind of VDMOS power devices plastic packaging according to claim 1, which is characterized in that described
Several metal pillars in first metal pillar group are arranged into several metal pillar row one, and several metal pillar row one are arranged in order
And length gradually increases, the spacing between metal pillar row one is identical two-by-two；
Several metal pillar row one constitute isosceles right triangle, and two right-angle sides of the first metal pillar group are respectively parallel to
The angle end both sides of substrate.
3. the anti-layered warping structure of a kind of VDMOS power devices plastic packaging according to claim 1, which is characterized in that described
Several metal pillars in second metal pillar group are arranged into several metal pillar row two, and several row of metal pillar two are arranged in order
And length gradually increases, the spacing between metal pillar row two is identical two-by-two；
Several metal pillar row two constitute isosceles right triangle, and two right-angle sides of the second metal pillar group are respectively parallel to
The angle end both sides in die bonding area.
4. the anti-layered warping structure of a kind of VDMOS power devices plastic packaging according to claim 1, which is characterized in that described
Several metal pillars in third metal pillar group form at least two rectangular metal pillar rings one, each rectangular metal pillar ring
For the four of one when being respectively parallel to the four of substrate, each rectangular metal pillar ring one is successively nested from inside to outside, adjacent rectangle gold
The spacing belonged between pillar ring one is identical；
Several metal pillars in the 4th metal pillar group form at least two rectangular metal pillar rings two, each rectangle gold
For the four of category pillar ring two when being respectively parallel to the four of die bonding area, each rectangular metal pillar ring two is successively embedding from inside to outside
It covers, the spacing between adjacent rectangle metal pillar ring two is identical.
5. the anti-layered warping structure of a kind of VDMOS power devices plastic packaging according to claim 1 or 2, which is characterized in that institute
The height for stating the metal pillar in top surface quadrangle end the first metal pillar group of substrate is to cover the plastic packaging body thickness of substrate top surface
1/3~1/2.
6. the anti-layered warping structure of a kind of VDMOS power devices plastic packaging according to claim 1 or 3, which is characterized in that institute
The height of the metal pillar on the outside of the quadrangle in the die bonding area of substrate in the second metal pillar group is stated not higher than being bonded in substrate
On chip top surface height.
7. the anti-layered warping structure of a kind of VDMOS power devices plastic packaging according to claim 1 or 4, which is characterized in that institute
The height for stating the metal pillar in third and fourth metal pillar group of the bottom surface of substrate is the thickness for the plastic-sealed body for covering substrate bottom surface
1/4~1/3.
8. the anti-layered warping structure of a kind of VDMOS power devices plastic packaging according to claim 1, which is characterized in that described
Metal pillar is cylinder.
9. the anti-layered warping structure of a kind of VDMOS power devices plastic packaging according to claim 8, which is characterized in that described
The diameter of metal pillar and the ratio of height are less than 1/2.
10. the anti-layered warping structure of a kind of VDMOS power devices plastic packaging according to claim 1, which is characterized in that described
The material of metal pillar and the material identical of substrate, material are copper or copper alloy.
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| CN201810419400.4A CN108376674B (en) | 2018-05-04 | 2018-05-04 | VDMOS power device plastic package anti-layering warping structure |
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| CN108376674B (en) | 2024-03-08 |
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