CN100464416C - Method for packing against semiconductor plastic sealer internal device lamination - Google Patents
Method for packing against semiconductor plastic sealer internal device lamination Download PDFInfo
- Publication number
- CN100464416C CN100464416C CNB2007100221413A CN200710022141A CN100464416C CN 100464416 C CN100464416 C CN 100464416C CN B2007100221413 A CNB2007100221413 A CN B2007100221413A CN 200710022141 A CN200710022141 A CN 200710022141A CN 100464416 C CN100464416 C CN 100464416C
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- die
- attach area
- semiconductor plastic
- molding compound
- making
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A packing method to avoid delamination of the elements in semi-conducting package includes: making a groove or several ones in parallel/crossing on the surface of the lead frame jointed to the epoxy resin package; plating on the surface with metal layer; coarsening the surface.
Description
Technical field:
The present invention relates to a kind of semiconductor plastic packaging body components and parts, especially relate to a kind of method for packing that prevents component-device sub-layer of semiconductor plastic package.Belong to the semiconductor packaging field.
Background technology:
The packaging body that plastic semiconductor encapsulation components and parts adopt multiple material to combine substantially, material wherein mainly contains die-attach area, epoxy resin, wire, polymer binder, the coat of metal etc.But the variation of factors such as different material can Yin Wendu, humidity, vibration and cause easily and between different material, produce layering; Especially in hot environment, because the thermal coefficient of expansion of different material is different, so can be in the horizontal direction or vertical direction produce in various degree draw, push away stress, and then between different material, produce layering (shown in Fig. 4 (a), 5 (a), 6 (a)), finally cause problems such as the functional defect of plastic semiconductor encapsulation components and parts or early failure.
Summary of the invention:
The objective of the invention is to overcome above-mentioned deficiency, a kind of method for packing that prevents component-device sub-layer of semiconductor plastic package is provided.
Purpose of the present invention can be realized by following two schemes:
Scheme one:
In semiconductor plastic packaging body, producing the one or more parallel or/and groove that intersects with the surface of the die-attach area of epoxy molding compound combination, the surface local in the die-attach area that combines with epoxy molding compound plates metal level simultaneously.Its making can be adopted machinery or etching and processing or mode such as strike off realizes the making of groove; Adopt modes such as plating, deposition, steaming gold, sputter to realize that the part plates metal level.Groove has increased contact area and the adhesion between interior die-attach area of plastic-sealed body and epoxy resin, can reduce the shear stress that the two is produced because of the different material expansion on X and Y in-plane.Increase the surface area of leadframe metal ground relatively by the mode of partially plating gold genus layer on the surface of die-attach area: can reduce the medium between die-attach area and epoxy resin on the one hand; On the other hand, metal substrate generally adopts copper material, and the coat of metal often adopts gold, silver etc., because the bonding force of copper and epoxy resin will be better than Jin Heyin greatly, so the method for partially plating gold genus layer has also increased the bonding force between die-attach area and epoxy resin indirectly.Therefore, more than being used in combination can make between die-attach area and the epoxy resin and stinging tightlyer mutually of two kinds of schemes, thereby play the effect (as Fig. 4,5) that prevents or reduce layering.
Scheme two:
Scheme two is on the basis of scheme one, makes matsurface on the surface of the die-attach area that combines with epoxy molding compound.Its making can be adopted machinery or etching and processing or mode such as strike off realizes.By make on the top layer of die-attach area that matsurface increases and epoxy resin between bonded area, reduce die-attach area that factor such as Yin Lali causes and the sliding force between the epoxy resin.Therefore, more than being used in combination can make between die-attach area and the epoxy resin and stinging tightlyer mutually of three kinds of schemes, thereby play the effect (as Fig. 6) that prevents or reduce layering.
Plastic semiconductor of the present invention encapsulates the improvement of components and parts lamination problem, helps improving the heat-sinking capability and the thermal stress resistance changing capability of components and parts, and the sealing of product, functional parameter and reliability all are guaranteed.
Description of drawings
Fig. 1 is embodiments of the invention 1 schematic diagrames.
Fig. 2 is embodiments of the invention 2 schematic diagrames.
Fig. 3 is a typical intact plastic-sealed body structural representation of the present invention.
Fig. 4 (a) and (b), (c) are for making the stressed comparison diagram on groove front and back die-attach area and epoxy molding compound composition surface.
Fig. 5 (a) and (b) are for making the stressed comparison diagram on localized metallic layer front and back die-attach area and epoxy molding compound composition surface.
Fig. 6 (a) and (b) are for making the stressed comparison diagram on matsurface front and back die-attach area and epoxy molding compound composition surface.
Among the figure: die-attach area 1, epoxy molding compound 2, groove 3, localized metallic layer 4, matsurface 5, wire 6, silicon material chip 7.
Embodiment:
Embodiment 1:
Referring to Fig. 1, the present invention prevents the method for packing of component-device sub-layer of semiconductor plastic package, in semiconductor plastic packaging body, producing the one or more parallel or/and groove 3 that intersects with the surface of the die-attach area 1 of epoxy molding compound 2 combinations, the surface local in the die-attach area 1 that combines with epoxy molding compound 2 plates metal level 4 simultaneously.
Embodiment 2:
Referring to Fig. 2, embodiment 2 is on the basis of embodiment 1, makes matsurface 5 on the surface of the die-attach area 1 that combines with epoxy molding compound 2.
Referring to Fig. 3, Fig. 3 is a typical intact plastic-sealed body structural representation.
Referring to Fig. 4,5,6, Fig. 4,5,6 for the present invention improve before and after the stressed comparison diagram on die-attach area and epoxy molding compound composition surface.
Claims (2)
1. method for packing that prevents component-device sub-layer of semiconductor plastic package, it is characterized in that: in semiconductor plastic packaging body, producing the one or more parallel or/and groove that intersects (3) with the surface of the die-attach area (1) of epoxy molding compound (2) combination, the surface local in the die-attach area (1) that combines with epoxy molding compound (2) plates metal level (4) simultaneously; Surface in the die-attach area (1) that combines with epoxy molding compound (2) makes matsurface (5); The making of described groove (3) is to adopt machinery or etching and processing mode to realize; The making of described metal level (4) is to adopt depositional mode to realize; The making of described matsurface (5) is to adopt machinery or etching and processing mode to realize.
2. a kind of method for packing that prevents component-device sub-layer of semiconductor plastic package according to claim 1 is characterized in that: described deposition is to electroplate or steaming gold or sputter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100221413A CN100464416C (en) | 2007-04-29 | 2007-04-29 | Method for packing against semiconductor plastic sealer internal device lamination |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100221413A CN100464416C (en) | 2007-04-29 | 2007-04-29 | Method for packing against semiconductor plastic sealer internal device lamination |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101075597A CN101075597A (en) | 2007-11-21 |
| CN100464416C true CN100464416C (en) | 2009-02-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007100221413A Active CN100464416C (en) | 2007-04-29 | 2007-04-29 | Method for packing against semiconductor plastic sealer internal device lamination |
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| Country | Link |
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| CN (1) | CN100464416C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101438826B1 (en) | 2008-06-23 | 2014-09-05 | 엘지이노텍 주식회사 | Light emitting device |
| CN102361025B (en) * | 2011-10-28 | 2012-10-03 | 深圳市气派科技有限公司 | High-density integrated circuit packaging structure, packaging method for packaging structure, and integrated circuit |
| JP6686691B2 (en) * | 2016-05-16 | 2020-04-22 | 株式会社デンソー | Electronic device |
| CN116469846A (en) * | 2023-06-05 | 2023-07-21 | 广州小鹏汽车科技有限公司 | Power semiconductor module and packaging method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1116770A (en) * | 1994-06-06 | 1996-02-14 | 摩托罗拉公司 | Method and apparatus for improving interfacial adhesion between a polymer and a metal |
| US6184064B1 (en) * | 2000-01-12 | 2001-02-06 | Micron Technology, Inc. | Semiconductor die back side surface and method of fabrication |
| CN1848420A (en) * | 2005-04-15 | 2006-10-18 | 三星Techwin株式会社 | Lead frame for semiconductor package |
| CN1851914A (en) * | 2006-05-29 | 2006-10-25 | 朱冬生 | Lead-frame and semi-conductor device with same |
| CN2893922Y (en) * | 2006-04-19 | 2007-04-25 | 宁波康强电子股份有限公司 | Improved large-power lead wire frame |
| CN201038153Y (en) * | 2007-04-29 | 2008-03-19 | 江苏长电科技股份有限公司 | Package method for preventing element lamination in semiconductor plastic package |
-
2007
- 2007-04-29 CN CNB2007100221413A patent/CN100464416C/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1116770A (en) * | 1994-06-06 | 1996-02-14 | 摩托罗拉公司 | Method and apparatus for improving interfacial adhesion between a polymer and a metal |
| US6184064B1 (en) * | 2000-01-12 | 2001-02-06 | Micron Technology, Inc. | Semiconductor die back side surface and method of fabrication |
| CN1848420A (en) * | 2005-04-15 | 2006-10-18 | 三星Techwin株式会社 | Lead frame for semiconductor package |
| CN2893922Y (en) * | 2006-04-19 | 2007-04-25 | 宁波康强电子股份有限公司 | Improved large-power lead wire frame |
| CN1851914A (en) * | 2006-05-29 | 2006-10-25 | 朱冬生 | Lead-frame and semi-conductor device with same |
| CN201038153Y (en) * | 2007-04-29 | 2008-03-19 | 江苏长电科技股份有限公司 | Package method for preventing element lamination in semiconductor plastic package |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101075597A (en) | 2007-11-21 |
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Effective date of registration: 20221115 Address after: 201201 room 111, building 1, No. 200, Jichuang Road, Pudong New Area, Shanghai Patentee after: Changdian Technology Management Co.,Ltd. Address before: 214431 No. 275 middle Binjiang Road, Jiangsu, Jiangyin Patentee before: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY Co.,Ltd. |
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