CN201048129Y - Effective packing method for improving component delamination in semiconductor plastic package - Google Patents

Effective packing method for improving component delamination in semiconductor plastic package Download PDF

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Publication number
CN201048129Y
CN201048129Y CN 200720036997 CN200720036997U CN201048129Y CN 201048129 Y CN201048129 Y CN 201048129Y CN 200720036997 CN200720036997 CN 200720036997 CN 200720036997 U CN200720036997 U CN 200720036997U CN 201048129 Y CN201048129 Y CN 201048129Y
Authority
CN
China
Prior art keywords
die
plastic package
semiconductor plastic
layer
attach area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN 200720036997
Other languages
Chinese (zh)
Inventor
梁志忠
王新潮
于燮康
茅礼卿
潘明东
陶玉娟
闻荣福
周正伟
李福寿
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JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN 200720036997 priority Critical patent/CN201048129Y/en
Application granted granted Critical
Publication of CN201048129Y publication Critical patent/CN201048129Y/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The utility model relates to an efficient packaging method for improving the lay separation of elements in a plastic semiconductor package body, and belongs to the technical field of the semiconductor packaging. The utility model is characterized in that one or a plurality of parallel or/and crossed groove(s) (3) are made on the surface of a metal lead frame (1) which is combined with epoxy powder coating material (2) in the plastic semiconductor package body, at the same time, an anchor eye (4) which can ensure that the epoxy powder coating material perforates is also made on the metal lead frame (1). The improvement of the lay separation problem of the elements in the plastic semiconductor package body of the utility model is favorable to improve the heat-emitting ability and the heat resistance variation of stresses ability of the elements, thereby better ensuring the leak tightness, the functional parameter and the reliability of products.

Description

Improve the effective packaging method of component-device sub-layer of semiconductor plastic package
Technical field:
The utility model relates to a kind of semiconductor plastic packaging body components and parts, especially relates to a kind of effective packaging method that improves component-device sub-layer of semiconductor plastic package.Belong to the semiconductor packaging field.
Background technology:
The packaging body that plastic semiconductor encapsulation components and parts adopt multiple material to combine substantially, material wherein mainly contains die-attach area, epoxy resin, wire, polymer binder, the coat of metal etc.But the variation of factors such as different material can Yin Wendu, humidity, vibration and cause easily and between different material, produce layering; Especially in hot environment, because the thermal coefficient of expansion of different material is different, so can be in the horizontal direction or vertical direction produce in various degree draw, push away stress, and then between different material, produce layering (shown in Fig. 6 (a), 7 (a), 8 (a), 9 (a)), finally cause problems such as the functional defect of plastic semiconductor encapsulation components and parts or early failure.
Summary of the invention:
The purpose of this utility model is to overcome above-mentioned deficiency, and a kind of effective packaging method that can improve component-device sub-layer of semiconductor plastic package is provided.
The purpose of this utility model can be realized by following four schemes:
Scheme one:
In semiconductor plastic packaging body, producing one or more parallel or/and the groove that intersects is produced the anchor hole that can make epoxy molding compound run through usefulness simultaneously on die-attach area with the surface of the die-attach area of epoxy molding compound combination.Groove and anchor hole are made and can be adopted machinery or etching and processing or mode such as strike off realizes.Being used in combination of groove and anchor hole can increase contact area and the adhesion between die-attach area and epoxy resin in the plastic-sealed body greatly.Groove can reduce the two shear stress that is produced because of the different material expansion on X and Y in-plane, anchor hole then can reduce the two stress on vertical (Z axle) direction.Therefore, more than being used in combination to make between die-attach area and the epoxy resin and stinging tightlyer mutually of two kinds of schemes from " on the solid ", thereby play the effect (as Fig. 6,7) that prevents or reduce layering.
Scheme two:
Scheme two is on the basis of scheme one, plates metal level at the surface local of the die-attach area that combines with epoxy molding compound.Its making can be adopted plating, deposition, the modes such as gold, sputter of steaming realize.Increase the surface area of leadframe metal ground relatively by the mode of partially plating gold genus layer on the surface of die-attach area: can reduce the medium between die-attach area and epoxy resin on the one hand; On the other hand, metal substrate generally adopts copper material, and the coat of metal often adopts gold, silver etc., because the bonding force of copper and epoxy resin will be better than Jin Heyin greatly, so the method for partially plating gold genus layer has also increased the bonding force between die-attach area and epoxy resin indirectly.Therefore, more than being used in combination can make between die-attach area and the epoxy resin and stinging tightlyer mutually of three kinds of schemes, thereby play the effect (as Fig. 8) that prevents or reduce layering.
Scheme three:
Scheme three is on the basis of scheme one, makes matsurface on the surface of the die-attach area that combines with epoxy molding compound.Its making can be adopted machinery or etching and processing or mode such as strike off realizes.By make on the top layer of die-attach area that matsurface increases and epoxy resin between bonded area, reduce die-attach area that factor such as Yin Lali causes and the sliding force between the epoxy resin.Therefore, more than being used in combination can make between die-attach area and the epoxy resin and stinging tightlyer mutually of three kinds of schemes, thereby play the effect (as Fig. 9) that prevents or reduce layering.
Scheme four,
Scheme four is on the basis of scheme two, makes matsurface on the surface of the die-attach area that combines with epoxy molding compound.More than being used in combination of four kinds of schemes, increased the bonded area between lead frame and epoxy resin, strengthened the bonding force between different material, reduced the slip probability between material, thereby played the effect that prevents or reduce layering.
The utility model plastic semiconductor encapsulates the improvement of components and parts lamination problem, helps improving the heat-sinking capability and the thermal stress resistance changing capability of components and parts, and the sealing of product, functional parameter and reliability all are guaranteed.
Description of drawings
Fig. 1 is embodiment 1 schematic diagram of the present utility model.
Fig. 2 is embodiment 2 schematic diagrames of the present utility model.
Fig. 3 is embodiment 3 schematic diagrames of the present utility model.
Fig. 4 is embodiment 4 schematic diagrames of the present utility model.
Fig. 5 is a typical intact plastic-sealed body structural representation of the present utility model.
Fig. 6 (a) and (b), (c) are for making the stressed comparison diagram on groove front and back die-attach area and epoxy molding compound composition surface.
Fig. 7 (a) and (b) are for making the stressed comparison diagram on anchor hole front and back die-attach area and epoxy molding compound composition surface.
Fig. 8 (a) and (b) are for making the stressed comparison diagram on localized metallic layer front and back die-attach area and epoxy molding compound composition surface.
Fig. 9 (a) and (b) are for making the stressed comparison diagram on matsurface front and back die-attach area and epoxy molding compound composition surface.
Among the figure: die-attach area 1, epoxy molding compound 2, groove 3, anchor hole 4, partially plating gold belongs to layer 5, matsurface 6, wire 7, silicon material chip 8.
Embodiment:
Embodiment 1:
Referring to Fig. 1, the utility model improves the effective packaging method of component-device sub-layer of semiconductor plastic package, in semiconductor plastic packaging body, producing one or more parallel with the surface of the die-attach area 1 of epoxy molding compound 2 combinations or/and the groove 3 that intersects is produced the anchor hole 4 that can make epoxy molding compound run through usefulness simultaneously on die-attach area 1.
Embodiment 2:
Referring to Fig. 2, embodiment 2 is on the basis of embodiment 1, plates metal level 5 at the surface local of the die-attach area 1 that combines with epoxy molding compound 2.
Embodiment 3:
Referring to Fig. 3, embodiment 3 is on the basis of embodiment 1, makes matsurface 6 on the surface of the die-attach area 1 that combines with epoxy molding compound 2.
Embodiment 4:
Referring to Fig. 4, embodiment 4 is on the basis of embodiment 2, makes matsurface 6 on the surface of the die-attach area 1 that combines with epoxy molding compound 2.
Referring to Fig. 5, Fig. 5 is a typical intact plastic-sealed body structural representation.
Referring to Fig. 6,7,8,9, Fig. 6,7,8,9 stressed comparison diagrams for die-attach area and epoxy molding compound composition surface before and after the utility model improvement.

Claims (7)

1. effective packaging method that improves component-device sub-layer of semiconductor plastic package, it is characterized in that: in semiconductor plastic packaging body, producing one or more parallel with the surface of the die-attach area (1) of epoxy molding compound (2) combination or/and the groove that intersects (3) is produced the anchor hole (4) that can make epoxy molding compound run through usefulness simultaneously on die-attach area (1).
2. a kind of effective packaging method that improves component-device sub-layer of semiconductor plastic package according to claim 1 is characterized in that: the surface local in the die-attach area (1) that combines with epoxy molding compound (2) plates metal level (5).
3. a kind of effective packaging method that improves component-device sub-layer of semiconductor plastic package according to claim 1 is characterized in that: the surface in the die-attach area (1) that combines with epoxy molding compound (2) makes matsurface (6).
4. a kind of effective packaging method that improves component-device sub-layer of semiconductor plastic package according to claim 2 is characterized in that: the surface in the die-attach area (1) that combines with epoxy molding compound (2) makes matsurface (6).
5. according to claim 1 or 2,3,4 described a kind of effective packaging methods that improve component-device sub-layer of semiconductor plastic package, it is characterized in that: the making of described groove (3) and anchor hole (4) is to adopt machinery or etching and processing or the mode of striking off to realize.
6. according to claim 2 or 4 described a kind of effective packaging methods that improve component-device sub-layer of semiconductor plastic package, it is characterized in that: the making of described metal level (5) is adopt to electroplate or deposition or steam gold or sputtering way realizes.
7. according to claim 3 or 4 described a kind of effective packaging methods that improve component-device sub-layer of semiconductor plastic package, it is characterized in that: the making of described matsurface (6) is to adopt machinery or etching and processing or the mode of striking off to realize.
CN 200720036997 2007-04-29 2007-04-29 Effective packing method for improving component delamination in semiconductor plastic package Expired - Lifetime CN201048129Y (en)

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Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
CN 200720036997 CN201048129Y (en) 2007-04-29 2007-04-29 Effective packing method for improving component delamination in semiconductor plastic package

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100470785C (en) * 2007-04-29 2009-03-18 江苏长电科技股份有限公司 Effective packaging method for improving component-device sub-layer of semiconductor plastic package
CN102593091A (en) * 2011-01-14 2012-07-18 丰田自动车株式会社 Semiconductor module
CN104241232A (en) * 2013-06-21 2014-12-24 矽品精密工业股份有限公司 Quad flat non-leaded package and method for fabricating the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100470785C (en) * 2007-04-29 2009-03-18 江苏长电科技股份有限公司 Effective packaging method for improving component-device sub-layer of semiconductor plastic package
CN102593091A (en) * 2011-01-14 2012-07-18 丰田自动车株式会社 Semiconductor module
US8742556B2 (en) 2011-01-14 2014-06-03 Toyota Jidosha Kabushiki Kaisha Semiconductor module
CN102593091B (en) * 2011-01-14 2014-08-20 丰田自动车株式会社 Semiconductor module
CN104241232A (en) * 2013-06-21 2014-12-24 矽品精密工业股份有限公司 Quad flat non-leaded package and method for fabricating the same
CN104241232B (en) * 2013-06-21 2017-05-17 矽品精密工业股份有限公司 Quad flat non-leaded package and method for fabricating the same

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GR01 Patent grant
CX01 Expiry of patent term

Granted publication date: 20080416

CX01 Expiry of patent term