CN201048130Y - Packing method capable of preventing component delamination in semiconductor plastic package - Google Patents

Packing method capable of preventing component delamination in semiconductor plastic package Download PDF

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Publication number
CN201048130Y
CN201048130Y CNU2007200372917U CN200720037291U CN201048130Y CN 201048130 Y CN201048130 Y CN 201048130Y CN U2007200372917 U CNU2007200372917 U CN U2007200372917U CN 200720037291 U CN200720037291 U CN 200720037291U CN 201048130 Y CN201048130 Y CN 201048130Y
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CN
China
Prior art keywords
semiconductor plastic
utility
plastic package
model
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNU2007200372917U
Other languages
Chinese (zh)
Inventor
梁志忠
王新潮
于燮康
茅礼卿
潘明东
陶玉娟
闻荣福
周正伟
李福寿
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JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CNU2007200372917U priority Critical patent/CN201048130Y/en
Application granted granted Critical
Publication of CN201048130Y publication Critical patent/CN201048130Y/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The utility model relates to a packaging method for preventing the lay separation of elements in a plastic semiconductor package body, and belongs to the technical field of the semiconductor packaging. The utility model is characterized in that a metal layer (3) is plated on a part of the surface of a metal lead frame (1) which is combined with epoxy powder coating material (2) in the plastic semiconductor package body, at the same time, a roughened surface (4) is made on the metal lead frame (1) which is combined with the epoxy powder coating material (2). The execution of the part plated metal lay (3) is realized by adopting the way of plating, depositing or steaming metal or sputtering. The execution of the roughened surface (4) is realized by adopting the way of mechanism or etching processing or doctoring and so on. The improvement of the lay separation problem of the elements in the plastic semiconductor package body of the utility model is favorable to improve the heat-emitting ability and the heat resistance variation of stresses ability of the elements, thereby better ensuring the leak tightness, the functional parameter and the reliability of products.

Description

Can prevent the method for packing of component-device sub-layer of semiconductor plastic package
Technical field:
The utility model relates to a kind of semiconductor plastic packaging body components and parts, especially relates to a kind of method for packing that can prevent component-device sub-layer of semiconductor plastic package.Belong to the semiconductor packaging field.
Background technology:
The packaging body that plastic semiconductor encapsulation components and parts adopt multiple material to combine substantially, material wherein mainly contains die-attach area, epoxy resin, wire, polymer binder, the coat of metal etc.But the variation of factors such as different material can Yin Wendu, humidity, vibration and cause easily and between different material, produce layering; Especially in hot environment, because the thermal coefficient of expansion of different material is different, so can be in the horizontal direction or vertical direction produce in various degree draw, push away stress, and then between different material, produce layering (shown in Fig. 6 (a), 7 (a), 8 (a), 9 (a)), finally cause problems such as the functional defect of plastic semiconductor encapsulation components and parts or early failure.
The purpose of this utility model is to overcome above-mentioned deficiency, and a kind of method for packing that can prevent component-device sub-layer of semiconductor plastic package is provided.
The purpose of this utility model can be realized by following scheme: a kind of method for packing that can prevent component-device sub-layer of semiconductor plastic package, it is characterized in that: in semiconductor plastic packaging body, surface local in the die-attach area that combines with epoxy molding compound plates metal level, makes matsurface on the surface of the die-attach area that combines with epoxy molding compound simultaneously.Partially plating gold belongs to can adopt plating, deposition, the modes such as gold, sputter of steaming realize; Matsurface can adopt machinery or etching and processing or mode such as strike off realizes.Increase the surface area of leadframe metal ground relatively by the mode of partially plating gold genus layer on the surface of die-attach area: can reduce the medium between die-attach area and epoxy resin on the one hand; On the other hand, metal substrate generally adopts copper material, and the coat of metal often adopts gold, silver etc., because the bonding force of copper and epoxy resin will be better than Jin Heyin greatly, so the method for partially plating gold genus layer has also increased the bonding force (as Fig. 3) between die-attach area and epoxy resin indirectly.Simultaneously by make on the top layer of die-attach area that matsurface increases and epoxy resin between bonded area, reduce die-attach area and the sliding force between the epoxy resin (as Fig. 4) that factor such as Yin Lali causes.Therefore, more than being used in combination can make between die-attach area and the epoxy resin and stinging tightlyer mutually of two kinds of schemes, thereby play the effect that prevents or reduce layering.
The utility model plastic semiconductor encapsulates the improvement of components and parts lamination problem, helps improving the heat-sinking capability and the thermal stress resistance changing capability of components and parts, and the sealing of product, functional parameter and reliability all are guaranteed.
Description of drawings
Fig. 1 is an embodiment schematic diagram of the present utility model.
Fig. 2 is a typical intact plastic-sealed body structural representation of the present utility model.
Fig. 3 (a) and (b) are for making the stressed comparison diagram on localized metallic layer front and back die-attach area and epoxy molding compound composition surface.
Fig. 4 (a) and (b) are for making the stressed comparison diagram on matsurface front and back die-attach area and epoxy molding compound composition surface.
Among the figure: die-attach area 1, epoxy molding compound 2, metal level 3, matsurface 4, wire 5, silicon material chip 6.
Embodiment:
Referring to Fig. 1, the utility model can prevent the method for packing of component-device sub-layer of semiconductor plastic package, it is in semiconductor plastic packaging body, surface local in the die-attach area 1 that combines with epoxy molding compound 2 plates metal level 3, makes matsurface 4 on the surface of the die-attach area 1 that combines with epoxy molding compound 2 simultaneously.
Referring to Fig. 2, Fig. 2 is a typical intact plastic-sealed body structural representation.
Referring to Fig. 3,4, Fig. 3,4 stressed comparison diagrams for die-attach area and epoxy molding compound composition surface before and after the utility model improvement.

Claims (3)

1. method for packing that can prevent component-device sub-layer of semiconductor plastic package, it is characterized in that: in semiconductor plastic packaging body, surface local in the die-attach area (1) that combines with epoxy molding compound (2) plates metal level (3), makes matsurface (4) on the surface of the die-attach area (1) that combines with epoxy molding compound (2) simultaneously.
2. a kind of method for packing that can prevent component-device sub-layer of semiconductor plastic package according to claim 1 is characterized in that: the making that described partially plating gold belongs to layer (3) is to adopt to electroplate or deposition or steam gold or sputtering way realizes.
3. a kind of method for packing that can prevent component-device sub-layer of semiconductor plastic package according to claim 1 and 2 is characterized in that: the making of described matsurface (4) is to adopt machinery or etching and processing or the mode of striking off to realize.
CNU2007200372917U 2007-04-29 2007-04-29 Packing method capable of preventing component delamination in semiconductor plastic package Expired - Lifetime CN201048130Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNU2007200372917U CN201048130Y (en) 2007-04-29 2007-04-29 Packing method capable of preventing component delamination in semiconductor plastic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNU2007200372917U CN201048130Y (en) 2007-04-29 2007-04-29 Packing method capable of preventing component delamination in semiconductor plastic package

Publications (1)

Publication Number Publication Date
CN201048130Y true CN201048130Y (en) 2008-04-16

Family

ID=39300722

Family Applications (1)

Application Number Title Priority Date Filing Date
CNU2007200372917U Expired - Lifetime CN201048130Y (en) 2007-04-29 2007-04-29 Packing method capable of preventing component delamination in semiconductor plastic package

Country Status (1)

Country Link
CN (1) CN201048130Y (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101814482A (en) * 2010-04-30 2010-08-25 江苏长电科技股份有限公司 Base island lead frame structure and production method thereof
CN104113978A (en) * 2013-08-23 2014-10-22 广东美的制冷设备有限公司 Aluminum-based circuit board and preparation method thereof, and electronic component full packaging

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101814482A (en) * 2010-04-30 2010-08-25 江苏长电科技股份有限公司 Base island lead frame structure and production method thereof
CN101814482B (en) * 2010-04-30 2012-04-25 江苏长电科技股份有限公司 Base island lead frame structure and production method thereof
CN104113978A (en) * 2013-08-23 2014-10-22 广东美的制冷设备有限公司 Aluminum-based circuit board and preparation method thereof, and electronic component full packaging
CN104113978B (en) * 2013-08-23 2017-06-09 广东美的制冷设备有限公司 Aluminum-based circuit board and preparation method thereof, electronic component are encapsulated entirely

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Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
AV01 Patent right actively abandoned

Effective date of abandoning: 20070429

C25 Abandonment of patent right or utility model to avoid double patenting