CN100483705C - Method against device lamination inside semiconductor plastic packer - Google Patents
Method against device lamination inside semiconductor plastic packer Download PDFInfo
- Publication number
- CN100483705C CN100483705C CNB2007100223480A CN200710022348A CN100483705C CN 100483705 C CN100483705 C CN 100483705C CN B2007100223480 A CNB2007100223480 A CN B2007100223480A CN 200710022348 A CN200710022348 A CN 200710022348A CN 100483705 C CN100483705 C CN 100483705C
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- China
- Prior art keywords
- semiconductor plastic
- die
- layer
- attach area
- molding compound
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
A packing method to avoid delamination of the elements in semi-conducting package includes: plating on the surface of the lead frame jointed to the epoxy resin package; and coarsening the surface. The plating process is by electroplate, condensate, vaporization or sputter. The coarse surface is made by machine or etching process or curage.
Description
Technical field:
The present invention relates to a kind of semiconductor plastic packaging body components and parts, especially relate to a kind of method for packing that can prevent component-device sub-layer of semiconductor plastic package.Belong to the semiconductor packaging field.
Background technology:
The packaging body that plastic semiconductor encapsulation components and parts adopt multiple material to combine substantially, material wherein mainly contains die-attach area, epoxy resin, wire, polymer binder, the coat of metal etc.But the variation of factors such as different material can Yin Wendu, humidity, vibration and cause easily and between different material, produce layering; Especially in hot environment, because the thermal coefficient of expansion of different material is different, so can be in the horizontal direction or vertical direction produce in various degree draw, push away stress, and then between different material, produce layering (shown in Fig. 6 (a), 7 (a), 8 (a), 9 (a)), finally cause problems such as the functional defect of plastic semiconductor encapsulation components and parts or early failure.
The objective of the invention is to overcome above-mentioned deficiency, a kind of method for packing that can prevent component-device sub-layer of semiconductor plastic package is provided.
Purpose of the present invention can be realized by following scheme: a kind of method for packing that can prevent component-device sub-layer of semiconductor plastic package, it is characterized in that: in semiconductor plastic packaging body, surface local in the die-attach area that combines with epoxy molding compound plates metal level, makes matsurface on the surface of the die-attach area that combines with epoxy molding compound simultaneously.Partially plating gold belongs to can adopt plating, deposition, the modes such as gold, sputter of steaming realize; Matsurface can adopt machinery or etching and processing or mode such as strike off realizes.Increase the surface area of leadframe metal ground relatively by the mode of partially plating gold genus layer on the surface of die-attach area: can reduce the medium between die-attach area and epoxy resin on the one hand; On the other hand, metal substrate generally adopts copper material, and the coat of metal often adopts gold, silver etc., because the bonding force of copper and epoxy resin will be better than Jin Heyin greatly, so the method for partially plating gold genus layer has also increased the bonding force (as Fig. 3) between die-attach area and epoxy resin indirectly.Simultaneously by make on the top layer of die-attach area that matsurface increases and epoxy resin between bonded area, reduce die-attach area and the sliding force between the epoxy resin (as Fig. 4) that factor such as Yin Lali causes.Therefore, more than being used in combination can make between die-attach area and the epoxy resin and stinging tightlyer mutually of two kinds of schemes, thereby play the effect that prevents or reduce layering.
Plastic semiconductor of the present invention encapsulates the improvement of components and parts lamination problem, helps improving the heat-sinking capability and the thermal stress resistance changing capability of components and parts, and the sealing of product, functional parameter and reliability all are guaranteed.
Description of drawings
Fig. 1 is the embodiments of the invention schematic diagram.
Fig. 2 is a typical intact plastic-sealed body structural representation of the present invention.
Fig. 3 (a) and (b) are for making the stressed comparison diagram on localized metallic layer front and back die-attach area and epoxy molding compound composition surface.
Fig. 4 (a) and (b) are for making the stressed comparison diagram on matsurface front and back die-attach area and epoxy molding compound composition surface.
Among the figure: die-attach area 1, epoxy molding compound 2, metal level 3, matsurface 4, wire 5, silicon material chip 6.
Embodiment:
Referring to Fig. 1, the present invention can prevent the method for packing of component-device sub-layer of semiconductor plastic package, it is in semiconductor plastic packaging body, surface local in the die-attach area 1 that combines with epoxy molding compound 2 plates metal level 3, makes matsurface 4 on the surface of the die-attach area 1 that combines with epoxy molding compound 2 simultaneously.
Referring to Fig. 2, Fig. 2 is a typical intact plastic-sealed body structural representation.
Referring to Fig. 3,4, Fig. 3,4 for the present invention improve before and after the stressed comparison diagram on die-attach area and epoxy molding compound composition surface.
Claims (2)
1, a kind of method for packing that can prevent component-device sub-layer of semiconductor plastic package, it is characterized in that: in semiconductor plastic packaging body, surface local in the die-attach area (1) that combines with epoxy molding compound (2) plates metal level (3), make matsurface (4) on the surface of the die-attach area (1) that combines with epoxy molding compound (2) simultaneously, the making that described partially plating gold belongs to layer (3) is to adopt depositional mode to realize, the making of described matsurface (4) is to adopt machinery or etching and processing to realize.
2, a kind of method for packing that can prevent component-device sub-layer of semiconductor plastic package according to claim 1 is characterized in that: described deposition is to electroplate or steaming gold or sputter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100223480A CN100483705C (en) | 2007-04-29 | 2007-04-29 | Method against device lamination inside semiconductor plastic packer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100223480A CN100483705C (en) | 2007-04-29 | 2007-04-29 | Method against device lamination inside semiconductor plastic packer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101075600A CN101075600A (en) | 2007-11-21 |
| CN100483705C true CN100483705C (en) | 2009-04-29 |
Family
ID=38976522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007100223480A Active CN100483705C (en) | 2007-04-29 | 2007-04-29 | Method against device lamination inside semiconductor plastic packer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100483705C (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1116770A (en) * | 1994-06-06 | 1996-02-14 | 摩托罗拉公司 | Method and apparatus for improving interfacial adhesion between a polymer and a metal |
| US6184064B1 (en) * | 2000-01-12 | 2001-02-06 | Micron Technology, Inc. | Semiconductor die back side surface and method of fabrication |
| CN1848420A (en) * | 2005-04-15 | 2006-10-18 | 三星Techwin株式会社 | Lead frame for semiconductor package |
| CN1851914A (en) * | 2006-05-29 | 2006-10-25 | 朱冬生 | Lead-frame and semi-conductor device with same |
-
2007
- 2007-04-29 CN CNB2007100223480A patent/CN100483705C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1116770A (en) * | 1994-06-06 | 1996-02-14 | 摩托罗拉公司 | Method and apparatus for improving interfacial adhesion between a polymer and a metal |
| US6184064B1 (en) * | 2000-01-12 | 2001-02-06 | Micron Technology, Inc. | Semiconductor die back side surface and method of fabrication |
| CN1848420A (en) * | 2005-04-15 | 2006-10-18 | 三星Techwin株式会社 | Lead frame for semiconductor package |
| CN1851914A (en) * | 2006-05-29 | 2006-10-25 | 朱冬生 | Lead-frame and semi-conductor device with same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101075600A (en) | 2007-11-21 |
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Effective date of registration: 20221123 Address after: 201201 room 111, building 1, No. 200, Jichuang Road, Pudong New Area, Shanghai Patentee after: Changdian Technology Management Co.,Ltd. Address before: 214431 No. 275 middle Binjiang Road, Jiangsu, Jiangyin Patentee before: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY Co.,Ltd. |
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