CN101075601A - Method for improving device lamination inside semiconductor plastic packer - Google Patents
Method for improving device lamination inside semiconductor plastic packer Download PDFInfo
- Publication number
- CN101075601A CN101075601A CN 200710022349 CN200710022349A CN101075601A CN 101075601 A CN101075601 A CN 101075601A CN 200710022349 CN200710022349 CN 200710022349 CN 200710022349 A CN200710022349 A CN 200710022349A CN 101075601 A CN101075601 A CN 101075601A
- Authority
- CN
- China
- Prior art keywords
- semiconductor plastic
- die
- attach area
- molding compound
- improving device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
A packing method to avoid delamination of the elements in semi-conducting package includes: making a groove or several ones in parallel/crossing on the surface of the lead frame jointed to the epoxy resin package; coarsening the surface.
Description
Technical field:
The present invention relates to a kind of semiconductor plastic packaging body components and parts, especially relate to a kind of method for packing that can improve component-device sub-layer of semiconductor plastic package.Belong to the semiconductor packaging field.
Background technology:
The packaging body that plastic semiconductor encapsulation components and parts adopt multiple material to combine substantially, material wherein mainly contains die-attach area, epoxy resin, wire, polymer binder, the coat of metal etc.But the variation of factors such as different material can Yin Wendu, humidity, vibration and cause easily and between different material, produce layering; Especially in hot environment, because the thermal coefficient of expansion of different material is different, so can be in the horizontal direction or vertical direction produce in various degree draw, push away stress, and then between different material, produce layering (shown in Fig. 4 (a), 5 (a), 6 (a)), finally cause problems such as the functional defect of plastic semiconductor encapsulation components and parts or early failure.
Summary of the invention:
The objective of the invention is to overcome above-mentioned deficiency, a kind of method for packing that can improve component-device sub-layer of semiconductor plastic package is provided.
Purpose of the present invention can be realized by following scheme: a kind of method for packing of component-device sub-layer of semiconductor plastic package that can improve is in semiconductor plastic packaging body, producing one or more parallel with the surface of the die-attach area of epoxy molding compound combination or/and the groove that intersects is made matsurface on the surface of the die-attach area that combines with epoxy molding compound simultaneously.The making of groove and matsurface can be adopted machinery or etching and processing or mode such as strike off realizes.Groove has increased contact area and the adhesion between interior die-attach area of plastic-sealed body and epoxy resin, can reduce the shear stress that the two is produced because of the different material expansion on X and Y in-plane; Simultaneously, by make on the top layer of die-attach area that matsurface increases and epoxy resin between bonded area, reduce die-attach area that factor such as Yin Lali causes and the sliding force between the epoxy resin.Therefore, more than being used in combination can make between die-attach area and the epoxy resin and stinging tightlyer mutually of two kinds of schemes, thereby play the effect (as Fig. 3,4) that prevents or reduce layering.
Plastic semiconductor of the present invention encapsulates the improvement of components and parts lamination problem, helps improving the heat-sinking capability and the thermal stress resistance changing capability of components and parts, and the sealing of product, functional parameter and reliability all are guaranteed.
Description of drawings
Fig. 1 is the embodiments of the invention schematic diagram.
Fig. 2 is a typical intact plastic-sealed body structural representation of the present invention.
Fig. 3 (a) and (b), (c) are for making the stressed comparison diagram on groove front and back die-attach area and epoxy molding compound composition surface.
Fig. 4 (a) and (b) are for making the stressed comparison diagram on matsurface front and back die-attach area and epoxy molding compound composition surface.
Among the figure: die-attach area 1, epoxy molding compound 2, groove 3, matsurface 4, wire 5, silicon material chip 6.
Embodiment:
Referring to Fig. 1, the present invention can improve the method for packing of component-device sub-layer of semiconductor plastic package, in semiconductor plastic packaging body, producing one or more parallel with the surface of the die-attach area 1 of epoxy molding compound 2 combinations or/and the groove 3 that intersects is made matsurface 4 on the surface of the die-attach area 1 that combines with epoxy molding compound 2 simultaneously.
Referring to Fig. 2, Fig. 2 is a typical intact plastic-sealed body structural representation.
Referring to Fig. 3,4, Fig. 3,4 for the present invention improve before and after the stressed comparison diagram on die-attach area and epoxy molding compound composition surface.
Claims (2)
1, a kind of method for packing that can improve component-device sub-layer of semiconductor plastic package, it is characterized in that: in semiconductor plastic packaging body, producing one or more parallel with the surface of the die-attach area (1) of epoxy molding compound (2) combination or/and the groove that intersects (3) is made matsurface (4) on the surface of the die-attach area (1) that combines with epoxy molding compound (2) simultaneously.
2, a kind of method for packing that can improve component-device sub-layer of semiconductor plastic package according to claim 1 is characterized in that: the making of described groove (3) and matsurface (4) is to adopt machinery or etching and processing or the mode of striking off to realize.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710022349 CN101075601A (en) | 2007-04-29 | 2007-04-29 | Method for improving device lamination inside semiconductor plastic packer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710022349 CN101075601A (en) | 2007-04-29 | 2007-04-29 | Method for improving device lamination inside semiconductor plastic packer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101075601A true CN101075601A (en) | 2007-11-21 |
Family
ID=38976523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200710022349 Pending CN101075601A (en) | 2007-04-29 | 2007-04-29 | Method for improving device lamination inside semiconductor plastic packer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101075601A (en) |
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2007
- 2007-04-29 CN CN 200710022349 patent/CN101075601A/en active Pending
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |