CN1905145A - Method of making a stacked die package - Google Patents

Method of making a stacked die package Download PDF

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Publication number
CN1905145A
CN1905145A CNA2006100940722A CN200610094072A CN1905145A CN 1905145 A CN1905145 A CN 1905145A CN A2006100940722 A CNA2006100940722 A CN A2006100940722A CN 200610094072 A CN200610094072 A CN 200610094072A CN 1905145 A CN1905145 A CN 1905145A
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CN
China
Prior art keywords
chip
bottom base
stacked die
encapsulation
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2006100940722A
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Chinese (zh)
Inventor
阿米努丁·伊斯梅尔
卢威耀
张光美
杨清才
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
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Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN1905145A publication Critical patent/CN1905145A/en
Pending legal-status Critical Current

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Die Bonding (AREA)
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Abstract

A method of making a stacked die package ( 50 ) includes attaching and electrically connecting a first integrated circuit (IC) die ( 52 ) to a base carrier ( 56 ). A plurality of successive layers ( 54 A, 54 B and 54 C) of an adhesive material ( 54 ) is formed on the first die ( 52 ). A second die ( 72 ) is attached to the first die ( 52 ) with the adhesive material ( 54 ) such that the successive layers of adhesive material ( 54 A, 54 B and 54 C) maintain a predetermined spacing (H) between the first die ( 52 ) and the second die ( 72 ). The second die ( 72 ) is electrically connected to the base carrier ( 56 ).

Description

Make the method for stacked die encapsulation
Background of invention
The present invention relates in general to the encapsulation of integrated circuit (IC), more specifically to the method for a kind of manufacturing chip stacked encapsulation (stacked die package).
The chip stacked encapsulation is characterised in that to have the two or more chips that are layered in the single encapsulation.Two or more chip laminates have improved the function that encapsulates in single encapsulation integrated, and need not to improve its size.Fig. 1 represents conventional chip stacked encapsulation 10.Encapsulation 10 comprises following chip 12, bottom base 14 and goes up chip 16.Bottom chip 12 utilizes first adhesive layer 18 to be connected on the bottom base 14.Bonding pad (not shown) on following chip 12 and last chip 16 utilizes first lead 20 and second lead 22 to be electrically connected with bottom base 14 by wire-bonded respectively.Utilize 24 pairs of following chips 12 of resin and last chip 16 and first and second leads 20,22 to seal, form stacked Chip Packaging 10 thus.As can see from Figure 1, when last chip 16 is connected to down on the chip 12, needing enough big spacing down between chip and the last chip 12,16 to prevent that first lead 20 is produced destruction.Therefore, conventional way is to adopt separator 26 always, and it is a blank silicon normally, thereby can between chip and last chip 12 and 16 enough spacings arranged down.Separator 26 utilizes second adhesive layer 28 to be connected down on the chip 12, and goes up chip 16 subsequently and utilize the 3rd adhesive layer 30 to be connected on the separator 26.When adopting blank silicon first lead 20 to be produced the problem of destroying when solving on stacked chip 16 in stacked die encapsulation, it has improved leading time and manufacturing cost.
In view of the above, need provide a kind of method of manufacturing stacked die encapsulation of cheapness, this method does not need blank silicon.
Description of drawings
Will more be expressly understood following when read in conjunction with the accompanying drawings to detailed description of the preferred embodiment of the present invention.The present invention is with the way of example illustrative and not limited by accompanying drawing, and identical in the accompanying drawings Reference numeral is represented similar member.Will be understood that accompanying drawing is not to draw to scale and be simplified for the ease of understanding the present invention.
Fig. 1 is the enlarged cross-sectional view that conventional stacked die encapsulates;
Fig. 2 is the enlarged cross-sectional view that is formed with first or following chip of a plurality of bonding material layers according to the embodiment of the present invention thereon;
Fig. 3 comprises second or go up the enlarged cross-sectional view of the following chip shown in Figure 2 of chip;
Fig. 4 is the enlarged cross-sectional view that is connected to the following chip of bottom base according to another embodiment of the present invention by reverse combination;
Fig. 5 is the enlarged cross-sectional view with following chip shown in Figure 4 of a plurality of bonding material layers that form thereon; And
Fig. 6 has the following chip shown in Figure 5 of stacked last chip and the enlarged cross-sectional view of bonding material layer thereon.
Embodiment
Hereinafter the detailed description that proposes in conjunction with the accompanying drawings is used as the description to the current preferred implementation of the present invention, rather than will represent the unique form of the present invention of implementing.Will be understood that identical or equivalent function can be realized by the different execution mode that comprises within the spirit and scope of the present invention.In order to simplify, be used to illustrate that example of the present invention only relates to the encapsulation with two stacked dies.But in fact same invention can be used in the encapsulation that has more than two stacked dies.In the accompanying drawings, identical Reference numeral is used to indicate the same member in each view.
The invention provides a kind of method of making chip stacked encapsulation, said method comprising the steps of: first integrated circuit (IC) chip is linked to each other with bottom base and be electrically connected.On first chip, form a plurality of folded mutually successively bonding material layers.Second chip utilizes jointing material to be connected on first chip, makes folded mutually successively bonding material layer keep predetermined spacing between first chip and second chip.Second chip is electrically connected with bottom base.
The present invention also provides a kind of method of making the stacked die encapsulation, and said method comprising the steps of: an IC chip is connected on the bottom base, and first chip has lower surface and upper surface.Upper surface has center and external zones.External zones comprises a plurality of first chips incorporate sheets.The lower surface of first chip is connected the end face of bottom base.First chip is by being electrically connected with the first chips incorporate sheet wire-bonded and with the end face wire-bonded of bottom base first lead with bottom base.On the center of first chip upper surface, form a plurality of folded mutually successively bonding material layers.The lower surface of second chip utilizes jointing material to be connected on the upper surface of first chip, makes folded mutually successively bonding material layer keep predetermined spacing between first chip and second chip.Second chip comprises a plurality of second chips incorporate sheets that are positioned on its upper surface.By with the second chips incorporate sheet wire-bonded and with the end face wire-bonded of bottom base second chip being electrically connected with bottom base second lead.At last, at least a portion of first and second chips, first and second leads and bottom base is packed.
The present invention also provides a kind of method of making the stacked die encapsulation, and said method comprising the steps of: an IC chip is connected on the bottom base, and first chip has lower surface and upper surface.Upper surface has center and external zones.External zones comprises a plurality of first chips incorporate sheets.The lower surface of first chip is connected on the end face of bottom base.On each first chips incorporate sheet, form a plurality of first lugs.By will oppositely being connected from first lead of bottom base end face on first lug on the first chips incorporate sheet first chip is electrically connected with bottom base, makes that forming a plurality of stitch on first lug connects.On connecting, stitch forms a plurality of second lugs.On the center of first chip upper surface, form a plurality of folded mutually successively bonding material layers.First and second lugs have formed wall around the first chip periphery district to comprise jointing material.The lower surface of second chip utilizes jointing material to be connected on the upper surface of first chip, makes folded mutually successively bonding material layer keep predetermined spacing between first chip and second chip.Second chip comprises a plurality of second chips incorporate sheets that are positioned on its upper surface.By with the second chips incorporate sheet wire-bonded and with the end face wire-bonded of bottom base second chip being electrically connected with bottom base second lead.At last, at least a portion of first and second chips, first and second leads and bottom base is packed.
Fig. 2 and 3 is expression manufacturing enlarged cross-sectional view according to the method for the stacked die encapsulation 50 of one embodiment of the present invention.
Referring now to Fig. 2, show folded mutually successively layer 54A, the 54B of a plurality of jointing materials 54 and first or following integrated circuit (IC) chip 52 of 54C with formation thereon.First chip 52 links to each other with bottom base or substrate 56 and is electrically connected.
First chip 52 has lower surface 58 and upper surface 60.Upper surface 60 comprises center (not shown) and external zones (not shown).The lower surface 58 of first chip 52 utilizes the adhesive (not shown) to be connected on the end face 62 of bottom base 56.Adhesive can be any suitable jointing material, for example adhesive tape, thermoplastic adhesives, epoxide resin material or the like.This adhesive that is used for the IC chip is connected on the bottom base is well-known to those skilled in the art.
First chip 52 utilizes first lead 64 to be electrically connected with bottom base 56.In this particular instance, a plurality of first chips incorporate sheets, 66 lead-in wires on first lead 64 and first chip, 52 external zoness are connected and go between with the end face 62 of bottom base 58 and are connected.Suitable wire bonds generally includes conductive metal wire, and it is made of copper or gold usually.
By being distributed in the mode that repeatedly applies, jointing material 54 forms folded mutually successively bonding material layer 54A, 54B and 54C on first chip, 52 centers.In this particular instance, jointing material 54 is dispensed in repeatedly applying on the center of first chip, 52 upper surfaces 60 with uncured or soft state.After applying, jointing material 54 was cured by the time limit that exposes and/or heating is stipulated at every turn.When layer 54A and 54B the preceding solidifies respectively basically, just when forming the preceding the jointing material 54 of layer 54A, 54B and be in gluey deformability state, be used for each follow-up layer 54B and the jointing material 54 of 54C and be assigned with.State of cure can be controlled by the temperature of regulating the heater block (not shown), and this is that those skilled in the art is known.
When full solidification, it is required with second or go up chip and be fixed on mechanical strength on first chip 52, as mentioned below that folded mutually successively bonding material layer 54A, 54B and 54C provide.Folded mutually successively bonding material layer 54A, 54B and 54C can form on first chip 52 in many ways, for example utilize pin 68 and syringe (not shown) or epoxy resin overflow register, and this is that those skilled in the art is known.In this particular instance, the thickness of each bonding material layer 54A, 54B and 54C is between about 1.5 mils-about 2.0 mils.But, should be appreciated that the present invention is not subjected to the restriction of the thickness of each layer 54A, 54B and 54C.The thickness of each layer 54A, 54B and 54C can change by the size that changes the pin 68 that distributes jointing material 54.
Although the jointing material 54 in this particular instance does not contact with first lead 64, but those skill in the art will appreciate that, jointing material 54 can contact or be sealed on the wire-bonded 70 that forms between first bonding pad 66 of first lead 64 and first chip 52 in the alternative, strengthens the joint between them thus.Jointing material 54 can comprise and is used to a chip is connected any common adhesive on another chip.Common adhesive comprises epoxy resin, cyanate and polyimides.Jointing material 54 preferably hasp solidifies (snapcure) material, and this is well known to a person skilled in the art.
Referring now to Fig. 3, show stacked die encapsulation 50, wherein second or go up chip 72 and be layered on first chip 52.More particularly, utilize the lower surface of jointing material 54 second or last chip 72 to be connected on the upper surface 60 of first chip 52.The lower surface of second chip 72 is bonded in the superiors of jointing material 54, here is a layer 54C. Bonding material layer 54A, 54B and 54C guarantee to have between first and second chips 52 and 72 enough spacings can not destroy be electrically connected (wire-bonded) of first lead 64 and bonding pad 66 to guarantee second chip 72.
Second chip 72 is electrically connected with bottom base 56, and it provides and has been used to make first and second chips 52 and 72 Internets that are electrically connected and are electrically connected with other parts or device mutually.In this particular instance, second chip 72 utilizes second lead 74 to be electrically connected with bottom base 56, second lead 74 be positioned at second chip, 72 upper surfaces on a plurality of second chips incorporate sheet, 76 wire-bonded and with the end face 62 of bottom base 56 on corresponding bonding pad wire-bonded.Second lead 74 is same types with first lead 64 preferably.
At last, first and second chips 52 and 70, first and second leads 66 and 74 and at least a portion of bottom base 56 utilize sealant 78 for example resin be packed.Can operate by the execution mold pressing and finish described encapsulation step, this is known to those skilled in the art.
As mentioned above, folded mutually successively bonding material layer 54A, 54B and 54C keep preset space length H between first and second chips 52 and 72.Preset space length H is enough to protect first chip 52 and bottom base 56, here is the destruction that the electrical connection between first lead 64 is not connected with first chip 52 by second chip 72.In this particular instance, preset space length H is about 5 mils at least.However, it will be understood by those skilled in the art that the present invention is not subjected to the restriction of spacing H size.But the size of spacing H depends on by first lead 64 and extends beyond the upper surface 60 of first chip 52 and the height H L of the coil that forms.Specifically, spacing H must be bigger than the height H L of coil.For example, the spacing H of about 6 mils requires the coil height HL by about 4 mils.Although only show three (3) folded mutually successively bonding material layer 54A, 54B and 54C in 3 at Fig. 2, but it will be understood by those skilled in the art that the present invention is not subjected on first chip 52 restriction of the quantity of folded adhesive layer mutually successively that forms, more or less layer can be arranged according to the thickness of required spacing H and every layer.
First chip 52 and second chip 72 preferably have substantially the same length and width dimensions.But second chip 72 can be bigger slightly or littler slightly than first chip 52.For example, the size range of common first and second chips can be from 4 millimeters * 4 millimeters-12 millimeters * 12 millimeters.First and second chips 52,72 also can have identical thickness, and still, this is optional.According to the profile thickness of required final encapsulation, first and second chips 52,72 can have the thickness range from about 6 mils to about 21 mils.In bottom base 56, first chip 52 and second chip 72 each all is type known to a person of ordinary skill in the art, for the complete the present invention that understands does not need these parts are further described.
Be described referring now to Fig. 4-6 pair another embodiment of the present invention, Fig. 4-the 6th, the enlarged cross-sectional view of the method for stacked die encapsulation 100 is made in expression.
Referring now to Fig. 4, first or down chip 102 link to each other with bottom base or substrate 104 by reverse engagement and be electrically connected, as shown in the figure.First chip 102 has lower surface 106 and upper surface 108.Upper surface 108 comprises center (not shown) and external zones (not shown).The lower surface 106 of first chip 102 utilizes the adhesive (not shown) to be connected on the end face 110 of bottom base 104.Adhesive can be any suitable jointing material, for example adhesive tape, thermoplastic adhesives, epoxide resin material or the like.This adhesive that is used for the IC chip is connected on the bottom base is well-known to those skilled in the art.
On each first chips incorporate sheet 114 on first chip, 102 external zoness, form a plurality of first lugs 112.First chip 102 utilizes first lead 116 to be electrically connected with bottom base 104.In this particular instance, first lead 116 is reversely connected to first lug 112 on the first chips incorporate sheet 114 from the end face 110 of bottom base 104, makes that forming a plurality of stitch on first lug 112 connects.The joint line that is suitable for generally comprises metal wire, as copper or gold thread.On connecting, stitch forms a plurality of second lugs 118.First and second lugs 112 and 118 walls that form around first chip, 102 external zoness.
Referring now to Fig. 5, on first chip 102, form a plurality of layer 120A, 120B, 120C and the 120D of folded mutually jointing material 120 successively.By being distributed in the mode that repeatedly applies, jointing material 120 forms folded mutually successively bonding material layer 120A, 120B, 120C and 120D on first chip 102.In this particular instance, jointing material 120 is dispensed in repeatedly applying on the center of first chip, 102 upper surfaces 108 with uncured or soft state.After applying at every turn, jointing material 120 by expose and/or time limit of heating regulation and at least the part be cured.When layer 120A, 120B and 120C solidify respectively basically the preceding, just when forming the preceding the jointing material 120 of layer 120A, 120B, 120C and be in gluey deformability state, be used for each follow-up layer 120B, 120C and the jointing material 120 of 120D and be assigned with.As mentioned above, state of cure can be controlled by the temperature of regulating the heater block (not shown), and this is that those skilled in the art is known.
When full solidification, it is required with second or go up chip and be fixed on mechanical strength on first chip 102, as mentioned below that folded mutually successively bonding material layer 120A, 120B, 120C and 120D provides.Folded mutually successively bonding material layer 120A, 120B, 120C and 120D can form on first chip 102 in many ways, for example utilize pin 122 and syringe (not shown) or epoxy resin overflow register, and this is that those skilled in the art is known.In this particular instance, the thickness of each bonding material layer 120A-120D is between about 1.5 mils-about 2.0 mils.But, should be appreciated that the present invention is not subjected to the restriction of every layer thickness, the thickness of each layer can change by the size that changes the pin 122 that distributes jointing material 120.
Be used to comprise jointing material 120 around first and second lugs 112 of first chip, 102 external zoness formation and 118 wall, described jointing material is dispensed on the center of first chip 102.Although gapped between first and second lugs 112 and 118 in the wall, jointing material still is contained in the wall by capillarity, and this is because the formed container of wall has the cause of very little cross-sectional area.Jointing material 120 is the hasp curing materials preferably, and this is known to those skilled in the art.
Referring now to Fig. 6, show stacked die encapsulation 100.Second or the lower surface of going up chip 124 utilize jointing material 120 to be connected on the upper surface 108 of first chip 102.More particularly, second chip 124 sticks to the 120D of the superiors of jointing material 120.Second chip 124 is electrically connected with bottom base 104 subsequently, and it provides and has been used to make first and second chips 102 and 124 Internets that are electrically connected and are electrically connected with other parts or device mutually.In this particular instance, second chip 124 utilizes second lead 126 to be electrically connected with bottom base 104, a plurality of second chips incorporate sheet (not shown) wire-bonded on second lead and second chip, 124 upper surfaces 128 and with the end face wire-bonded of bottom base 104.At last, first and second chips 102 and 124, first and second leads 116 and 126 and at least a portion of bottom base 104 utilize sealant 130 for example resin be packed.The soldered ball (not shown) can be connected on the lower surface of substrate 104, forms the BGA encapsulation thus, and this is known in the art.Alternatively, substrate 104 can comprise the lead frame mark zone, thereby forms the encapsulation of QFN type.For example can by array just molded array process (MAP) once form one or once form a plurality of packaging systems 100.
As mentioned above, folded mutually successively bonding material layer 120A-120D keeps preset space length H between first and second chips 102 and 124.Preset space length H is enough to protect first chip 102 and bottom base 104, here is the destruction that the electrical connection between first lead 116 is not connected with first chip 102 by second chip 124.In this particular instance, preset space length H is about 5 mils at least.However, it will be understood by those skilled in the art that the present invention is not subjected to the restriction of spacing H size.As mentioned above, the height H L of the size of the spacing H coil that must form than extending beyond the upper surface 108 of first chip 102 by first lead 114 is bigger.In addition, although in Fig. 4-6, only show four (4) folded mutually successively bonding material layer 120A, 120B, 120C and 120D, but it will be understood by those skilled in the art that the present invention is not subjected on first chip 102 restriction of the quantity of folded adhesive layer mutually successively that forms, more or less layer can be arranged according to the thickness of required spacing H and every layer.
And as mentioned above, first and second chips 102 and 124 preferably have substantially the same length and width dimensions.But second chip 124 can be bigger slightly or littler slightly than first chip 102.For example, the size range of common first and second chips can be from 4 millimeters * 4 millimeters-12 millimeters * 12 millimeters.First and second chips 102,124 also can have identical thickness, and still, this is optional.According to the profile thickness of required final encapsulation, first and second chips 102,124 can have the thickness range from about 6 mils to about 21 mils.In bottom base 104, first chip 102 and second chip 124 each all is type known to a person of ordinary skill in the art, for the complete the present invention that understands does not need these parts are further described.
Although the method for making the stacked die encapsulation is described, but the invention allows for a kind of stacked die encapsulation, it comprises the bottom base with end face and bottom surface, first integrated circuit (IC) chip that links to each other and be electrically connected with bottom base, first chip has lower surface and upper surface, upper surface has center and external zones, and wherein the lower surface of first chip links to each other with the end face of bottom base; On the center of first chip upper surface, form a plurality of folded mutually successively bonding material layers; The 2nd IC chip has and utilizes jointing material to be connected to the lower surface of first chip upper surface, and wherein folded mutually successively bonding material layer keeps the preset distance and second chip to be electrically connected with bottom base between first chip and second chip.
Jointing material can be epoxy resin, cyanate and polyimides.Jointing material is the hasp curing materials preferably.The destruction that predetermined spacing is enough to protect the electrical connection between first chip and the bottom base not be connected with first chip by second chip.The thickness of each bonding material layer is between about 1.5 mils-about 2.0 mils, and predetermined spacing is about 5 mils at least.
First chip utilizes first lead to be electrically connected with bottom base.First lead can with a plurality of first chips incorporate sheet wire-bonded in the first chip periphery district and with the end face wire-bonded of bottom base.In alternative embodiment, the stacked die encapsulation is included in a plurality of first lugs that form on the first chips incorporate sheet in the first chip periphery district.First lead makes that from the end face of bottom base and the first lug reverse engagement on first chip forming a plurality of stitch on first lug connects.The stacked die encapsulation is included in stitch and connects a plurality of second lugs of going up formation.First and second lugs have formed wall around the first chip periphery district to comprise jointing material.
Second chip utilizes second lead to be electrically connected with bottom base, a plurality of second chips incorporate sheet wire-bonded on the upper surface of second lead and second chip and with the end face wire-bonded of bottom base.At least a portion of first and second chips, first and second leads and bottom base is utilized sealant, and for example resin is packed.
First and second chips can have substantially the same length and substantially the same width.In alternative embodiment, comparable first chip of second chip is bigger.
Clearly visible from the above description, the present invention provides a kind of manufacturing stacked die encapsulation inexpensive method by eliminate the band that adopts blank silicon or special manufacturing from encapsulation process.Owing to do not need the step of the band that connects blank silicon or special manufacturing, therefore also reduced process time.
In order to illustrate and to describe the explanation that has proposed the preferred embodiment for the present invention, but this explanation is not to want detailed or limit the present invention to disclosed form.It will be appreciated by those skilled in the art that under the prerequisite that does not break away from wide in range inventive concept of the present invention and can make a change above-described execution mode.For example, the present invention is not limited to have the encapsulation of two stacked dies, but can be used in the encapsulation with a plurality of stacked dies.In addition, the present invention is not limited to any single wire-bonded technology or concrete encapsulation.That is to say that the present invention can be applied to the encapsulated type of all wire-bonded, including, but not limited to BGA, QFN, QFP, PLCC, CUEBGA, TBGA and TSOP.In addition, chip size and step can change to adapt to required package design.Therefore, be appreciated that the present invention is not limited to disclosed embodiment, but covered all changes in the spirit and scope of the present invention that limit by accessory claim.

Claims (20)

1. make the method that stacked die encapsulates for one kind, it comprises:
First integrated circuit (IC) chip is connected on the bottom base;
First chip is electrically connected with bottom base;
On first chip, form a plurality of folded mutually successively bonding material layers;
Utilize jointing material that second chip is connected on first chip, wherein, described folded mutually successively bonding material layer keeps predetermined spacing between first chip and second chip; And
Second chip is electrically connected with bottom base.
2. the method for manufacturing stacked die encapsulation as claimed in claim 1 is characterized in that, forms folded mutually successively bonding material layer on first chip by jointing material is distributed in the mode that repeatedly applies.
3. the method for manufacturing stacked die encapsulation as claimed in claim 2 is characterized in that, when layer solidifies basically the preceding the jointing material that is used for each succeeding layer is distributed.
4. the method for manufacturing stacked die as claimed in claim 3 encapsulation is characterized in that, described jointing material is a kind of in epoxy resin, cyanate and the polyimides.
5. the method for manufacturing stacked die encapsulation as claimed in claim 4 is characterized in that described jointing material comprises the hasp curing materials.
6. the method for manufacturing stacked die encapsulation as claimed in claim 1 is characterized in that the destruction that predetermined spacing is enough to protect the electrical connection between first chip and the bottom base not be connected with first chip by second chip.
7. the method for manufacturing stacked die encapsulation as claimed in claim 6 is characterized in that predetermined spacing is about 5 mils at least.
8. the method for manufacturing stacked die encapsulation as claimed in claim 7 is characterized in that the thickness of each bonding material layer is between about 1.5 mils-about 2.0 mils.
9. the method for manufacturing stacked die encapsulation as claimed in claim 1 is characterized in that described first chip utilizes first lead to be electrically connected with bottom base.
10. the method for manufacturing stacked die as claimed in claim 9 encapsulation is characterized in that, a plurality of first chips incorporate sheet wire bond on the external zones of described first lead and first chip upper surface and with the end face wire bond of bottom base.
11. the method for manufacturing stacked die as claimed in claim 9 encapsulation is characterized in that, also is included in the step that forms a plurality of first lugs on each first chips incorporate sheet of external zones of first chip upper surface.
12. the method for manufacturing stacked die encapsulation as claimed in claim 11 is characterized in that, described first lead makes that from the end face of bottom base and the first lug reverse engagement on the first chips incorporate sheet forming a plurality of stitch on first lug connects.
13. the method for manufacturing stacked die encapsulation as claimed in claim 12 is characterized in that, also is included in stitch and connects the step that goes up formation second lug.
14. the method for manufacturing stacked die as claimed in claim 13 encapsulation is characterized in that, first and second lugs have formed wall around the external zones of first chip to comprise jointing material.
15. the method for manufacturing stacked die encapsulation as claimed in claim 9, it is characterized in that, second chip utilizes second lead to be electrically connected with bottom base, a plurality of second chips incorporate sheet wire-bonded on second lead and second chip upper surface and with the end face wire-bonded of bottom base.
16. the method for manufacturing stacked die encapsulation as claimed in claim 15 is characterized in that, also comprises the step of at least a portion that encapsulates first and second chips, first and second leads and bottom base.
17. a method of making the stacked die encapsulation, it comprises:
The one IC chip is connected on the bottom base, and first chip has lower surface and upper surface, and upper surface has center and external zones, and external zones comprises a plurality of first chips incorporate sheets, and the lower surface of first chip is connected on the end face of bottom base;
First chip by with first lead and the first chips incorporate sheet wire-bonded and with the bottom base end face on the first corresponding bonding pad wire-bonded and be electrically connected with bottom base;
On the center of first chip upper surface, form a plurality of folded mutually successively bonding material layers;
Be connected on the upper surface of first chip by the lower surface of folded mutually successively bonding material layer second chip, wherein second chip comprises a plurality of second chips incorporate sheets that are positioned on its upper surface, and folded mutually successively bonding material layer remains on predetermined spacing between first chip and second chip;
By second chip is electrically connected with bottom base with second lead and the second chips incorporate sheet wire-bonded and with the second corresponding bonding pad wire-bonded on the bottom base; And
At least a portion to first and second chips, first and second leads and bottom base encapsulates.
18. the method for manufacturing stacked die encapsulation as claimed in claim 17 is characterized in that, and is further comprising the steps of:
Form a plurality of first lugs on each first chips incorporate sheet, first lead makes that forming a plurality of stitch on first lug connects on oppositely being connected first lug on the first chips incorporate sheet from the first corresponding bonding pad on the bottom base end face; And
Form second lug on stitch connects, first and second lugs have formed wall around the first chip periphery district to comprise adhesive layer.
19. a method of making the stacked die encapsulation, it comprises:
The one IC chip is connected on the bottom base, and first chip has lower surface and upper surface, and upper surface has center and external zones, and external zones comprises a plurality of first chips incorporate sheets, and the lower surface of first chip is connected on the end face of bottom base;
On each first chips incorporate sheet, form a plurality of first lugs;
By will oppositely being connected from first lead of first bonding pad on the bottom base end face on first lug on the first chips incorporate sheet first chip is electrically connected with bottom base, makes that forming a plurality of stitch on first lug connects;
On connecting, stitch forms a plurality of second lugs;
Form a plurality of folded mutually successively bonding material layers on the center of first chip upper surface, first and second lugs have formed wall around the first chip periphery district to comprise jointing material;
Utilize jointing material that the lower surface of second chip is connected on the upper surface of first chip, second chip has a plurality of second chips incorporate sheets that are positioned on its upper surface, and folded mutually successively bonding material layer remains on predetermined spacing between first chip and second chip;
By second chip is electrically connected with bottom base with second lead and the second chips incorporate sheet wire-bonded and with the corresponding second bonding pad wire-bonded on the bottom base end face; And
At least a portion to first and second chips, first and second leads and bottom base encapsulates.
20. the method for manufacturing stacked die encapsulation as claimed in claim 19, it is characterized in that, form folded mutually successively bonding material layer on first chip by jointing material is distributed in the mode that repeatedly applies, and when layer solidifies basically the preceding, the jointing material that is used for each succeeding layer is distributed.
CNA2006100940722A 2005-07-28 2006-06-22 Method of making a stacked die package Pending CN1905145A (en)

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US11/193,144 US20070026573A1 (en) 2005-07-28 2005-07-28 Method of making a stacked die package

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