JPS5851525A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPS5851525A JPS5851525A JP56148819A JP14881981A JPS5851525A JP S5851525 A JPS5851525 A JP S5851525A JP 56148819 A JP56148819 A JP 56148819A JP 14881981 A JP14881981 A JP 14881981A JP S5851525 A JPS5851525 A JP S5851525A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- ribbon
- frames
- semiconductor device
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はプリント配髄板の実装密度を倍増することがで
きる半導体装置、及びその製造方法に関するものである
。即ち、例えば従来の半導体集積回路等の４０ピンのデ
ュアルインラインパッケージとほとんど同寸法、同形状
で８０ビンの実装を可能とするデュアルインラインパッ
ケージを実現することができる半導体装置に係るもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that can double the packaging density of a printed pulp board, and a method for manufacturing the same. That is, the present invention relates to a semiconductor device that can realize a dual in-line package that has almost the same dimensions and shape as a 40-pin dual in-line package such as a conventional semiconductor integrated circuit, and can mount 80 bins.
近年半導体産業とりわけ半導体集積回路の発展は極めて
急速であり、一つの半導体チップに搭載可能な素子数は
年毎にほぼ２倍の割合で増加する傾向にある。従って、
例えば、半導体ｌチッノマイクロゾロセサに於いては当
初の４ビット並列処理のものから、８ビット並列処理へ
、更に１６ビツ＋、３２ビット並列処理へと、その中心
が多ビット化する動向にある。この多ビット化は必然的
に１チツゾ当シの必要なビン数の増加を伴なうこととな
る。例えば、４ビツトタイプでは必要なビン数は２４本
程度であったものが、８ビツトタイプでは４０本程度、
１６ビツトタイプでは４０〜６０本程度必要であシ、３
２ビ、トタイゾでは６０〜１００本程度必要程度想され
る。従来の標準的なｉ４ッケージの形状を第１図に示す
。第１図は２２ピンのデュアルインラインノｅツケージ
の例を示す。In recent years, the semiconductor industry, particularly semiconductor integrated circuits, has been developing extremely rapidly, and the number of elements that can be mounted on one semiconductor chip tends to increase at a rate of approximately double every year. Therefore,
For example, in semiconductor l-chino microprocessors, there is a trend toward multi-bit processing, from the original 4-bit parallel processing to 8-bit parallel processing, and then to 16-bit and 32-bit parallel processing. be. This increase in the number of bits inevitably involves an increase in the number of bins required for one chip. For example, a 4-bit type requires about 24 bins, but an 8-bit type requires about 40.
For 16-bit type, approximately 40 to 60 lines are required, 3
About 60 to 100 pieces are expected to be needed for 2-bi and Totaizo. FIG. 1 shows the shape of a conventional standard i4 package. FIG. 1 shows an example of a 22-pin dual in-line electronic cage.
図示の如く、１１本のリード１が２列に配列された構造
となっている。さて、ピン数が増大すると、パッケージ
の形状が大きくなシ、次に述べる問題点を生ずる。As shown in the figure, the structure has eleven leads 1 arranged in two rows. Now, as the number of pins increases, the size of the package becomes larger, which causes the following problems.
（１） 多ピンになるに従い、プリント配線板上に大
きな面積を必要とし、実装密度を低下せしめ、ひいては
機器の小型化、コンパクト化のネックとなる。(1) As the number of pins increases, a larger area is required on the printed wiring board, lowering the mounting density, and eventually becoming a bottleneck in making devices smaller and more compact.
（２）多ピンになるに従い、標準的なデュアルインライ
ン型では大型化し、取扱いが不便となる。(2) As the number of pins increases, the standard dual in-line type becomes larger and becomes inconvenient to handle.
特に６０ピン以上では、現状ではクワッドインライン型
等の特殊な形状のノ母ツケージとするのが一般的でアシ
ノリント配線板上への実装が不便であるばかシでなく、
・クツケージ自身が高価となシ、且つ半導体装置の組立
上も余分なコストを必要とすることとなる。In particular, for devices with 60 pins or more, it is common practice at present to use a motherboard with a special shape such as a quad inline type, which is inconvenient to mount on an ashinolint wiring board.
- The shoe cage itself is expensive, and additional costs are required for assembling the semiconductor device.
本発明の目的はこれらの欠点を解決するため、半導体装
置の・ぐッケージのリボンフレームラ多重化
にすることによシ従来の半導体装置の・ぐッケーノとほ
ぼ同一の寸法、形状、生産コストで、２倍のピン数を供
給できるようにしたもので、以下詳細に説明する。The purpose of the present invention is to solve these drawbacks by multiplexing the packaging of a semiconductor device into a ribbon frame layer with almost the same dimensions, shape, and production cost as the packaging of a conventional semiconductor device. , which can supply twice the number of pins, will be explained in detail below.
第２図〜第５図は本発明の第１の実施例であシ、第２図
は本発明に係るリボンフレームの上面よシ見た展開図第
３図はリボンフレームの側面図、第４図はこのリボンフ
レームを用いてプラスチック・モールド樹脂で構成した
半導体装置、第５図はこの半導体装置の側面の断面図を
示す。2 to 5 show a first embodiment of the present invention, FIG. 2 is a developed view of the ribbon frame according to the present invention seen from above, FIG. 3 is a side view of the ribbon frame, and FIG. The figure shows a semiconductor device constructed of plastic molded resin using this ribbon frame, and FIG. 5 shows a side sectional view of this semiconductor device.
この構造の特徴とするところは第３図に示すように通常
のリボンフレームを２枚重ね合せた構造にある。７は下
側のリボンフレームを、９は上側のリボンフレームを示
す。これらは絶縁体である接着剤１１によって接着され
ている。２は下側のす＆ンフレームに一体に形成されて
い、る半導体集積回路等のチップ１０を搭載するアイラ
ンドである。上側のリボンフレーム９は、下側のりビン
フレーム７に対して、アイランド部分が無く、且つチッ
プ側の端部がポンディングスペース３の部分だけ短かく
形成されている。又、第２図に示すように、プリント基
板に挿入するリードに対応する部分４と５は上側のリー
ドフレームと下側のリードフレームが千鳥状に交互に形
成されている。チッ７’ＩＯ上のがンディングノぐ、ド
とリードフレーム７と９のチップ側への端部のボンディ
ングスペース３，６とは第３図に示す如く金線の如きが
ンディングワイヤ１３で接続されている。ここでがンデ
ィングワイヤ１３が３に示される下側のリードフレーム
端部のポンデインダス硬−ス３と上側のリードフレーム
端部のボンデインダスペーズ６とは階段状に形成されて
いる。従ってワイヤ１３と１４は２階建のような構造に
張ることができる。The feature of this structure is that, as shown in FIG. 3, it is a structure in which two ordinary ribbon frames are stacked one on top of the other. 7 indicates the lower ribbon frame, and 9 indicates the upper ribbon frame. These are bonded together with an adhesive 11 which is an insulator. Reference numeral 2 designates an island which is integrally formed with the lower wind frame and on which a chip 10 such as a semiconductor integrated circuit is mounted. The upper ribbon frame 9 has no island portion than the lower ribbon frame 7, and its end on the chip side is formed to be shorter by the portion of the bonding space 3. Further, as shown in FIG. 2, in the portions 4 and 5 corresponding to the leads to be inserted into the printed circuit board, upper lead frames and lower lead frames are alternately formed in a staggered manner. The bonding holes 3 and 6 on the chip 7'IO and the bonding spaces 3 and 6 at the ends of the lead frames 7 and 9 toward the chip are connected by a gold wire 13 as shown in FIG. ing. Here, the bonding wire 13 shown at 3 is formed into a stepped shape between the bonding insulator 3 at the end of the lower lead frame and the bonding insulator 6 at the end of the upper lead frame. The wires 13 and 14 can therefore be strung in a two-story structure.
第４図は半導体集積回路等のチップ１０と、ボンディン
グワイヤ１３．１４等とを包み込んでプラスチック封止
し、リードの抜き曲げ加工を完了した、本発明の半導体
装置の完成図である。第５図は第４図の側方よシ見た断
面図である。FIG. 4 is a completed view of the semiconductor device of the present invention, in which a chip 10 such as a semiconductor integrated circuit, bonding wires 13, 14, etc. are wrapped and sealed in plastic, and the lead cutting and bending process is completed. FIG. 5 is a cross-sectional view of FIG. 4 when viewed from the side.
これを製作するには、下側のリードフレーム７及び上側
のリードフレーム９を各々よく知られた通常の製造方法
で製作する。この際、上側に対応するリードフレーム９
は、アイランド部分が無く、且つチップ側の端部を下側
のがンガインダス＜−ス３に対応する部分だけ短かく形
成する。又、リード端部は、上・下側が４，５に示すよ
うに各々千鳥状になるよう上側及び下側のリードフレー
ムを形成する。To manufacture this, the lower lead frame 7 and the upper lead frame 9 are each manufactured using well-known conventional manufacturing methods. At this time, the lead frame 9 corresponding to the upper side
In this case, there is no island portion, and the end portion on the chip side is formed to be shorter by a portion corresponding to the lower conductor index 3. Further, the lead ends form upper and lower lead frames so that the upper and lower sides are staggered, respectively, as shown at 4 and 5.
この上下側の２枚のリードフレームをエポキシ系又はポ
リイミド系等の接着剤を用い、全面に塗布し、圧力を加
えながら貼り合せ、所定の乾燥を行う。後に全面に接着
剤が付着して残っているので、例えばウレソルプのよう
な溶解性の溶剤ではみ出した所などの余分な接着剤を除
去する。このようにして、下側のアイランド部２及びワ
イヤボンディング接続部の金属面を完全に露出する。こ
の露出したアイランド２に金−シリコン共晶又は銀ペー
ストのような接着剤で半導体集積回路等のチップを圧着
し、ダイスボンディングを終了する。An adhesive such as epoxy or polyimide is applied to the entire surface of the two upper and lower lead frames, and the adhesive is bonded together while applying pressure, followed by predetermined drying. Afterwards, adhesive remains on the entire surface, so use a soluble solvent such as uresol to remove excess adhesive from the protruding areas. In this way, the metal surfaces of the lower island portion 2 and wire bonding connections are completely exposed. A chip such as a semiconductor integrated circuit is pressure-bonded to the exposed island 2 using an adhesive such as gold-silicon eutectic or silver paste, and die bonding is completed.
後に自動ワイヤデンディング機に装着し、チップトリボ
ンフレーム間にワイヤデンディングスル。After that, it is installed on an automatic wire ending machine and the wire ending is inserted between the tip tri-bond frame.
ワイヤがンデづングはプログラムによりがンデイング順
を与えであるが、下側リボンへのボンディング、上側り
ボンへのボンディングと交互に２５μｍφの金線液ｉを
する。通常の品質管理基準でワイヤの外観検査をしたの
ちにプラスチックモールド作業を行う。プラスチックモ
ールドは通常の公知の技術で可能であｐｌいずれのモー
ルド樹脂でも成型性、耐湿性が問題なければ使用できる
。The order of bonding the wire is given by the program, and the gold wire liquid i of 25 μm diameter is alternately bonded to the lower ribbon and bonded to the upper ribbon. After the wire is visually inspected according to standard quality control standards, the plastic molding process is carried out. Plastic molding can be done using ordinary known techniques, and any molding resin can be used as long as there are no problems with moldability or moisture resistance.
次に通常の方法によるリード切断、リード曲げ等の機械
加工にしム第４図、第５図に示す半導体装置が完成する
。即ち、ワイヤデンディングは従来の１本分のがンデプ
ングスペースに２本の配線が可能となり、実装密度が向
上する。又、ビンも従来のほぼ一本分のスペースに２本
のビンを形成することが可能である。 、、
以上説明したように、本実施例は２枚のりボン。Next, the semiconductor device shown in FIGS. 4 and 5 is completed by mechanical processing such as cutting the leads and bending the leads by a conventional method. That is, in the case of wire ending, two wires can be installed in the space required for one wire in the conventional method, and the packaging density is improved. Furthermore, it is also possible to form two bottles in the space of approximately one bottle in the conventional case. ,, As explained above, this example uses two sheets of glue.
フレームを重ね合せた構造となっているので、半導体集
積回路等の印刷配線板への実装に際して、実装密度を倍
増することが出来る効果を生ずる。Since it has a structure in which the frames are overlapped, it has the effect of doubling the mounting density when mounting semiconductor integrated circuits and the like on printed wiring boards.
即ち、１４ピンの大きさのノぞ、ケージに２８ビンが実
装でき、４０ピンの大きさのパッケージでは８０２ンが
実装出来る利点を生じる。That is, there is an advantage that 28 bins can be mounted on a cage with a size of 14 pins, and 802 bins can be mounted on a package with a size of 40 pins.
また製造方法の説明において述べたように、従来技術・
と比較して、若干の材料及び製作の手間を要するだけで
あるので、極めて少額の製造コストの上昇に抑えること
ができる利点がある。Also, as mentioned in the explanation of the manufacturing method, the conventional technology
Compared to this, it requires only a small amount of material and manufacturing effort, so it has the advantage of suppressing the increase in manufacturing costs to a very small amount.
第６図は本発明の第２の実施例を示す。この場合は、プ
リント配線板に挿入するリード部分４及び５が通常の標
準型デュアルインラインパッケージにおける如く、スト
レートになっていることを特徴とする。この場合は、リ
ードが千鳥状になっていないので、プリント配線板への
リードの半田ディツプの際、上側と下側のリードが短絡
しやすい問題点を生じるため、第７図に示す↓うな専用
ソケットを介してプリント配線板に実装する必要がおる
。しかしながら、リードが千鳥状の方式と比較して、製
造工程はよシ簡単になシ、半導体装置としてのコストが
よシ低下するメリットが生ずる。また取扱いも容易であ
る。FIG. 6 shows a second embodiment of the invention. This case is characterized in that the lead parts 4 and 5 inserted into the printed wiring board are straight, as in a normal standard dual-in-line package. In this case, the leads are not staggered, so when soldering the leads to the printed wiring board, the upper and lower leads tend to short-circuit. It is necessary to mount it on a printed wiring board via a socket. However, compared to the method in which the leads are staggered, the manufacturing process is simpler and the cost of the semiconductor device is much lower. It is also easy to handle.
第８図は本発明の第３の実施例を示す。この例では、フ
ラットノｅ、ケージのリードを２層構造としたもので且
つ、リード全体を絶縁物で覆い、プリント配線板への接
続部分のみを絶縁物を除去した構造となっている。通常
一般に用いられている半田付けの方法によって、プリン
ト配線板２０上の接続部分２１と、下側又は上側のリー
ド端子の接続部分とが半田付は接着２２される。FIG. 8 shows a third embodiment of the invention. In this example, the leads of the flat cage have a two-layer structure, and the entire lead is covered with an insulating material, and the insulating material is removed only at the portion connected to the printed wiring board. The connecting portion 21 on the printed wiring board 20 and the connecting portion of the lower or upper lead terminal are soldered and bonded 22 by a commonly used soldering method.
このような方法により、フラット・ｅツケージにおいて
もビンの実装密度を大略倍増することが可能である。By such a method, it is possible to approximately double the packaging density of the bins even in a flat e-cage.
尚、以上の説明は、上側と下側り？ンフと一ムの二層の
リード端子構造のものについて説明したが、三層の構造
のものにも、或いは四層以上の構造のものにも当然適用
が可能である。In addition, does the above explanation refer to the upper and lower sides? Although a two-layer lead terminal structure with one layer and one layer has been described, it is naturally applicable to a structure with three layers, or a structure with four or more layers.
又、上層と下層の１７ 、ｐンフレーム間の絶縁体につ
いては、以上の実施例においては、絶縁性のエポキシ系
又はポリイミド系の接着剤で構成しである。In the above embodiments, the insulator between the upper layer and the lower layer 17 and the pn frame is made of an insulating epoxy or polyimide adhesive.
第９図は本発明の第４の実施例を示す外観図である。第
８図に示すように、上側のリード４と下側のリード５と
の間の絶縁体３０を厚く形成したものである。これはエ
ポキシ系もしくはポリイミド系の樹脂の硬化条件等を適
切に選択することによシ、容易にすることができる。絶
縁体３０が薄い方がメタルフレームの切断、折シ曲げ等
の加工は容易であるが、上下層の間のリード間の静電容
量が大きくなる傾向にある。リード間の絶縁体３０を厚
く形成した場合は、リードの切断、折シ曲げ等の加工が
難しくなるが、上下層リード間の静電容量が小さくなる
利点がある。FIG. 9 is an external view showing a fourth embodiment of the present invention. As shown in FIG. 8, the insulator 30 between the upper lead 4 and the lower lead 5 is formed thick. This can be facilitated by appropriately selecting the curing conditions of the epoxy or polyimide resin. The thinner the insulator 30 is, the easier it is to process the metal frame by cutting, bending, etc., but the capacitance between the leads between the upper and lower layers tends to increase. If the insulator 30 between the leads is formed thickly, processing such as cutting and bending the leads becomes difficult, but there is an advantage that the capacitance between the upper and lower layer leads becomes smaller.
以上説明したようにこの発明は、モールド型の半導体集
積回路等のパッケージに適用して、ビンの実装密度をほ
ぼ倍増できるものであり、この構造のための製造コスト
の上昇も僅かなものに抑えることができるものである。As explained above, this invention can be applied to packages for molded semiconductor integrated circuits, etc., and can almost double the packaging density of the bins, and the increase in manufacturing costs for this structure can be kept to a negligible level. It is something that can be done.
又、取扱いも容易である。従がって、高密度半導体集積
回路とシわけマイクロノロセサやメモリに応用して、プ
リント配線板への実装密度の向上、機器の小型化に太き
く貢献するものである。Moreover, it is easy to handle. Therefore, the present invention can be applied to high-density semiconductor integrated circuits, microcontrollers, and memories, greatly contributing to the improvement of mounting density on printed wiring boards and miniaturization of equipment.
第１図は従来の標準的な・ぐッケーノの外観図、第２図
は本発明のリボンフレームの展開図、第３図は本発明の
りがンフレームの側面図、第４図は本発明の第１の実施
例の半導体装置の外観図、第５図は本発明の第１の実施
例の半導体装置の側断面図、第６図は本発明の第２の実
施例を示す外観図、第７図は専用ソケットの断面図、第
８図は第３の実施例を示す外観図である。第９図は第４
の実施例を示す外観図である。
１・・・従来の半導体装置のリード、２・・・アイラン
ド部、３・・・下側リボンフレームのボンディングペー
ス、４・・・上側！ＪｙＰンフレームのリード、５・・
・下側リボンフレームのリード、６・・・上側り？ンフ
レームのがンディングスペース、７・・・下［Ｎ”／フ
レーム、９・・・上側リボンフレーム、１０・・・半導
体チップ、１１・・・絶縁体、２０・・・プリント配線
板、２１・・・プリント配線板上の電極接続部分、２２
・・・半田付接着部分、３０・・・厚く形成された絶縁
体。
第４図 第５図
第６図
５Ｕ ５０
手続補正書（方式）
昭和５７年２月８日
特許庁長官 殿
２ 発明の名称
半導体装置及びその製造方法
３ 補正をする者
事件との関係 特 許出 願 人昭和５７
年１月２６日（発送日）
笛３図Fig. 1 is an external view of a conventional standard guccano, Fig. 2 is a developed view of the ribbon frame of the present invention, Fig. 3 is a side view of the ribbon frame of the present invention, and Fig. 4 is a diagram of the ribbon frame of the present invention. 5 is a side sectional view of the semiconductor device of the first embodiment of the present invention. FIG. 6 is an external view of the semiconductor device of the second embodiment of the present invention. FIG. 7 is a sectional view of the dedicated socket, and FIG. 8 is an external view showing the third embodiment. Figure 9 is the 4th
FIG. 2 is an external view showing an example. 1...Lead of conventional semiconductor device, 2...Island part, 3...Bonding paste of lower ribbon frame, 4...Upper side! Lead of JyP'n Frame, 5...
・Lead of lower ribbon frame, 6...upper side? 7... Lower [N''/frame, 9... Upper ribbon frame, 10... Semiconductor chip, 11... Insulator, 20... Printed wiring board, 21. ...Electrode connection part on printed wiring board, 22
...Solder bonding part, 30...Thickly formed insulator. Figure 4 Figure 5 Figure 6 5U 50 Procedural amendment (method) February 8, 1980 Commissioner of the Japan Patent Office 2 Title of invention Semiconductor device and its manufacturing method 3 Relationship with the case of the person making the amendment Patent Issuance Wish person 1982
January 26, 2019 (shipment date) Whistle 3
Claims (2)
ムに絶縁性の樹脂で接着された第２のリボンフレームと
を含み、半導体チップがいずれか一方のり？ンフレーム
にダイポンディングされ、該半導体チップと該第１及び
第２のリボンフレームとにワイヤデンディングされるリ
ボンフレームのポンディングスペースが、階段状に形成
されていることを特徴とする半導体装置。(1) It includes a first glue frame and a second ribbon frame bonded to the first glue frame with an insulating resin, and the semiconductor chip is attached to one of the glue frames. 1. A semiconductor device, wherein a bonding space of a ribbon frame, which is die-bonded to a ribbon frame and wire-dipped between the semiconductor chip and the first and second ribbon frames, is formed in a stepped shape.
準備する工程と、該第１のリボンフレームと第２のす＆
ンフレームを絶縁性の樹脂で接着する工程と、一方のり
？ンフレームに半導体チップをグイポンディングする工
程と、該半導体チップト該第１及び第２のリボンフレー
ムとにワイヤポンディングする工程とを含む半導体装置
の製造方法。(2) A step of preparing a first ribbon frame and a second ribbon frame, and a step of preparing the first ribbon frame and the second ribbon frame.
The process of gluing the frame with insulating resin, and the glue on the other hand? A method for manufacturing a semiconductor device, comprising the steps of bonding a semiconductor chip to a ribbon frame, and bonding the semiconductor chip to the first and second ribbon frames.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56148819A JPS5851525A (en) | 1981-09-22 | 1981-09-22 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56148819A JPS5851525A (en) | 1981-09-22 | 1981-09-22 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5851525A true JPS5851525A (en) | 1983-03-26 |
Family
ID=15461420
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56148819A Pending JPS5851525A (en) | 1981-09-22 | 1981-09-22 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5851525A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4613473A (en) * | 1984-04-20 | 1986-09-23 | United Technologies Corporation | Method for forming composite articles of complex shapes |
| JPH02209760A (en) * | 1989-02-09 | 1990-08-21 | Shinko Electric Ind Co Ltd | Multiple lead frame |
| US6534846B1 (en) | 1998-11-12 | 2003-03-18 | Shinko Electric Industries Co., Ltd. | Lead frame for semiconductor device and semiconductor device using same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50147667A (en) * | 1974-05-16 | 1975-11-26 |
-
1981
- 1981-09-22 JP JP56148819A patent/JPS5851525A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50147667A (en) * | 1974-05-16 | 1975-11-26 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4613473A (en) * | 1984-04-20 | 1986-09-23 | United Technologies Corporation | Method for forming composite articles of complex shapes |
| JPH02209760A (en) * | 1989-02-09 | 1990-08-21 | Shinko Electric Ind Co Ltd | Multiple lead frame |
| US6534846B1 (en) | 1998-11-12 | 2003-03-18 | Shinko Electric Industries Co., Ltd. | Lead frame for semiconductor device and semiconductor device using same |
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