TW202129829A - Chip packaging structure - Google Patents

Abstract

A chip packaging method and a chip packaging structure are disclosed. The disclosed chip packaging method includes: forming a protective layer having material properties on an active surface of a die; mounting the die whose active surface is formed with the protective layer on a carrier, wherein the active surface faces the carrier, the back surface faces away from the carrier; forming a plastic sealing layer having material properties for encapsulating the die; peeling the carrier to expose the protective layer; forming a conductive layer and a dielectric layer; the packaging method can reduce or eliminate the warpage in the panel packaging process, reduce the precision requirement on the dies on the panel, reduce the difficulty of the panel packaging process, and make the packaged chip structure have a durable lifetime, especially suitable for large panel-level package and large electric flux, thin chip package.

Description

Chip package structure

The present disclosure relates to the field of semiconductor technology, and in particular to chip packaging methods and packaging structures.

Panel-level packaging is about dicing a wafer to separate many dies, arranging and pasting the dies on a carrier board, and encapsulating the many dies at the same time in the same process flow. Panel-level packaging has received widespread attention as a technology that has emerged in recent years. Compared with traditional wafer-level packaging, panel-level packaging has the advantages of high production efficiency, low production costs, and suitability for mass production.

However, there are many technical barriers to panel packaging, such as the problem of panel warpage and the accuracy of die alignment on the panel.

Especially in the current trend of small and lightweight electronic equipment, small and thin chips are increasingly favored by the market. However, the difficulty of packaging small and thin chips using large-scale panel packaging technology cannot be underestimated.

The present disclosure aims to provide a semiconductor chip packaging method and a chip packaging structure. The packaging method can reduce or eliminate warpage in the panel packaging process, reduce the precision requirements of the die on the panel, and reduce the difficulty of the panel packaging process, and The packaged chip structure has a durable life cycle, and is especially suitable for large-scale panel-level packaging and packaging of large electric flux and thin chips.

The present disclosure provides a chip packaging structure, including: at least one die; a protective layer formed on the active surface of the die, and conductive filled through holes are formed in the protective layer, at least a part of the conductive filled through holes and at least A part of the electrical connection points are electrically connected; a plastic encapsulation layer, the plastic encapsulation layer is used to encapsulate the crystal grains; a conductive layer is formed at least partly on the surface of the protective layer, and the conductive layer and at least a part of the conductive filling are connected The hole is electrically connected; the dielectric layer is formed on the conductive layer.

In an embodiment, the Young's modulus of the protective layer is any of the following numerical ranges or values: 1000 to 20000 MPa, 1000 to 10000 MPa, 4000 to 8000 MPa, 1000 to 7000 MPa, 4000 to 7000 MPa, 5500 MPa.

In one embodiment, the material of the protective layer is an organic/inorganic composite material.

In another embodiment, the thickness of the protective layer is any of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, 50 μm.

In another embodiment, the thermal expansion coefficient of the protective layer is any of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In a preferred embodiment, the thermal expansion coefficient of the plastic encapsulation layer is any of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In another preferred embodiment, the protective layer and the plastic encapsulation layer have the same or similar thermal expansion coefficients.

In another preferred embodiment, the protective layer includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm.

In an advantageous embodiment, the diameter of the inorganic filler particles is 1 to 2 μm.

In an advantageous embodiment, the conductive filled via is formed by a conductive medium-filled protective layer opening, and the conductive filled via has a lower surface of the conductive filled via and an upper surface of the conductive filled via. The ratio of the surface area to the area of the upper surface of the conductive filled through hole is 60% to 90%.

In an advantageous embodiment, there is a gap between the lower surface of the conductive filled via and the insulating layer, and/or the lower surface of the conductive filled via is at a position close to the center of the electrical connection point.

In a preferred embodiment, the protective layer opening is a protective layer opening formed by laser patterning.

In another preferred embodiment, the conductive layer includes conductive traces and/or conductive bumps; wherein: at least a part of the conductive traces closest to the active surface of the die is formed on the surface of the protective layer, and The conductive filled via is electrically connected; the conductive bump is formed on the bonding pad or the connection point of the conductive trace.

In another preferred embodiment, the conductive layer is one or more layers.

In a preferred embodiment, a conductive covering layer is formed on the electrical connection point.

In an advantageous embodiment, the thickness of the conductive covering layer is 2 to 3 μm.

In an advantageous embodiment, the conductive covering layer is a Cu layer.

In a preferred embodiment, at least a part of the conductive trace closest to the active surface of the die is formed on the front surface of the plastic encapsulation layer and extends to the edge of the package body.

In a preferred embodiment, the back surface of the die is exposed from the molding layer.

In a preferred embodiment, the surface of the dielectric layer has grooves at positions corresponding to the conductive layer.

In a preferred embodiment, the at least one crystal grain is a plurality of crystal grains, and the plurality of crystal grains are electrically connected according to a product design.

In a preferred embodiment, the plurality of dies are dies with different functions to form a multi-chip module.

The present disclosure provides a chip packaging method, including: forming a protective layer on the active surface of the crystal grain; mounting the crystal grain with the protective layer formed on the active surface of the crystal grain on a carrier, and the active surface of the crystal grain Facing the carrier board, the back of the die faces away from the carrier board; forming a plastic encapsulation layer for encapsulating the die; peeling off the carrier board to expose the protective layer.

In one embodiment, forming a protective layer on the active surface of the die includes: forming a protective layer on the active surface of the wafer of the wafer, and cutting the wafer on which the protective layer is formed into a plurality of crystal grains with the protective layer.

In one embodiment, the material of the protective layer is an organic/inorganic composite material.

In an embodiment, the Young's modulus of the protective layer is any of the following numerical ranges or values: 1000~20000 MPa, 1000~10000 MPa, 4000~8000 MPa, 1000~7000MPa, 4000~7000 MPa, 5500 MPa .

In an embodiment, the thickness of the protective layer is any of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, 50 μm.

In another embodiment, the thermal expansion coefficient of the protective layer is any of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In an embodiment, the thermal expansion coefficient of the plastic encapsulation layer is any of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In another embodiment, the protective layer and the plastic encapsulation layer have the same or similar thermal expansion coefficients.

In a preferred embodiment, the protective layer includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm or the diameter of the inorganic filler particles is 1 to 2 μm.

In another preferred embodiment, the method further includes the step of forming a protective layer opening on the protective layer, and the ratio of the area of the lower surface of the protective layer opening to the upper surface of the protective layer opening is 60% to 90%.

In a preferred embodiment, laser patterning is used to form the protective layer openings.

In another preferred embodiment, the method further includes the step of thinning the back surface of the plastic encapsulation layer to expose the back surface of the die.

In a preferred embodiment, the method further includes a step of forming a groove at a position corresponding to the conductive layer on the dielectric layer by metal etching.

In a preferred embodiment, the method further includes the step of performing plasma surface treatment and/or chemical promotion modifier treatment on the surface of the wafer and/or the protective layer.

In a preferred embodiment, it further includes an electroless plating process step on the active surface of the wafer to form a conductive covering layer on the electrical connection points.

In order to make the technical solutions of the present disclosure clearer and the technical effects more clear, the following gives detailed and specific descriptions and explanations of the preferred embodiments of the present disclosure in conjunction with the accompanying drawings. Disclosure restrictions.

1 to 12 are flowcharts of a chip packaging method proposed according to an exemplary embodiment of the present disclosure.

As shown in FIG. 1, at least one wafer 100 is provided. The wafer 100 has a wafer active surface 1001 and a wafer back surface 1002. The wafer 100 includes a plurality of dies 113, wherein the active surface of each die constitutes The active surface 1001 of the wafer 100, the active surface of each crystal grain in the wafer 100 is formed into a series of active components and passive components through a series of processes such as doping, deposition, and etching. The active components include diodes and triodes. Passive components include voltage transformers, capacitors, resistors, inductors, etc. These active components and passive components are connected by connecting wires to form a functional circuit, thereby realizing various functions of the chip. The active surface 1001 of the wafer further includes an electrical connection point 103 for leading out the functional circuit and an insulating layer 105 for protecting the electrical connection point 103.

Preferably, an electroless plating process step is performed on the active surface 1001 of the wafer to form a conductive covering layer on the electrical connection point 103. Optionally, the conductive coating layer is one or more layers of Cu, Ni, Pd, Au, Cr; preferably, the conductive protection layer is a Cu layer; the thickness of the conductive protection layer is preferably 2-3 μm. The conductive cover layer is not shown in FIG. 1. The conductive covering layer can protect the electrical connection points 103 on the active surface 1001 of the wafer from laser damage in the subsequent step of forming the opening of the protective layer.

As shown in FIG. 2, a protective layer 107 is applied on the active surface 1001 of the wafer.

In one embodiment, the protective layer is applied to the active surface 1001 of the wafer in a lamination manner.

Optionally, before the step of applying the protective layer 107 on the active surface of the wafer 1001, the active surface 1001 and/or the surface of the protective layer 107 on the wafer 100 is applied Physical and/or chemical treatment to make the bonding between the protective layer 107 and the wafer 100 tighter. The treatment method can optionally be plasma surface treatment to roughen the surface to increase the bonding area and/or chemical promotion modifier treatment, introducing a modification promotion group between the wafer 100 and the protective layer 107, For example, surface modifiers with both organic affinity and inorganic affinity groups can increase the adhesion between the organic/inorganic interface layer.

The protective layer 107 can be used to protect the active surface 1131 of the crystal grain. In the subsequent molding process, due to the molding pressure, the molding material that flows under heating can easily penetrate into the gap between the die 113 and the carrier 117, destroying the circuit on the die active surface 1131. When the die is active When the surface 1131 has a protective layer, the protective layer 107 can protect the crystal grain active surface 1131 from infiltration of plastic encapsulation material, thereby protecting the crystal grain active surface 1131 from damage.

The presence of the protective layer 107 can also make the adhesion between the die 113 and the adhesive layer 121 stronger, so that during the plastic packaging process, the plastic packaging pressure is not likely to cause the die 113 to be on the carrier board. Position shift occurred on 117.

In a preferred embodiment, the Young's modulus of the protective layer 107 is in the range of 1000 to 20000 MPa, more preferably the Young's modulus of the protective layer 107 is in the range of 1000 to 10000 MPa; further preferably The Young's modulus of the protective layer 107 is 1000-7000, 4000-7000, or 4000-8000 MPa; in the best embodiment, the Young's modulus of the protective layer 107 is 5500 MPa.

In a preferred embodiment, the thickness of the protective layer 107 is in the range of 15-50 μm; more preferably, the thickness of the protective layer is in the range of 20-50 μm; in a preferred embodiment, the protective layer The thickness of 107 is 35 μm; in another preferred embodiment, the thickness of the protective layer 107 is 45 μm; in another preferred embodiment, the thickness of the protective layer 107 is 50 μm.

When the Young's modulus of the protective layer 107 is in the range of 1000-20000 MPa, on the one hand, the protective layer 107 is soft and has good flexibility and elasticity; on the other hand, the protective layer can provide sufficient support The force makes the protective layer 107 have sufficient support for the conductive layer on its surface. At the same time, when the thickness of the protective layer 107 is 15-50 μm, it is ensured that the protective layer 107 can provide sufficient buffer and support.

Especially in some types of wafers, it is necessary to use thin dies for packaging, and the conductive layer needs to reach a certain thickness to form a large electric flux. At this time, the thickness of the protective layer 107 is selected to range from 15 to 50 μm. The value range of the Young's modulus of the protective layer 107 is 1000-10000 MPa. The protective layer 107, which is soft and flexible, can form a buffer layer between the die 113 and the conductive layer, so that the conductive layer does not excessively compress the crystal during use of the wafer. The grain 113 prevents the crystal grain 113 from being broken by the pressure of the heavy conductive layer. At the same time, the protective layer 107 has sufficient material strength, and the protective layer 107 can provide sufficient support for the thick conductive layer.

When the Young's modulus of the protective layer 107 is 1000-20000 MPa, especially when the Young's modulus of the protective layer 107 is 4000-8000 MPa, when the thickness of the protective layer 107 is 20-50 μm, due to the The material properties of the protective layer 107 enable the protective layer 107 to effectively protect the crystal grains against the ejector pin pressure of the crystal grain transfer device during the subsequent crystal grain transfer process.

The die transfer process is a process of rearranging and bonding the cut and separated die 113 to the carrier 117 (reconstruction process). The die transfer process requires the use of a bonder machine, which includes a thimble , Using a thimble to lift up the die 113 on the wafer 100, use a bonder head to suck up the lifted die 113, transfer and bond it to the carrier 117.

In the process of pushing up the crystal grains 113 by the thimble, the crystal grains 113, especially the thin crystal grains 113, are brittle and easy to be broken by the pushing pressure of the thimble. The protective layer 100 with material characteristics can protect the brittle crystals in this process. The grain 113 can maintain the integrity of the grain 113 even under a relatively large lifting pressure.

In a preferred embodiment, the protective layer 107 is an organic/inorganic composite material layer including filler particles. Further, the filler particles are inorganic oxide particles; further, the filler particles are SiO ₂ particles; in one embodiment, the filler particles in the protective layer 107 are of two or more different types Inorganic oxide particles, such as SiO ₂ mixed with TiO ₂ particles. Preferably, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO ₂ particles, such as SiO ₂ mixed TiO ₂ particles, are spherical or spherical-like. In a preferred embodiment, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO ₂ particles, such as SiO ₂ mixed TiO ₂ particles, have a filling amount of more than 50%.

Organic materials have the advantages of easy operation and application. The die 113 to be encapsulated is made of inorganic materials such as silicon. When the protective layer 107 is made of organic materials alone, due to the difference between the material properties of organic materials and those of inorganic materials , It will make the packaging process more difficult and affect the packaging effect. The use of organic/inorganic composite materials in which inorganic particles are added to organic materials will modify the material properties of organic materials, making the materials have the characteristics of organic materials and inorganic materials.

In a preferred embodiment, when (T<Tg), the thermal expansion coefficient of the protective layer 107 ranges from 3 to 10 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 5. ppm/K; in a preferred embodiment; the thermal expansion coefficient of the protective layer 107 is 7 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 10 ppm/K.

In the next plastic packaging process, the die 113 with the protective layer 107 will expand and contract accordingly during the heating and cooling process of the plastic packaging process. When the thermal expansion coefficient of the protective layer 107 is in the range of 3-10 ppm/K The degree of expansion and contraction between the protective layer 107 and the die 113 remains relatively consistent. The connection interface between the protective layer 107 and the die 113 is not easy to produce interface stress, and it is not easy to damage the bond between the protective layer 107 and the die 113, so that after packaging The wafer structure is more stable.

The packaged chip often needs to undergo thermal and thermal cycles during use. The thermal expansion coefficient of the protective layer 107 ranges from 3 to 10 ppm/K and the die 113 has the same or similar thermal expansion coefficient. During the thermal and thermal cycles, the protective layer 107 It maintains a relatively consistent degree of expansion and contraction with the die 113, avoids the accumulation of interface fatigue at the interface between the protective layer 107 and the die 113, makes the packaged chip durable and prolongs the service life of the chip.

On the other hand, if the thermal expansion coefficient of the protective layer is too small, it is necessary to fill the composite material of the protective layer 107 with too many filler particles. While further reducing the thermal expansion coefficient, it will also increase the Young’s modulus of the material, making the protective layer material more effective. The flexibility is reduced, the rigidity is too strong, and the cushioning effect of the protective layer 107 is poor. It is optimal to limit the thermal expansion coefficient of the protective layer to 5-10 ppm/k.

In a preferred embodiment, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO ₂ particles, have a diameter of less than 3 μm. Preferably, the filler particles in the protective layer 107, such as inorganic oxide particles For example _{, the diameter of SiO 2} particles is between 1 and 2 μm.

Controlling the diameter of the filler particles to be less than 3μm facilitates the formation of a protective layer opening with smoother sidewalls on the protective layer 107 during the laser patterning process, so that the material can be fully filled during the conductive material filling process and avoid large sizes. The concave-convex protective layer opening sidewall 109c cannot be filled with conductive material on the back side of the sidewall shielded by the protrusion, which affects the conductive performance of the conductive filled via 111.

At the same time, the filling size of 1~2μm will expose the small particle size filler during the laser patterning process, so that the sidewall 109c of the opening of the protective layer will have a certain roughness. The sidewall with certain roughness will interact with the conductive material. The contact surface is larger, the contact is closer, and the conductive filled through hole 111 with good conductivity is formed.

The diameter of the filler described above is the average value of the particle diameter.

In a preferred embodiment, the value range of the tensile strength of the protective layer 107 is 20-50 MPa; in a preferred embodiment, the tensile strength of the protective layer 107 is 37 MPa.

Optionally, after the process of applying the protective layer 107 on the active surface 1001 of the wafer, the back surface 1002 of the wafer is polished to thin the wafer to a desired thickness.

Modern electronic equipment is small and lightweight, and the wafer has a trend of thinning. In this step, the wafer 100 sometimes needs to be thinned to a very thin thickness. However, the processing and transfer of the thin wafer 100 are difficult, and the grinding The thinning process is difficult, and it is often difficult to thin the wafer 100 to a desired thickness. When the surface of the wafer 100 has a protective layer 107, the protective layer 107 with material characteristics will support the wafer 100, reducing the difficulty of processing, transferring and thinning the wafer 100.

As shown in FIG. 3a, a protective layer opening 109 is formed on the surface of the protective layer 107.

A protective layer opening 109 is formed at a position corresponding to the protective layer 107 and the electrical connection point 103 on the active surface 1001 of the wafer to expose the electrical connection point 103 on the active surface 1001 of the wafer.

Preferably, there is a one-to-one correspondence between the protective layer openings 109 and the electrical connection points 103 on the active surface 1001 of the wafer.

Optionally, each of at least a part of the protective layer openings 109 corresponds to a plurality of the electrical connection points 103.

Optionally, at least a part of the electrical connection points 103 correspond to a plurality of the protective layer openings 109.

Optionally, at least a part of the protective layer opening 109 does not have a corresponding electrical connection point 103, or at least a part of the electrical connection point 103 does not have a corresponding protective layer opening 109.

Preferably, the protective layer opening is formed in a laser patterning manner.

In the process flow of forming the protective layer opening 109 by laser patterning, the conductive covering layer formed on the electrical connection point 103 in the electroless plating process step can protect the electrical connection point 103 on the active surface 1001 of the wafer from laser damage.

Preferably, as shown in the partial enlarged view in FIG. 3a, there is a gap between the lower surface of the protective layer opening 109a and the insulating layer 105, and/or the lower surface of the protective layer opening 109a is close to the electrical connection point 103 In a central location.

In a preferred embodiment, the shape of the protective layer opening 109 is such that the area of the upper surface 109b of the protective layer opening is larger than the area of the lower surface 109a of the protective layer opening, and the ratio of the area of the lower surface 109a of the protective layer opening to the upper surface 109b of the protective layer opening It is 60%~90%.

At this time, the slope of the sidewall 109c of the protective layer opening can facilitate the filling of the conductive material. During the filling process, the conductive material will be uniformly and continuously formed on the sidewall.

Optionally, as shown in FIG. 3b, the protective layer opening 109 is filled with a conductive medium, so that the protective layer opening 109 becomes a conductive filled through hole 111, and at least a part of the conductive filled through hole 111 is connected to the wafer The electrical connection points 103 on the active surface 1001 are electrically connected. The conductive filling through hole 111 is made to extend the electrical connection point 103 on the active surface of the wafer 1001 to the surface of the protective layer, and the protective layer is formed around the conductive filling through hole 111. The conductive medium can be gold, silver, copper, tin, aluminum and other materials or a combination of materials, or other suitable conductive materials through the use of PVD, CVD, sputtering, electrolytic plating, electroless plating processes, or other suitable metals The deposition process forms the conductive filling via 111 in the protective layer opening 109.

The filling of the conductive medium may be a complete filling of the protective layer opening 109, or only a layer of conductive material is formed in the protective layer opening 109, which can be electrically connected to the conductive layer. Correspondingly, the conductive filled via 111 is understood to mean that as long as the protective layer opening 109 has a conductive medium that can be electrically connected to the conductive layer, it is not necessary to completely fill the protective layer opening 109.

By pre-forming the protective layer opening 109 on the protective layer 107 and/or filling in a conductive medium, the position of the electrical connection point 103 on the active surface of the wafer 1001 can be accurately positioned through the protective layer opening 109, and the area of the protective layer opening 109 It can be made smaller, and the spacing between the openings can also be smaller, so that during the subsequent conductive layer formation step, the conductive traces can be closer, and there is no need to worry about the positional deviation of the electrical connection points 103.

As shown in FIG. 4, the wafer 100 on which the protective layer 107 has been applied is cut along the dicing path to obtain a plurality of crystal grains 113 formed with a protective layer. The crystal grains 113 have a crystal grain active surface 1131 and a crystal grain back surface. 1132.

In one embodiment, the wafer 100 with the protective layer 107 as shown in FIG. 2 is cut to form the die 113.

In one embodiment, the wafer 100 having the protective layer 107 and the protective layer opening 109 as shown in FIG. 3 a is cut to form the die 113.

In one embodiment, the wafer 100 with the protective layer 107 and the conductive filling via 111 as shown in FIG. 3b is cut to form the die 113.

Due to the material properties of the protective layer 107, in the dicing process of the wafer 100, the separated die 113 is free of burrs and die chips.

In one embodiment, before the step of dicing the wafer 100 to separate the die 113, the method further includes performing plasma surface treatment on the side of the wafer 100 with the protective layer 107 applied with the protective layer 107, The surface roughness is increased to increase the adhesion of the die 113 on the carrier plate 117 in the subsequent process, and it is not easy to cause the die movement of the die 113 under the molding pressure.

It is understandable that, if the process permits, the wafer 100 can be optionally cut into the die 113 to be packaged according to the specific actual situation, and then the active surface 1131 of each die 113 to be packaged is cut Form a protective layer.

As shown in FIG. 5a, a carrier board 117 is provided. The carrier board 117 has a carrier board front side 1171 and a carrier board back side 1172. The divided die 113 is arranged at a preset position on the carrier board front side 1171. The active surface 1131 of the die faces the carrier 117, and the back surface 1132 of the die is arranged away from the carrier 117.

The shape of the carrier 117 is: circle, triangle, quadrilateral or any other shape. The size of the carrier 117 can be a small-sized wafer substrate, or a rectangular carrier of various sizes, especially large sizes. The material of 117 can be metal, non-metal, plastic, resin, glass, stainless steel, etc. Preferably, the carrier plate 117 is a quadrilateral large-size panel made of stainless steel.

The carrier board 117 has a carrier board front side 1171 and a carrier board back side 1172, and the carrier board front side 1171 is preferably a flat surface.

In one embodiment, the die 113 is bonded and fixed on the carrier 117 by the adhesive layer 121.

The adhesive layer 121 may be formed on the front surface 1171 of the carrier board by laminating, printing, spraying, coating, or the like. In order to facilitate the separation of the carrier plate 117 and the die 113 completed by plastic packaging on the back in the subsequent process, the adhesive layer 121 preferably adopts a material that is easy to separate, for example, a thermal separation material is used as the adhesive layer 121.

Preferably, the position where the die 113 is arranged can be pre-marked on the carrier 117, and the mark can be formed on the carrier 117 by laser, mechanical engraving, etc., and the die 113 is also provided with an alignment mark , To aim and align with the pasting position on the carrier board 117 when pasting.

Optionally, as shown in FIG. 5b, in one packaging process, multiple, especially multiple dies 113a and 113b with different functions, two or more than two are shown in the figure, according to The actual product requirements are arranged on the carrier 117 and packaged. After the package is completed, it is cut into multiple packages; thus, one package includes multiple dies 113a and 113b to form a multi-chip module (Multi-chip module, MCM), and the positions of multiple dies 113a and 113b can be set freely according to actual product requirements.

The form of the die 113 arranged on the carrier 117 may be the die 113 cut into the wafer 100 with the protective layer 107 as shown in FIG. 2.

It can also be a die 113 cut into a wafer 100 having a protective layer 107 and a protective layer opening 109 as shown in FIG. 3a, and the die 113 formed with the protective layer 107 and the protective layer opening 109 After 113 is pasted on the adhesive layer 121 of the carrier board 117, the protective layer opening 109 is in a hollow state.

It can also be a die 113 cut into a wafer 100 having a protective layer 107 and a conductive filled through hole 111 as shown in FIG. 3b.

As shown in FIG. 6, a molding layer 123 is formed.

A plastic encapsulation layer 123 is formed on the periphery of the die 113 to be packaged and the exposed surface of the front surface 1171 of the carrier board or the adhesive layer 121. The plastic encapsulation layer 123 is used to completely encapsulate the front surface of the carrier board 1171 and the die 113 to be packaged to reconstruct a flat structure, so that after the carrier 117 is peeled off, the next step can be continued on the reconstructed flat structure的encapsulation steps.

The side of the plastic encapsulation layer 123 in contact with the front side 1171 of the carrier board or the adhesive layer 121 is defined as the front side 1231 of the encapsulation layer. The side of the plastic encapsulation layer 123 facing away from the front surface 1171 of the carrier board or the adhesive layer 121 is defined as the back surface 1232 of the encapsulation layer.

Preferably, the front surface 1231 of the plastic encapsulation layer and the back surface 1232 of the encapsulation layer are substantially flat and parallel to the front surface 1171 of the carrier board.

In one embodiment, the plastic encapsulation layer 123 is formed of an organic/inorganic composite material by compression molding.

Preferably, the thermal expansion coefficient of the plastic encapsulation layer 123 is 3-10 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the plastic encapsulation layer 123 is 5 ppm/K; in another preferred embodiment, the thermal expansion coefficient of the plastic encapsulation layer 123 is 5 ppm/K; The thermal expansion coefficient of 123 is 7 ppm/K; in another preferred embodiment, the thermal expansion coefficient of the plastic encapsulation layer 123 is 10 ppm/K.

Preferably, the plastic encapsulation layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients.

The thermal expansion coefficient of the plastic encapsulation layer 123 is selected to be 3-10 ppm/K and the thermal expansion coefficient is the same or similar to that of the protective layer 107. During the heating and cooling process of the plastic encapsulation process, the expansion and contraction between the protective layer 107 and the plastic encapsulation layer 123 The two materials are not prone to interface stress. The low thermal expansion coefficient makes the thermal expansion coefficients of the plastic encapsulation layer, the protective layer and the die close, so that the interface of the plastic encapsulation layer 123, the protective layer 107 and the die 113 are tightly combined to avoid the generation of interfaces. Layer separation.

The packaged chip often needs to undergo a cold and heat cycle during use. Since the thermal expansion coefficients of the protective layer 107, the plastic encapsulation layer 123 and the die 113 are similar, the protective layer 107, the plastic encapsulation layer 123 and the die 113 are The interface fatigue is small, and the interface gap between the protective layer 107, the plastic encapsulation layer 123 and the die 113 is not easy to appear, so that the service life of the chip is prolonged, and the chip can be applied in a wide range of fields.

The difference in thermal expansion coefficient between the die 113 and the plastic encapsulation layer 123 will also cause the panel element after plastic encapsulation to warp. Due to the warping phenomenon, it is difficult to accurately position the die 113 in the panel element in the subsequent formation process of the conductive layer. The position has a great influence on the formation process of the conductive layer.

Especially, in the large panel packaging process, due to the large size of the panel, even a slight panel warping will cause the crystal grains of the outer four peripheral parts of the panel far away from the center to have a larger size than before molding. Therefore, in the large-scale panel packaging process, solving the warpage problem becomes one of the keys to the entire process. The warpage problem even limits the enlargement of the panel size and becomes a technical barrier in the large-scale panel packaging process.

The thermal expansion coefficients of the protective layer 107 and the plastic encapsulation layer 123 are limited in the range of 3-10 ppm/K, and preferably the plastic encapsulation layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients, which can be effective Avoid the warpage of panel components, and realize the packaging process of large-scale panels.

At the same time, during the molding process, due to the molding pressure exerting pressure on the back of the die 113, this pressure is easy to press the die 113 into the adhesive layer 121, so that the die 113 is trapped in the process of forming the molding layer 123. In the adhesive layer 121, after the molding layer 123 is formed, the die 113 and the front surface 1231 of the molding layer are not on the same plane. The surface of the die 113 protrudes beyond the front surface 1231 of the molding layer to form a stepped structure. During the formation of the conductive layer, the conductive trace 125 also has a stepped structure correspondingly, which makes the package structure unstable.

When the active surface 1131 of the die has a protective layer 107 with material characteristics, it can play a buffering effect under the molding pressure to prevent the die 113 from sinking into the adhesive layer 121, thereby avoiding the generation of a stepped structure 1231 on the front side of the molding layer.

As shown in FIG. 7a, the thickness of the molding layer 123 can be reduced by grinding or polishing the back surface 1232 of the molding layer.

In one embodiment, as shown in FIG. 7b, the thickness of the plastic encapsulation layer 123 can be reduced to the back side 1132 of the die 113, thereby exposing the back side 1132 of the die. The packaged wafer structure is shown in Figure 13b.

As shown in FIG. 8, the carrier plate 117 is peeled off to expose the front surface 1231 of the plastic encapsulation layer and the protective layer 107.

In one embodiment, when the form of the die 113 arranged on the carrier plate 117 is the die 113 having a protective layer 107 and a protective layer opening 109 as shown in FIG. 3a, the carrier plate is peeled off 1172, the protective layer opening 109 will also be exposed.

In one embodiment, when the form of the die 113 arranged on the carrier board 117 is as shown in FIG. 2 having the protective layer 107 but no protective layer has been formed on the protective layer 107 For the die 113 cut into the wafer 100 with the opening, after the carrier 117 is peeled off, there is a step of forming a protective layer opening on the protective layer 107 on the die 113 covered by the plastic encapsulation layer 123.

In one embodiment, when the form of the die 113 arranged on the carrier 117 is the die 113 cut from the wafer 100 with the protective layer 107 and the conductive filling via 111 as shown in FIG. 3b, The conductive filled via 111 will be exposed.

The structure of the plastic encapsulation layer 123 coated with the die 113 after the carrier 117 is separated is defined as the panel module 150.

9 and 10 show an embodiment of the process of forming conductive filling vias on the die 113 in the plastic encapsulation layer 123 and patterning the conductive layer.

When the protective layer 107 covering the surface of the die 113 in the plastic encapsulation layer 123 has not formed a conductive filling through hole 111, the protective layer opening 109 is filled with a conductive medium, so that the protective layer opening 109 becomes a conductive filling through hole 111. The conductive filling through hole 111 is electrically connected to the electrical connection point 103 on the active surface 1001 of the wafer. The conductive filling through hole 111 extends the electrical connection point 103 on the active surface of the wafer 1001 to the surface of the protective layer, and the protective layer is formed around the conductive filling through hole 111. The conductive medium can be gold, silver, copper, tin, aluminum and other materials or a combination of materials, or other suitable conductive materials through the use of PVD, CVD, sputtering, electrolytic plating, electroless plating processes, or other suitable metals The deposition process forms the conductive filling via 111 in the protective layer opening 109.

The filling of the conductive medium may be a complete filling of the protective layer opening 109, or only a layer of conductive material is formed in the protective layer opening 109, which can be electrically connected to the conductive layer. Correspondingly, the conductive filled via 111 is understood to mean that as long as the protective layer opening 109 has a conductive medium that can be electrically connected to the conductive layer, it is not necessary to completely fill the protective layer opening 109.

A conductive trace 125 is formed on the die 113 in the plastic encapsulation layer 123; at least a part of the conductive trace 125 is formed on the surface of the protective layer 107 on the active surface 1131 of the die, and at least a part of the conductive filling The through hole 111 is electrically connected; in one embodiment, the conductive trace 125 extends along the surface of the protective layer 107 and the front surface 1231 of the plastic encapsulation layer, and extends to the edge of the chip package body when the package is completed. The packaged chip structure is shown in the figure Shown in 13b. The conductive trace 125 extends to the edge of the package body. At this time, the conductive trace 125 wraps and connects the interface between the protective layer 107 and the plastic encapsulation layer 123, which increases the stability of the chip structure after packaging.

The conductive trace 125 can be one or more layers of copper, gold, silver, tin, aluminum and other materials or a combination of materials, or other suitable conductive materials through the use of PVD, CVD, sputtering, electrolytic plating, and electroless plating processes. , Or other suitable metal deposition process.

Preferably, the conductive filled via 111 and the conductive trace 125 are performed in the same conductive layer forming step.

Of course, alternatively, the conductive filled via 111 is formed first, and then the conductive trace 125 is formed.

Figure 10 shows that conductive studs 127 are formed on the pads or connection points of the conductive traces 125; the shape of the conductive studs 127 can be round or other shapes such as oval, square, linear, etc. . The conductive bump 127 can be one or more layers of copper, gold, silver, tin, aluminum and other materials or a combination of materials, or other suitable conductive materials through the use of PVD, CVD, sputtering, electrolytic plating, and electroless plating processes. , Or other suitable metal deposition process.

The conductive layer is composed of conductive traces 125 and/or conductive bumps 127, and the conductive layer may be one layer or multiple layers. The conductive layer may have a fan-out RDL function.

As shown in FIGS. 11a and 11b, a dielectric layer 129 is formed on the conductive layer.

One or more dielectric layers 129 are formed on the surface of the conductive layer by laminating, coating, spraying, printing, molding, and other suitable methods.

The dielectric layer 129 can be BCB (benzocyclobutene), PI (polyimide), PBO (polybenzoxazole), ABF, silicon dioxide, silicon nitride, silicon oxynitride, tantalum pentoxide , Alumina, polymer matrix dielectric film, organic polymer film; it can also be organic composite material, resin composite material, polymer composite material, polymer composite material, such as epoxy resin with filler, ABF, or Other polymers suitable for fillers; other materials with similar insulating and structural properties. In a preferred embodiment, the dielectric layer 129 is ABF. The dielectric layer 129 plays a role of protecting the conductive layer and insulating. In one embodiment, the applied thickness of the dielectric layer 129 is thicker than the thickness of the conductive layer, and the conductive layer is exposed through a grinding process; in another embodiment, the applied thickness of the dielectric layer 129 is the same as the thickness of the conductive layer, After the dielectric layer 129 is applied, the conductive layer is just exposed.

In one embodiment, the steps of FIG. 9 to FIG. 11 b are repeated to form a multi-layer conductive layer on the crystal grain active surface 1131 of the crystal grain 113.

Return to the steps in Figure 9 to Figure 11b. In an embodiment, the step of forming the conductive layer may be: A conductive trace 125 is formed on the active surface 1131 of the die 113; Use lamination, coating, spraying, printing, molding and other suitable methods to form one or more dielectric layers 129 on the surface of the conductive trace 125. The height of the dielectric layer 129 is higher than the height of the conductive trace 125, and the conductive The trace 125 is completely enclosed in the dielectric layer 129; and An opening is formed on the dielectric layer 129 at a position corresponding to the bonding pad or the connection point of the conductive trace 125, and a conductive bump 127 is formed in the opening.

In another embodiment, the conductive bump 127 may not be formed in the opening, so that the bonding pads or the connection points of the conductive trace 125 of the completed package are exposed from the opening.

In a preferred embodiment, after the application step of the dielectric layer 129, the thickness of the outermost conductive layer is reduced by etching to form a groove 131 on the outer surface of the dielectric layer 129. The packaged wafer structure is shown in FIG. 13b .

Optionally, as shown in FIG. 11b, in one packaging process, multiple, especially multiple dies 113a and 113a with different functions, two or more than two are shown in the figure. As a multi-chip package module, the patterned design of the conductive layer of the multiple dies 113a and 113b is designed according to the electrical connection requirements of the actual product. The packaged wafer structure is shown in Figure 13c.

As shown in Figure 12, the packaged monomer is cut and separated to form a packaged wafer, which can be cut by machine or laser.

13a, 13b and 13c are schematic diagrams of the chip package structure.

FIG. 13a is a schematic diagram of a chip packaging structure obtained according to a packaging method provided by an exemplary embodiment of the present disclosure.

As shown in the figure, a chip package structure includes a die 113, the die 113 includes a die active surface 1131 and a die back 1132, and the die active surface 1131 includes an electrical connection point 103 and an insulating layer 105; The protective layer 107 is formed on the active surface 1131 of the crystal grain, and conductive filled through holes 111 are formed in the protective layer 107, at least a part of the conductive filled through holes 111 and at least a part of the electrical connection points 103 are electrically connected, It is used to draw at least a part of the electrical connection points 103 from the active surface 1131 of the die; a plastic encapsulation layer 123, the plastic encapsulation layer 123 is used to encapsulate the die 113; a conductive layer is formed at least partly on the protection On the surface of the layer 107, the conductive layer is electrically connected to at least a part of the conductive filled through holes 111; the dielectric layer is formed on the conductive layers 125, 127.

In an embodiment, the Young's modulus of the protective layer 107 is any of the following numerical ranges or values: 1000~20000 MPa, 1000~10000 MPa, 4000~8000 MPa, 1000~7000 MPa, 4000~7000 MPa, 5500 MPa.

In one embodiment, the material of the protective layer 107 is an organic/inorganic composite material.

In an embodiment, the thickness of the protective layer 107 is any of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, 50 μm.

In an embodiment, the thermal expansion coefficient of the protective layer 107 is any of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In an embodiment, the thermal expansion coefficient of the plastic encapsulation layer 123 is any of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In one embodiment, the protective layer 107 and the plastic encapsulation layer 123 have the same or similar thermal expansion coefficients.

In an embodiment, the protective layer 107 includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm or the diameter of the inorganic filler particles is 1 to 2 μm.

In one embodiment, the ratio of the area of the lower surface 111a of the conductive filled via to the area of the upper surface 111b of the conductive filled via is 60% to 90%.

In one embodiment, the conductive filled via 111 is formed by filling the protective layer opening 109 with a conductive medium.

In one embodiment, a conductive covering layer is formed on the electrical connection point 103.

In one embodiment, as shown in the partial enlarged view in FIG. 13a, there is a gap between the lower surface 111a of the conductive filled via and the insulating layer 105.

In one embodiment, as shown in the partial enlarged view in FIG. 13a, the lower surface 111a of the conductive filled via is located at a position close to the center of the electrical connection point 103.

In one embodiment, the conductive layer includes conductive traces 125 and/or conductive bumps 127; wherein: at least a part of the conductive traces 125 closest to the active surface 1131 of the die is formed on the surface of the protective layer 107, It is electrically connected to the conductive filled via 111.

The conductive bump 127 is formed on the bonding pad or the connection point of the conductive trace 125.

The conductive layer may be one layer or multiple layers.

In one embodiment, as shown in FIG. 13b, at least a part of the conductive trace 125 closest to the die active surface 1131 is formed on the front surface 1231 of the plastic encapsulation layer and extends to the edge of the package body.

In another embodiment, as shown in FIG. 13 b, the back surface 1132 of the die is exposed from the molding layer 123.

In another embodiment, as shown in FIG. 13b, the surface of the dielectric layer 129 has a groove at a position corresponding to the conductive layer.

In one embodiment, as shown in FIG. 13c, the package structure includes a plurality of dies 113, and the plurality of dies 113 are electrically connected according to the product design. Optionally, the plurality of dies 113 are dies with different functions to form a multi-chip module.

Figure 14a shows a schematic diagram of the packaged chip in use. During use, the packaged chip is connected to the circuit board or substrate 161 through solder 160, and then connected with other circuit elements.

When the surface of the dielectric layer 129 of the package chip has the groove 131, the solder 160 can be connected stably and not easily moved.

Fig. 14b shows a schematic diagram of the packaged chip module in use. During use, the packaged chip module is connected to the circuit board or substrate 161 through solder 160, and then connected with other circuit elements.

The specific embodiments described above are intended to further describe the technical solutions and technical effects of the present disclosure in detail. However, those skilled in the art will understand that the specific embodiments described above are not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the inventive idea of the present disclosure shall be included in the protection scope of the present disclosure.

100: Wafer 1001: Wafer active surface 1002: backside of wafer 103: electrical connection point 105: insulating layer 107: Protective layer 109: Protective layer opening 109a: The lower surface of the protective layer opening 109b: The upper surface of the protective layer opening 109c: Sidewall of protective layer opening 111: Conductive filled vias 111a: Conductive filled via bottom surface 111b: Conductive filling the upper surface of the via 113: Die 113a: Die 113b: Die 1131: Active surface of crystal grain 1132: Die back 117: Carrier Board 1171: Front of the carrier board 1172: back of the carrier board 121: Adhesive layer 123: Plastic layer 1231: front side of plastic encapsulation layer 1232: The back of the plastic layer 125: conductive trace 127: conductive bump 129: Dielectric layer 131: Groove 150: Panel Module 160: Solder 161: Substrate

1 to 12 are the processes of the chip packaging method proposed according to the exemplary embodiment of the present disclosure; FIG. 1 is a schematic diagram of a semiconductor wafer according to an exemplary embodiment of the present disclosure; 2 is a schematic diagram of a semiconductor wafer after a protective layer is applied according to an exemplary embodiment of the present disclosure; FIG. 3a is a schematic diagram of a semiconductor wafer with openings in a protective layer according to an exemplary embodiment of the present disclosure; FIG. 3b is a schematic diagram of a semiconductor wafer in which conductive filled vias are formed according to an exemplary embodiment of the present disclosure; 4 is a schematic diagram of dicing a semiconductor wafer to form a die with a protective layer according to an exemplary embodiment of the present disclosure; Fig. 5a is a schematic diagram of die sticking on a carrier board according to an exemplary embodiment of the present disclosure; FIG. 5b is a schematic diagram of a die combination on a carrier board according to an exemplary embodiment of the present disclosure; Fig. 6 is a schematic diagram of forming a plastic encapsulation layer on a carrier plate according to an exemplary embodiment of the present disclosure; Fig. 7a is a schematic diagram of reducing the thickness of a plastic encapsulation layer according to an exemplary embodiment of the present disclosure; FIG. 7b is a schematic diagram of thinning the plastic encapsulation layer to the back of the exposed die according to an exemplary embodiment of the present disclosure; FIG. 8 is a schematic diagram of peeling off the carrier board and the adhesive layer according to an exemplary embodiment of the present disclosure; FIG. 9 is a schematic diagram of forming conductive filled vias and conductive traces on a panel module according to an exemplary embodiment of the present disclosure; FIG. 10 is a schematic diagram of forming conductive bumps on a panel module according to an exemplary embodiment of the present disclosure; 11a and 11b are schematic diagrams of forming a dielectric layer on a panel module according to an exemplary embodiment of the present disclosure; FIG. 12 is a schematic diagram of cutting a panel module to form a packaged wafer according to an exemplary embodiment of the present disclosure; FIG. 13a is a schematic diagram of a chip packaging structure obtained by using the above-mentioned packaging method according to an exemplary embodiment of the present disclosure; FIG. 13b is a schematic diagram of a chip packaging structure obtained by using the above packaging method according to an exemplary embodiment of the present disclosure; FIG. 13c is a schematic diagram of a chip module packaging structure obtained by using the above packaging method according to an exemplary embodiment of the present disclosure; Fig. 14a is a schematic diagram of a packaged chip in use according to an exemplary embodiment of the present disclosure; Fig. 14b is a schematic diagram of a packaged chip module in use according to an exemplary embodiment of the present disclosure.

103: electrical connection point

105: insulating layer

107: Protective layer

111: Conductive filled vias

113: Die

1131: Active surface of crystal grain

1132: Die back

123: Plastic layer

1231: front side of plastic encapsulation layer

1232: The back of the plastic layer

125: conductive trace

127: conductive bump

129: Dielectric layer

131: Groove

Claims (16)

A chip packaging structure, including: At least one crystal grain; A protective layer is located on one side of the active surface of the crystal grain, and the side surface of the protective layer is flush with the side surface of the crystal grain. A conductive filled through hole is formed in the protective layer, and at least a part of the conductive filled through hole is electrically connected Point electrical connection; A plastic encapsulation layer, the plastic encapsulation layer is used to encapsulate the die; A conductive layer formed at least partly on the surface of the protective layer, and at least a part of the conductive layer is electrically connected to the conductive filled via; and A dielectric layer formed on the conductive layer; Among them, the Young's modulus of the conductive layer is in the range of 1000 to 20000 MPa. According to the chip packaging structure of claim 1, the material of the protective layer is an organic/inorganic composite material. In the chip package structure according to claim 1, the thickness of the protective layer is in the range of 15-50 μm. In the chip package structure described in claim 1, the thermal expansion coefficient of the protective layer is in the range of 3-10 ppm/K. In the chip package structure described in claim 1, the thermal expansion coefficient of the plastic encapsulation layer is in the range of 3-10 ppm/K. In the chip package structure according to claim 1, the protective layer and the plastic encapsulation layer have the same or similar thermal expansion coefficient. According to the chip packaging structure of claim 2, the protective layer includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm. According to the chip package structure of claim 1, the conductive filled through hole is formed by filling the protective layer with a conductive medium, and the conductive filled through hole has a conductive filled through hole lower surface and a conductive filled through hole upper surface, and the conductive filled through hole The ratio of the area of the lower surface of the through hole to the upper surface of the conductive filled through hole is 60% to 90%. In the chip package structure according to claim 8, there is a gap between the lower surface of the conductive filled through hole and the insulating layer, and/or the lower surface of the conductive filled through hole is located at a position close to the center of the electrical connection point. The chip package structure according to any one of claims 1 to 9, wherein the conductive layer includes conductive traces and/or conductive bumps; Wherein, at least a part of the conductive trace closest to the active surface of the die is formed on the surface of the protective layer, and is electrically connected to the conductive filled via. According to the chip package structure according to any one of claims 1 to 9, a conductive covering layer is formed on the electrical connection point. In the chip package structure according to claim 10, at least a part of the conductive trace closest to the active surface of the die is formed on the front surface of the plastic encapsulation layer and extends to the edge of the package body. According to the chip package structure according to any one of claims 1 to 9, the back surface of the die is exposed from the plastic encapsulation layer. In the chip package structure according to any one of claims 1 to 9, the surface of the dielectric layer has a groove at a position corresponding to the conductive layer. According to the chip package structure according to any one of claims 1 to 9, the at least one die is a plurality of die, and the plurality of die is electrically connected according to a product design. According to the chip package structure according to any one of claims 1 to 9, the plurality of dies are dies with different functions to form a multi-chip module.

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