TWI829392B - Chip packaging method and chip structure - Google Patents

Abstract

The present disclosure provides a chip package for power modules including at least one semiconductor die; a driver circuit for controlling the at least one semiconductor die; a protective layer formed on a die active surface of the at least one die and a driver active surface of the driver circuit; a metal unit having at least one metal feature; and a molding layer for encapsulating the at least one semiconductor die, the driver circuit, the protective layer and metal unit. The chip package is connected with an external circuit from the active surface side via the at least one metal feature. The present disclosure also provides a method of making the chip packages for power modules.

Description

Chip packaging method and chip structure

The present disclosure relates to the field of semiconductor technology, and in particular to a chip packaging method and chip structure with an embedded lead frame.

Panel-level packaging involves cutting a wafer to separate many dies, arranging and pasting the dies on a carrier board, and packaging many dies simultaneously in the same process flow. As a technology that has emerged in recent years, panel-level packaging has received widespread attention. Compared with traditional wafer-level packaging, panel-level packaging has the advantages of high production efficiency, low production cost, and is suitable for mass production.

At the same time, the demand for chip packaging in today's power modules has increased significantly. However, traditional chip packaging still uses copper clips (Cu clips) and wire bonding (wire bonding), so there are many shortcomings. For example, the bulky size of copper clips makes it difficult to thin traditional chip packages. Moreover, in traditional chip packaging, the copper clips located above the die may cause the die to crack due to their weight. This shortcoming becomes more severe when thinner dies are required for power modules. In addition, wire bonding can result in poor electrical and thermal performance of conventional chip packages.

Therefore, this application discloses corresponding chip structures and packaging wafers to solve the shortcomings of traditional chip packaging. In particular, chip structures and packaged wafers with embedded lead frames have better electrical and thermal properties for power modules.

The present disclosure aims to provide a chip package for a power module, including at least one die having an opposite die active surface and a die backside, wherein the at least one die has a thinner thickness for reducing Resistor when used as a power module; a drive circuit for controlling the at least one die, which has an opposite drive active surface and a drive backside; a protective layer formed on the active surface of the die and the drive active surface, It has a plurality of protective layer openings for exposing the die active surface and the driving active surface from the protective layer; a metal unit, the metal unit includes at least one metal feature, wherein the at least one metal feature has At least one connection pad, the at least one connection pad has an opposite connection pad front side and a connection pad back side; and a plastic encapsulation layer for encapsulating the at least one die, the driving circuit, the protective layer and the metal unit. The chip package is connected to an external circuit via at least one metal feature.

In some embodiments, the at least one die includes a first die and a second die having a first die active surface and a second die active surface respectively, wherein the first die, the second die The die and the drive circuit are surrounded by the metal unit, and the first die active surface, the second die active surface and the drive active surface are substantially flush.

In some embodiments, the chip package further includes a first conductive structure formed on at least one metal feature of the metal unit, a protective layer and an encapsulation layer, wherein the first conductive structure is connected to the die active and a driving active surface for connecting the at least one die and the driving circuit to the metal unit.

In some embodiments, the first conductive structure has a plurality of conductive filled vias connected to the die active surface and the drive active surface, and at least one metal feature, a protective layer and a molding layer in the metal unit A panel-level conductive layer is formed on the protective layer, wherein the conductive filled via hole is formed by filling the protective layer opening with conductive material.

In some embodiments, the wafer package further includes a second conductive structure formed on at least one metal feature of the metal unit and the molding layer, the second conductive structure and the first conductive structure being formed on the at least one wafer. The opposite side of the particle, wherein the second conductive structure is connected to the first conductive structure by at least one metallic feature of the metal unit.

In some embodiments, the first conductive structure and the second conductive structure have substantially the same weight for balancing the chip package from the active side of the die and the backside of the die.

In some embodiments, the second conductive structure is in direct contact with the die backside of at least one die for electrically grounding the chip package backside.

In some embodiments, the chip packaging further includes forming at least one gap in the molding layer for exposing the backside of the die from the molding layer, wherein the at least one gap is filled with a conductive medium to form The conductive filling gap is used for connecting with the second conductive structure.

In some embodiments, the chip package further includes an additional molding layer formed on the backside of the die of the at least one die and encapsulated by the molding layer; and at least one gap in the additional molding layer, It is used to expose the back side of the die from the plastic encapsulation layer, and fill the at least one gap with a conductive medium to form a conductive filling gap for connecting with the second conductive structure.

In some embodiments, the chip package further includes a first dielectric layer for encapsulating the first conductive structure, wherein the first conductive structure is exposed from the first dielectric layer for communicating with the external circuits are connected; and a second dielectric layer is used to encapsulate the second conductive structure, wherein the second conductive structure is exposed from the second dielectric layer and is used to be connected to an external component.

The present disclosure also aims to provide a wafer structure, including at least one die having an opposite active surface of the die and a backside of the die; a protective layer formed on the active surface of the die has a plurality of protective layer openings for The die active surface is exposed from the protective layer; a metal unit, the metal unit includes at least one metal feature, wherein the at least one metal feature has at least one connection pad, and the at least one connection pad has an opposite The front side of the connection pad and the back side of the connection pad; a plastic sealing layer for encapsulating the die, protective layer and metal unit; and a first conductive structure formed on at least one metal feature, protective layer and plastic sealing layer of the metal unit , wherein the first conductive structure is connected to the active surface of the die for connecting the at least one die to the metal unit. The chip structure is connected to an external circuit via at least one metallic feature.

In some embodiments, the external circuit includes a printed circuit board, and the first conductive structure is in direct contact with the printed circuit board for directly connecting the at least one die to the printed circuit board.

In some embodiments, the wafer structure further includes a second conductive structure formed on at least one metal feature of the metal unit and the molding layer, and the second conductive structure and the first conductive structure are formed on the at least one wafer structure. The opposite side of the die, wherein the second conductive structure is connected to the at least one die through the first conductive structure and at least one metallic feature of the metal unit for electrically back-grounding the chip structure.

In some embodiments, the second conductive structure is in direct contact with the die backside of at least one die for transferring heat from the die backside to out of the wafer structure.

In some embodiments, the first conductive structure and the second conductive structure have substantially the same weight for balancing the chip package from the active side of the die and the back side of the die.

The present disclosure is also intended to provide a manufacturing method of a chip package for a power module, including providing at least one die having an opposite die active surface and a die backside, wherein the die active surface of the at least one die The thickness between the die and the backside of the die is thin to reduce the resistance of the power module; a driving circuit for controlling the at least one die is provided, which has an opposite driving active surface and a driving backside; in the crystal A protective layer is formed on the grain active surface and the driving active surface, which has a plurality of protective layer openings for exposing the grain active surface and the driving active surface from the protective layer; a metal unit is placed to surround the at least one die and drive circuit, wherein the metal unit has at least one metal feature, the at least one metal feature has at least one connection pad, the at least one connection pad has an opposite connection pad front side and a connection pad back side; forming a plastic encapsulation layer, Used to encapsulate the at least one die, drive circuit, protective layer and metal unit; and connect the chip package to an external circuit through at least one metal feature of the metal unit.

In some embodiments, the manufacturing method further includes forming a first conductive structure so as to be in direct contact with the front surface of the connection pad of the at least one connection pad, the second surface of the protective layer of the protective layer, and the front surface of the plastic sealing layer, The front side of the connection pad, the second side of the protective layer and the front side of the plastic sealing layer are substantially flush.

In some embodiments, the manufacturing method further includes forming a second conductive structure in direct contact with the back side of the connection pad of the at least one connection pad and the back side of the plastic encapsulation layer, wherein the back side of the plastic encapsulation layer and the front side of the plastic encapsulation layer are opposite to each other. .

In some embodiments, the manufacturing method further includes forming at least one gap in the molding layer for exposing the backside of the at least one die; and filling the at least one gap with conductive material. The dielectric is connected to the second conductive structure to form a conductive filling gap.

In some embodiments, the manufacturing method further includes forming a first dielectric layer encapsulating the first conductive structure, wherein the first conductive structure is exposed from the first dielectric layer for communicating with the external The circuits are connected; and a second dielectric layer encapsulating the second conductive structure is formed, wherein the second conductive structure is exposed from the second dielectric layer for connection with an external component.

In order to make the technical solutions of the present disclosure clearer and the technical effects more clear, the following is a detailed and specific description and explanation of the preferred embodiments of the present disclosure in conjunction with the drawings. It should not be understood that the following description is the only implementation form of the present disclosure, or that it is a complete description of the present disclosure. Public restrictions.

FIG. 1 is a flowchart of a chip packaging method 10 according to an embodiment of the present disclosure. 2 to 25 are schematic flow diagrams of a panel assembly manufactured according to the chip packaging method in FIG. 1 .

Referring to Figure 1, the chip packaging method 10 of the present disclosure includes the following steps:

Step S101: Provide wafer 100.

As shown in Figure 2, at least one wafer 100 is provided. The wafer 100 has a wafer active surface 1001 and a wafer backside 1002. The wafer 100 includes a plurality of wafer grains 113, wherein the active surface of each wafer grain constitutes the wafer active surface 1001. The active surface of each grain in 100 forms a series of active components and passive components through a series of processes such as doping, deposition, and etching. Active components include diodes, triodes, etc., and passive components include voltage components, Capacitors, resistors, inductors, etc., these active components and passive components are connected using connecting wires to form a functional circuit, thereby realizing various functions. The wafer active surface 1001 also includes electrical connection points 103 for leading out functional circuits and an insulating layer 105 for protecting the electrical connection points 103 .

Step S102: Apply the protective layer 107 on the active surface 1001 of the wafer.

Figures 3a and 3b show the process steps of optionally applying a protective layer 107 on the active surface of the wafer 1001:

As shown in Figure 3a, a protective layer 107 is applied on the active surface 1001 of the wafer.

Preferably, the protective layer 107 is applied to the active surface 1001 of the wafer by lamination.

Optionally, before the step of applying the protective layer 107 on the wafer active surface 1001, physical and/or chemical treatment is performed on the wafer active surface 1001 and/or the side where the protective layer 107 is applied to the wafer 100, so that the protective layer 107 and The bonding between the wafers 100 is tighter. The treatment method can optionally be plasma surface treatment to roughen the surface to increase the bonding area and/or chemical accelerating modifier treatment, introducing accelerating modification groups between the wafer 100 and the protective layer 107, for example, simultaneously with an affinity organic and surface modifiers with affinity for inorganic groups to increase the adhesion between organic/inorganic interface layers.

As shown in Figure 3b, a protective layer opening 109 is formed on the surface of the protective layer 107.

A protective layer opening 109 is formed in the protective layer 107 at a position corresponding to the electrical connection point 103 on the active surface 1001 of the wafer to expose the electrical connection point 103 on the active surface 1001 of the wafer.

Preferably, there is a one-to-one correspondence between the protective layer opening 109 and the electrical connection point 103 on the active surface 1001 of the wafer.

Optionally, each of at least a portion of the protective layer openings 109 corresponds to a plurality of electrical connection points 103 .

Optionally, at least a portion of the electrical connection points 103 correspond to a plurality of protective layer openings 109 .

Optionally, at least a portion of the protective layer openings 109 do not have corresponding electrical connection points 103 , or at least a portion of the electrical connection points 103 do not have corresponding protective layer openings 109 .

The protective layer opening 109 is formed by laser patterning or photolithography patterning.

If the protective layer opening 109 is formed by laser patterning, preferably, before applying the protective layer 107 on the active surface of the wafer 1001, an electroless plating process step is performed on the active surface of the wafer 1001 to form a conductive covering on the electrical connection point 103. layer. Optionally, the conductive covering layer is one or more layers of Cu, Ni, Pd, Au, Cr; preferably, the conductive protective layer is a Cu layer; the thickness of the conductive protective layer is preferably 2-3 μm. The conductive cover is not shown in the figure. The conductive covering layer can protect the electrical connection points 103 on the active surface 1001 of the wafer from laser damage in the subsequent step of forming the protective layer opening 109 .

Preferably, as shown in the partial enlarged view in FIG. 3 b , there is a gap between the lower surface 109 a of the protective layer opening and the insulating layer 105 . Preferably, the lower surface 109 a of the protective layer opening is located near the center of the electrical connection point 103 .

In a preferred embodiment, the shape of the protective layer opening 109 is such that the area of the upper surface 109b of the protective layer opening is larger than the area of the lower surface 109a of the protective layer opening, and the area ratio of the lower surface 109a of the protective layer opening to the upper surface 109b of the protective layer opening is is 60%~90%.

At this time, the slope of the protective layer opening sidewall 109c can facilitate filling of the conductive material. During the filling process, the conductive material will be uniformly and continuously formed on the sidewall.

Alternatively, the protective layer opening 109 may not be formed temporarily, and the protective layer opening 109 may be formed on the protective layer after the process of peeling off the carrier board.

Optionally, a conductive medium is filled in the protective layer opening 109 so that the protective layer opening 109 becomes a conductive filled through hole 124 . At least a portion of the conductive filled vias 124 are connected to the electrical connection points 103 on the active surface 1001 of the wafer. The conductive filled through hole 124 is caused to extend the electrical connection point 103 on the active surface 1001 of the chip to the protective layer surface in one direction, and the protective layer is formed around the conductive filled through hole 124 . The conductive medium can be gold, silver, copper, tin, aluminum and other materials or combinations thereof, or other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electrodeless plating processes, or other suitable The metal deposition process forms conductive filled vias 124 in the protective layer openings 109 .

Figures 4a to 4c show another process step of optionally applying a protective layer 107 on the active surface 1001 of the wafer:

As shown in Figure 4a, a wafer conductive layer 130 is formed on the wafer active surface 1001.

The wafer conductive layer 130 is the wafer conductive trace 106 . The wafer conductive traces 106 can be made of copper, gold, silver, tin, aluminum or other materials or combinations thereof, or other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electrodeless plating processes, or Other suitable metal deposition processes may be used.

At least a portion of the wafer conductive traces 106 are connected to at least a portion of the electrical connection points 103 on the wafer active surface 1001 .

Optionally, the wafer conductive traces 106 interconnect and lead out the plurality of electrical connection points 103 in at least a part of the wafer active surface 1001. For the die formed thereby, please refer to the die schematic diagram A in FIG. 6b.

The formation of the wafer conductive traces 106 can reduce the number of protective layer openings 109 formed in the subsequent process. The wafer conductive traces 106 are used to first interconnect the multiple electrical connection points 103 with each other according to the circuit design, eliminating the need to install the wafer conductive traces 103 at each electrical connection point. 103 needs to form protective layer opening 109.

Optionally, the wafer conductive traces 106 separately lead out at least a portion of the electrical connection points 103 on the wafer active surface 1001. For the die formed thereby, please refer to the die schematic diagram B in FIG. 6b.

The formation of the wafer conductive traces 106 helps to reduce the difficulty of the subsequent formation of the protective layer opening 109. Due to the existence of the wafer conductive traces 106, the lower surface 109a of the protective layer opening can have a larger area. Correspondingly, it can Making the protective layer opening 109 have a larger area, especially on a wafer 100 with smaller exposed electrical connection points 103, makes it possible to form the protective layer opening 109.

Although not shown in the figure, it can be understood that the wafer conductive traces 106 individually lead out a portion of the electrical connection points 103 on the wafer active surface 1001 and interconnect another portion of the electrical connection points 103 on the wafer active surface 1001 with each other. lead out.

As shown in Figure 4b, a protective layer 107 is applied on the wafer active surface 1001 and the wafer conductive layer 130.

In one embodiment, the protective layer 107 is applied by lamination.

Optionally, before the step of applying the protective layer 107, physical and/or chemical treatment is performed on the active surface 1001 of the wafer and/or the side where the protective layer 107 is applied to the wafer 100, so that the gap between the protective layer 107 and the wafer 100 is are more closely integrated. The treatment method can optionally be plasma surface treatment to roughen the surface to increase the bonding area and/or chemical accelerating modifier treatment, introducing accelerating modification groups between the wafer 100 and the protective layer 107, for example, simultaneously with an affinity organic and surface modifiers with affinity for inorganic groups to increase the adhesion between organic/inorganic interface layers.

As shown in Figure 4c, a protective layer opening 109 is formed on the surface of the protective layer 107.

At least a portion of the protective layer opening 109 is positioned corresponding to the wafer conductive layer 130, and the wafer conductive layer 130 is exposed through the protective layer opening 109; the protective layer opening 109 has a protective layer opening lower surface 109a and a protective layer opening upper surface 109b.

In a preferred embodiment, the shape of the protective layer opening 109 is such that the area of the upper surface 109b of the protective layer opening is larger than the area of the lower surface 109a of the protective layer opening. At this time, the slope of the side wall 109c of the protective layer opening can facilitate the filling of the conductive material. Easy to carry out, the conductive material will be evenly and continuously formed on the side walls during the filling process.

Preferably, the contact area of a single contact area between the wafer conductive layer 130 and the electrical connection point 103 is smaller than the contact area of a single contact area between the wafer conductive layer 130 and the protective layer opening 109 .

When the type of wafer 100 is such that the area of the exposed electrical connection point 103 is small, forming a conductive layer on the active surface 1001 of the wafer, and then forming the protective layer opening 109 can effectively reduce the difficulty of forming the protective layer opening 109 and avoid the formation of the protective layer opening 109. The opening lower surface 109a is too small, making it difficult to form the protective layer opening 109.

The protective layer opening 109 is formed by laser patterning or photolithography patterning.

Alternatively, the protective layer opening 109 may not be formed temporarily, and the protective layer opening 109 may be formed on the protective layer after the process of peeling off the carrier board.

Optionally, the protective layer opening 109 is filled with a conductive medium, so that the protective layer opening 109 becomes a conductive filled through hole 124, at least a part of the conductive filled through hole 124 is connected to the wafer conductive layer 130, and the protective layer surrounds the conductive filled through hole 124. .

Figures 5a to 5c show yet another optional process step of applying a protective layer 107 on the active surface 1001 of the wafer.

As shown in Figure 5a, a wafer conductive trace (wafer trace) 106 is formed on the active surface 1001 of the wafer.

The wafer conductive traces 106 can be made of copper, gold, silver, tin, aluminum or other materials or combinations thereof, or other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electrodeless plating processes, or Other suitable metal deposition processes may be used.

The at least a portion of the wafer conductive traces 106 may interconnect and lead out a plurality of the electrical connection points 103 in at least a portion of the wafer.

The at least part of the wafer conductive traces 106 may also be derived from at least a part of the electrical connection points 103 separately. For the crystal grains formed thereby, please refer to the grain diagram B in FIG. 6c.

As shown in FIG. 5 b , wafer conductive studs 111 are formed on the pads or connection points of the wafer conductive traces 106 .

The shape of the conductive bumps 111 of the wafer can be round or other shapes such as ellipse, square, linear, etc. The conductive bumps 111 of the wafer can be one or more layers of copper, gold, silver, tin, aluminum and other materials or a combination thereof, or can also be other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electrodeless plating, etc. Electroplating process, or other suitable metal deposition process.

Alternatively, the conductive bumps 111 of the wafer can also be directly formed at the electrical connection points 103 on the active surface 1001 of the wafer to lead out the electrical connection points 103. For the crystal grains thus formed, please refer to the crystal grain diagram C in Figure 6c.

The wafer conductive traces 106 and/or the wafer conductive bumps 111 are referred to as the wafer conductive layer 130 .

As shown in Figure 5c, a protective layer 107 is applied on the wafer conductive layer 130.

The protective layer 107 is applied on the wafer conductive layer 130 to cover the wafer conductive layer 130 .

In some embodiments, the protective layer 107 is applied by lamination.

In some embodiments, the protective layer 107 is applied so that the protective layer 107 completely covers the wafer conductive layer 130. In this case, after the application process of the protective layer 107, the thickness of the protective layer 107 is thinned to expose the wafer. conductive layer 130 surface.

In other embodiments, the thickness of the protective layer 107 is applied just enough to expose the surface of the conductive layer 130 of the wafer.

Optionally, before the step of applying the protective layer 107, physical and/or chemical treatment is performed on the wafer active surface 1001 on which the wafer conductive layer 130 is formed and/or the side on which the protective layer 107 is applied to the wafer 100, so that the protective layer The bond between 107 and wafer 100 is tighter. The treatment method can optionally be plasma surface treatment to roughen the surface to increase the bonding area and/or chemical accelerating modifier treatment, introducing accelerating modification groups between the wafer 100 and the protective layer 107, for example, simultaneously with an affinity organic and surface modifiers with affinity for inorganic groups to increase the adhesion between organic/inorganic interface layers.

In step S102, during the process of applying the protective layer 107 on the active surface of the chip 1001, the protective layer 107 can protect the active surface of the die 1131 from penetration of the plastic sealing material during the molding process, thus protecting the active surface of the die 1131 from damage; at the same time, during the molding process, The molding pressure will not easily cause the position of the die 113 to move on the carrier board (or the first carrier board) 117; in addition, it can also reduce the alignment accuracy requirements for the subsequent panel-level conductive layer formation process.

The protective layer 107 is made of insulating material, optionally such as BCB benzocyclobutene, PI polyimide, PBO polybenzoxazole, polymer matrix dielectric film, organic polymer film, or others with similar insulation and structure. Materials with special characteristics are formed by lamination, coating, printing, etc.

Preferably, the Young's modulus of the protective layer 107 is in the range of 1000 to 20000 MPa, and more preferably, the Young's modulus of the protective layer 107 is in the range of 1000 to 10000 MPa; further preferably, the Young's modulus of the protective layer 107 is in the range of 1000 to 10000 MPa. The modulus is between 1000~7000, 4000~7000 or 4000~8000 MPa; in the best embodiment, the Young's modulus of the protective layer 107 is 5500 MPa.

Preferably, the thickness of the protective layer 107 is in the range of 15~50 μm; more preferably, the thickness of the protective layer is in the range of 20~50 μm; in a preferred embodiment, the thickness of the protective layer 107 is 35 μm. ; In another preferred embodiment, the thickness of the protective layer 107 is 45 μm; in yet another preferred embodiment, the thickness of the protective layer 107 is 50 μm.

When the Young's modulus value range of the protective layer 107 is 1000-20000 MPa, on the one hand, the protective layer 107 is soft and has good flexibility and elasticity; on the other hand, the protective layer can provide sufficient supporting force to protect the Layer 107 has sufficient support for the conductive layer formed on its surface. At the same time, when the thickness of the protective layer 107 is 15-50 μm, it is ensured that the protective layer 107 can provide sufficient buffering and support.

Especially in some types of wafers, thin dies need to be used for packaging, and the conductive layer needs to reach a certain thickness value to form a large electric flux. At this time, the thickness range of the protective layer 107 is selected to be 15~50 μm. The numerical range of the Young's modulus of the protective layer 107 is 1000-10000 MPa. The soft and flexible protective layer 107 can form a buffer layer between the die 113 and the conductive layer formed on the surface of the protective layer, so that during the use of the wafer, the conductive layer on the surface of the protective layer will not overly press the die. grain 113 to prevent the pressure of the thick conductive layer from breaking the grain 113. At the same time, the protective layer 107 has sufficient material strength, and the protective layer 107 can provide sufficient support for the thick conductive layer.

When the Young's modulus of the protective layer 107 is 1000-20000 MPa, especially when the Young's modulus of the protective layer 107 is 4000-8000 MPa, and the thickness of the protective layer 107 is 20~50 μm, due to the The material characteristics enable the protective layer 107 to effectively protect the grains against the ejector pressure of the grain transfer equipment during the subsequent grain transfer process.

The grain transfer process is a process of rearranging and bonding the cut and separated grains 113 to the carrier plate 117 (reconstruction process). The grain transfer process requires the use of a grain transfer equipment (bonder machine). The grain transfer equipment includes an ejector pin. Use an ejection pin to lift up the die 113 on the wafer 100 , and use a bonder head to pick up the lifted die 113 , transfer it, and bond it to the carrier board 117 .

During the process of the ejector pin pushing up the crystal grain 113, the crystal grain 113, especially the thin crystal grain 113, is brittle and easily broken by the lifting pressure of the ejector pin. The protective layer 107 with material characteristics can protect the brittle crystal grain 113 during this process. The integrity of the grain 113 can be maintained even under relatively large jacking pressure.

Preferably, the protective layer 107 is an organic/inorganic composite material layer including filler particles. Further, the filler particles are inorganic oxide particles; further, the filler particles are SiO2 particles; in one embodiment, the filler particles in the protective layer 107 are two or more different types of inorganic oxide particles, for example SiO2 mixed with TiO2 particles. Preferably, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO2 particles, such as SiO2 mixed TiO2 particles, are spherical or spherical-like. In a preferred embodiment, the filling amount of filler particles, such as inorganic oxide particles, such as SiO2 particles, such as SiO2 mixed TiO2 particles, in the protective layer 107 is more than 50%.

Organic materials have the advantage of being easy to operate and apply. The die 113 to be encapsulated is made of inorganic material such as silicon. When the protective layer 107 is made of organic materials alone, due to the difference between the material properties of the organic material and the material properties of the inorganic material , which will make the packaging process difficult and affect the packaging effect. Using organic/inorganic composite materials that add inorganic particles to organic materials will modify the material properties of organic materials, making the materials have the characteristics of both organic and inorganic materials.

Especially the coefficient of thermal expansion (CTE) of the material. The silicon material grain 113 has a low thermal expansion coefficient, usually about 3 ppm/K. The protective layer 107 is an organic/inorganic composite material layer including filler particles, which can make the protective layer 107 The thermal expansion coefficient is reduced, which reduces the difference in properties between the organic layer and the inorganic layer in the packaging structure.

In a preferred embodiment, when (T<Tg), the thermal expansion coefficient of the protective layer 107 ranges from 3 to 10 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 5 ppm/K; In a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 7 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 10 ppm/K.

In the subsequent molding process, the die 113 with the protective layer 107 will expand and contract accordingly during the heating and cooling process of the molding process. When the thermal expansion coefficient of the protective layer 107 is in the range of 3~10 ppm/K , the degree of expansion and contraction between the protective layer 107 and the die 113 remains relatively consistent. The connection interface between the protective layer 107 and the die 113 is not easy to generate interface stress, and is not easy to destroy the bond between the protective layer 107 and the die 113, so that after packaging The wafer structure is more stable.

The packaged wafer often needs to go through hot and cold cycles during use. The thermal expansion coefficient of the protective layer 107 ranges from 3 to 10 ppm/K and the die 113 has the same or similar thermal expansion coefficient. During the hot and cold cycle, the protection The layer 107 and the die 113 maintain a relatively consistent degree of expansion and contraction, which prevents interface fatigue from accumulating at the interface between the protective layer 107 and the die 113, making the packaged chip durable and extending the service life of the chip.

On the other hand, if the thermal expansion coefficient of the protective layer is too small, the composite material of the protective layer 107 needs to be filled with too many filler particles, which will further reduce the thermal expansion coefficient and increase the Young's modulus of the material, making the protective layer material The flexibility is reduced, the stiffness is too strong, and the buffering effect of the protective layer 107 is poor. It is optimal to limit the thermal expansion coefficient of the protective layer to 5-10 ppm/k.

When the step of forming the protective layer opening 109 by laser patterning is included, preferably, the diameter of the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO2 particles, is less than 3 μm, preferably in the protective layer 107 The filler particles, such as inorganic oxide particles, such as SiO2 particles, have a diameter between 1 and 2 μm.

Controlling the diameter of the filler particles to less than 3 μm is conducive to forming protective layer openings 109 with smoother sidewalls on the protective layer 107 during the laser patterning process, so that the material can be fully filled during the conductive material filling process and avoid having The large-sized concave and convex protective layer opening sidewall 109c cannot be filled with conductive material behind the sidewall blocked by the protrusions, which affects the conductive performance of the conductive filled through-hole 124.

At the same time, the filling size of 1~2 μm will expose the small particle size filler during the laser patterning process, causing the protective layer opening sidewall 109c to have a certain roughness. This sidewall with a certain roughness will interact with the conductive material. The contact area is larger and the contact is closer, forming a conductive filled through hole 124 with good conductivity.

The diameter size of the filler mentioned above is the average value of the particle diameter.

Optionally, the tensile strength of the protective layer 107 ranges from 20 to 50 MPa; in a preferred embodiment, the tensile strength of the protective layer 107 is 37 MPa.

Optionally, after applying the protective layer 107 on the active surface 1001 of the wafer, the backside 1002 of the wafer is ground to thin the wafer 100 to a required thickness.

Modern electronic devices are becoming smaller and lighter, and wafers have a tendency to become thinner. In this step, the wafer 100 sometimes needs to be thinned to a very thin thickness. However, the processing and transfer of the thin wafer 100 is difficult, and the grinding and thinning process requires It is difficult, and it is often difficult to thin the wafer 100 to an ideal thickness. When the surface of the wafer 100 has a protective layer 107, the protective layer 107 with material properties will support the wafer 100 and reduce the difficulty of processing, transferring and thinning the wafer 100.

Step S103: Cut the wafer 100 on which the protective layer 109 is applied to form die 113 having the protective layer 109.

As shown in FIG. 6 a , the wafer 100 with the protective layer 107 applied is cut along the dicing lane to obtain a plurality of crystal grains 113 with a protective layer formed thereon. The crystal grains 113 have a crystal grain active surface 1131 and a crystal grain backside 1132 .

As shown in FIG. 6 b , the wafer 100 with the wafer conductive layer 130 formed thereon and the protective layer 107 formed with the protective layer opening 109 is cut along the dicing lane to obtain a plurality of crystal grains 113 , and the crystal grains 113 have crystal grain active surfaces. 1131 and the back side of the die 1132.

Among them, die diagram A in FIG. 6b shows that the conductive traces 106 of the die interconnect and lead out multiple electrical connection points 103 on the active surface 1131 of the die.

Diagram B of the die in FIG. 6b shows that the conductive traces 106 of the die separately lead out the electrical connection points 103 on the active surface 1131 of the die.

As shown in Figure 6c, the wafer 100 with the wafer conductive layer 130 and the protective layer 107 applied is cut along the dicing lane to obtain a plurality of crystal grains 113. The crystal grains 113 have a crystal grain active surface 1131 and a crystal grain backside 1132. .

Among them, die diagram A in FIG. 6c shows that the conductive traces 106 of the die interconnect and lead out multiple electrical connection points 103 on the active surface 1131 of the die.

Diagram B of the die in FIG. 6c shows that the conductive traces 106 of the die separately lead out the electrical connection points 103 on the active surface 1131 of the die.

Schematic diagram C of the die in FIG. 6c shows that the conductive protrusions 111 of the wafer are directly formed at the electrical connection points 103 on the active surface 1001 of the wafer to lead out the electrical connection points 103.

Optionally, before the step of cutting the wafer 100 to separate the grains 113, it also includes performing plasma surface treatment on the side of the wafer 100 with the protective layer 107 to increase the surface roughness, so as to facilitate the subsequent process. The adhesion of the die 113 on the carrier 117 is increased, making it less likely for the die 113 to move under the molding pressure.

Due to the material properties of the protective layer, during the cutting process of the wafer 100, the separated grains 113 are free of burrs and chippings.

It can be understood that, if the process allows, and the wafer 100 can be cut into dies 113 to be packaged according to specific actual conditions, the wafer conductive layer 130 can be formed on the die active surface 1131 of each die 113. and/or protective layer 107. The wafer conductive layer 130 refers to the conductive layer formed before the die 113 cut into the wafer 100 is mounted on the carrier 117 .

Step S104: Provide a metal structure.

According to the embodiment shown in FIG. 7 , the metal structure is a metal frame 200 , and the metal frame 200 is composed of a metal unit array. The metal frame 200 can use an existing lead frame in the industry, or can be formed by etching or mechanical stamping one or more pieces of metal according to actual requirements. The metal being patterned can be a single metal, such as copper, or an alloy. The surface of the metal can be partially or completely coated with a second metal, such as nickel and/or gold, to protect the metal sheet from environmental corrosion, such as oxidation. In some embodiments, the thickness of the metal is no less than the thickness of die 113 . In other embodiments, the thickness of the metal may initially be smaller than the thickness of the die 113 , but after the die 113 is ground to reduce the thickness of the package die, the thicknesses of the metal and the die 113 will be substantially the same. The patterned metal can be rectangular, square or other shapes, as shown in Figure 7. The metal is patterned to include the same 4 metal units, and the outer outline of each metal unit is rectangular, as shown here. For example, the number of metal units is not limited to 4 and can be set according to actual needs. The shape of the metal unit can also be rectangular or other shapes. The blank area in the metal unit indicates that the metal has been completely etched away, and the remaining metal part includes metal features. , different metal characteristics can bring different performance improvements.

The lead frame will be embedded in the plastic encapsulation layer 123 described below; therefore, it is also called an embedded lead frame. Alternatively, the metal frame 200 may also include a molded interconnect substrate or other conductive substrate having the same or similar functions as the above-mentioned lead frame.

In Figure 7, the metal features include at least one connection pad 201. These connection pads 201 are arranged inside the outline edge of the metal frame 200. They can also be arranged in other positions according to actual needs. The connection pads 201 are connected by metal that has not been etched away. Rod 203 connects. The connection pads 201 are equivalent to the pins of the packaged die. According to the present disclosure, after the die 113 is packaged, the connection pads 201 are in an exposed state, and the packaged die 113 is welded to the circuit board through these connection pads 201 on to achieve connections with other circuit components. The connecting rods 203 are retained when the metal is patterned to ensure that the connecting pads 201 and other features formed during the patterning are connected to the outer contour of the metal frame 200, so that when the metal frame 200 is transferred, the patterning can be ensured on it. Features on will not drop. Optionally, you can first attach the metal sheet to a temporary support for engraving. After the engraving is completed, use the support to transfer the position of the metal frame. This method does not require engraving connecting lines/connecting rods.

As shown in FIG. 7 , each metal unit in the metal frame 200 includes a vacancy 202 . The vacancy 202 is shown as a blank area in the figure. The blank area is formed by completely etching part of the metal, and its area is larger than the die 113 The surface area is such that the die 113 and the metal frame 200 are not contacted when the die 113 and the metal frame 200 are pasted to the carrier 117 in subsequent steps. According to the example in the figure, each metal unit includes one vacancy 202. In other examples, one metal unit may also include two or more vacancies 202, and each vacancy 202 accommodates one or more dies 113. Adjacent metal frames 200 have a common outer contour edge. As shown in Figure 7, the metal frame 200 in the upper left corner and the metal frames 200 on its right and lower sides each have a common outer contour edge, so that all metal frames 200 connected to become one.

The metal frame 200 of the present disclosure as shown in Figure 7 is only exemplary. The area of a whole piece of metal can be the same as the surface area of the carrier plate 117, and the shape is also the same as the shape of the carrier plate 117, preferably rectangular or rectangular, but It can also be designed into other shapes according to actual needs. However, it was found during the experiment that when the area of the carrier plate 117 is relatively large, if the metal frame 200 is etched with the same size as the carrier plate 117, because the metal is relatively thin, when the area is relatively large, during the transfer process It will easily cause deformation and be difficult to operate. Therefore, preferably, two or more pieces of metal whose total area is the same as the surface area of the carrier plate 117 can be used to etch one or more metal frames 200 on each piece of metal. During the production process, each piece of metal after etching is sequentially They are arranged on the carrier plate 117 and have the same surface area as the carrier plate 117 when put together.

Step S105: Arrange the die 113 and the metal structure with the protective layer 107 on the carrier board 117.

Figures 8a to 9 show a preferred embodiment of disposing the metal frame 200 on the carrier plate 117 in step S105.

Since the metal material used in the metal frame 200 is relatively thin, especially when the area is relatively large, the surface is easily bent and deformed when being picked up and placed. Therefore, in order to make it more convenient to accurately stick the metal frame 200 to the carrier plate 117 while maintaining a flat surface. , the following methods can be used:

As shown in Figures 8a and 8b, a temporary support plate 300 is provided, an adhesive layer 301 is formed on its surface, and the patterned metal frame 200 is attached to the temporary support plate 300 by adhesion. Optional Alternatively, the temporary support plate 300 may not be used, but the thick adhesive layer 301 may be directly used as the temporary support plate 300 to transport the patterned metal frame 200 . Preferably, the shapes and sizes of the temporary support plate 300, the adhesive layer 301 and the carrier plate 117 are consistent. In addition, the two opposite surfaces of the connection pad 201 of the metal frame 200 that are in contact with and away from the adhesive layer 301 are respectively defined as the connection pad back 2012 and the connection pad front 2011.

Preferably, as shown in Fig. 8a, after the metal frame 200 is adhered to the temporary support plate 300, the connecting rods 203 are cut to separate the metal frame 200. Optionally, each connecting rod 203 connecting each metal unit is cut, so that each metal unit adhered to the temporary support plate 300 is separated from each other; it is also possible to cut the connecting rod 203 in a specific area, and the entire temporary The metal frame 200 on the support plate 300 is separated into two parts, four parts, six parts, or any other number of parts. Preferably, the cutting line SL is along the center line of the connecting rod 203. The advantage of this method is that during the packaging process, it is often necessary to undergo heating and cooling steps to separate the entire metal frame 200 into smaller units, or directly separate it into separate metal units, so that during the heating and cooling steps of the packaging In the structure, the smaller metal frames 200 or metal units expand and contract independently of each other. Due to the smaller area, the degree of expansion and contraction of each unit or unit is smaller, making the packaging process easier to control and operate.

Preferably, as shown in Figure 8b, after the metal frame 200 is adhered to the temporary support plate 300, the connecting rod 203 is separated and removed from the metal frame 200, thereby separating the metal units in the metal frame 200, as shown in Figure 8b The connection pads 201 are divided into independent parts. Since features on the metal frame can be independent of each other, board-level testing can be performed before cutting, which can significantly reduce testing costs and time.

As shown in FIG. 9 , a carrier board 117 is provided. The carrier board 117 has a carrier board front 1171 and a carrier board back 1172 . The shape of the carrier plate 117 is: circular, triangular, quadrilateral or any other shape. The size of the carrier plate 117 can be a small-sized wafer substrate, or it can be a rectangular carrier plate of various sizes, especially a large size. The material of the plate 117 can be metal, non-metal, plastic, resin, glass, stainless steel, etc. Preferably, the carrier plate 117 is a large-sized quadrilateral panel made of stainless steel.

The carrier board 117 has a carrier board front surface 1171 and a carrier board back surface 1172. The carrier board front surface 1171 is a plane.

The die 113 is adhered and fixed on the carrier board 117 using the adhesive layer 121 .

The adhesive layer 121 can be formed on the front side of the carrier 1171 by lamination, printing, spraying, coating, etc. In order to facilitate the separation of the carrier board 117 and the molded die 113 on the back in the subsequent process, the adhesive layer 121 is preferably made of an easily separable material, for example, a thermal separation material is used as the adhesive layer 121 .

The side of the temporary support plate 300 on which the metal frame 200 is attached faces the front 1171 of the carrier plate. The surface area of the temporary support plate 300 is the same as that of the carrier plate 117 and the shape is the same. By aligning and contacting the two, the metal frame 200 can be attached. After being installed on the adhesive layer 121, the temporary support plate 300 is peeled off, and the adhesive layer 301 on the metal frame 200 is removed, thereby completing the mounting of the metal frame 200.

In this step, preferably, the metal frame 200 is aligned to the carrier plate 117 by pre-formed alignment marks on the carrier plate 117 and the metal frame 200 (the marks are not shown in the figure). The adhesive layer 301 adheres the metal frame 200 to the carrier board 117 .

In addition, the metal foil or metal sheet can also be attached to the temporary support plate 300 through the adhesive layer 301 on the temporary support plate 300, and then the metal foil or metal sheet can be etched into a desired pattern to form a patterned metal frame. 200, and then transfer the metal frame 200 to the carrier plate 117.

The side of the metal frame 200 facing the carrier plate 117 is defined as the front side of the metal frame, and the side facing away from the carrier plate 117 is defined as the back side of the metal frame. The metal structure front side and the metal structure back side, the metal unit front side and the metal unit back side, the metal feature front side and the metal feature back side are also defined accordingly.

FIG. 10 shows an embodiment in which the die 113 is placed on the carrier 117 in step S105.

Since the metal frame 200 has been pasted on the adhesive layer 121 on the front side of the carrier board 1171, which is shown as the connection pad 201 in Figure 10, when continuing to adhere the die 113, it is necessary to ensure that the die 113 does not contact the metal frame 200. , in this disclosure, the die 113 is pasted in the vacancy 202 of the metal frame 200 , optionally one vacancy 202 corresponds to one die 113 or one vacancy 202 corresponds to multiple die 113 . Preferably, a position mark for the arrangement of the die 113 is provided on the carrier plate 117. The mark can be formed on the carrier plate 117 by means of laser, mechanical engraving, etc. At the same time, an alignment element mark is also provided on the die 113, so as to When pasting, it is aligned with the pasting position on the carrier board 117 . Figure 10 is only an example diagram. Figure 10 only shows that the die 113 adhered to the adhesive layer 121 of the carrier 117 is in the form of a die with a protective layer 107 and a protective layer opening 109 as shown in Figure 6a. The grain 113; the die adhered to the adhesive layer 121 of the carrier 117 can also be in the form of a die with a chip conductive layer 130, a protective layer 107 and a protective layer opening 109 as shown in Figure 6b, or can be in the form of Figure 6b The die form with wafer conductive layer 130 and protective layer 107 is shown in 6c. At the same time, the metal frame 200 adhered to the adhesive layer 121 can also be a metal frame 200 with only the connecting rod 203 cut but without removing the connecting rod 203 as shown in FIG. 8a , or it can also be a metal frame 200 with a complete connecting rod 203 .

As shown in Figure 10, one metal unit corresponds to one die 113. The number of die 113 on the carrier 117 is the same as the number of metal units on the carrier 117. The arrangement of the die 113 is the same as the arrangement of the metal units on the carrier 117. corresponding to the arrangement. The number and arrangement of metal units are not limited to the one shown in Figure 10, but can be customized according to actual needs.

In addition, one metal unit can correspond to multiple die 113, and the multiple die 113 are placed in predetermined vacancies 202. In particular, the multiple die are multiple die with different functions, and are arranged according to the needs of the actual product. In the metal unit on the carrier board 117, it is packaged. After the packaging is completed, it is cut into multiple packages; thus, one package includes multiple dies to form a multi-chip module (MCM). , and the positions of multiple grains can be freely set according to the needs of the actual product.

In the installation sequence shown in FIGS. 9 and 10 , the metal frame 200 is first installed on the carrier board 117 , and then the die 113 is installed on the carrier board 117 . However, this is only an example, and the die may also be installed first. The particles 113 are installed on the carrier plate 117, and then the metal frame 200 is installed on the carrier plate 117.

Step S106: Form the plastic sealing layer 123 on the carrier plate 117.

As shown in Figure 11, the plastic encapsulation layer 123 covers the entire carrier board 117 and is used to encapsulate all the dies 113 and the metal frame 200. In Figure 11, it is embodied as a connection pad 201 to reconstruct a flat plate structure so as to After the carrier board 117 is peeled off, the subsequent packaging steps can be continued on the restructured flat plate structure.

The side of the plastic sealing layer 123 that contacts the front surface 1171 of the carrier or the adhesive layer 121 is defined as the front surface 1231 of the plastic sealing layer. The side of the plastic layer 123 facing away from the front surface 1171 of the carrier or the adhesive layer 121 is defined as the back side 1232 of the plastic layer.

Preferably, the front surface 1231 of the plastic sealing layer and the back surface 1232 of the plastic sealing layer are substantially flat and parallel to the front surface 1171 of the carrier plate.

The plastic sealing layer 123 may adopt slurry printing, injection molding, hot pressing molding, compression molding, transfer molding, liquid sealant molding, vacuum lamination, or other suitable molding methods. The plastic sealing layer 123 can be made of organic composite materials, resin composite materials, polymer composite materials, polymer composite materials, such as epoxy resin with fillers, ABF (Ajinomoto buildup film) or other polymers with suitable fillers.

In one embodiment, the plastic sealing layer 123 is formed of an organic/inorganic composite material by compression molding.

Optionally, before forming the plastic sealing layer 123, some pre-processing steps may be performed, such as chemical cleaning and plasma cleaning, to remove impurities on the surface of the die 113 and the metal frame 200, so that the plastic sealing layer 123 is in contact with the die 113 and the metal frame. 200 and the carrier board 117 can be connected more closely without delamination or cracking.

Preferably, the thermal expansion coefficient of the plastic sealing layer 123 is 3~10 ppm/K; in one preferred embodiment, the thermal expansion coefficient of the plastic sealing layer 123 is 5 ppm/K; in another preferred embodiment, the thermal expansion coefficient of the plastic sealing layer 123 is 7. ppm/K; in another preferred embodiment, the thermal expansion coefficient of the plastic sealing layer 123 is 10 ppm/K.

Preferably, the plastic sealing layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients.

The thermal expansion coefficient of the plastic sealing layer 123 is selected to be 3~10 ppm/K and has the same or similar thermal expansion coefficient as the protective layer 107. During the heating and cooling process of the molding process, the expansion and contraction between the protective layer 107 and the plastic sealing layer 123 The degree remains consistent, and the two materials are not prone to interface stress. The low thermal expansion coefficient makes the thermal expansion coefficients of the plastic layer 123, the protective layer 107 and the die 113 close, making the interfaces of the plastic layer 123, the protective layer 107 and the die 113 tightly bonded. Avoid interface layer separation.

The packaged wafer often needs to go through hot and cold cycles during use. Since the thermal expansion coefficients of the protective layer 107, the plastic sealing layer 123 and the die 113 are similar, during the hot and cold cycle process, the protective layer 107, the plastic cover 123 and the die 113 have similar thermal expansion coefficients. 113 has less interface fatigue, and interface gaps are less likely to occur between the protective layer 107, the plastic sealing layer 123 and the die 113, which increases the service life of the chip and makes the chip applicable to a wide range of fields.

The difference in thermal expansion coefficient between the crystal grain 113 and the plastic sealing layer 123 will also cause warping of the panel assembly after molding. Due to the warping phenomenon, it is difficult to accurately position the crystal grain 113 in the panel assembly during the subsequent conductive layer formation process. The location has a great impact on the conductive layer formation process.

Especially in the large panel packaging process, due to the large size of the panel, even a slight panel warpage will cause the grains in the outer and surrounding parts of the panel away from the center to be larger than before molding. Therefore, in the large-size panel packaging process, solving the warpage problem has become one of the keys to the entire process. The warpage problem even limits the enlargement of panel size and becomes a technical barrier in large-size panel packaging.

Limiting the thermal expansion coefficients of the protective layer 107 and the plastic sealing layer 123 to the range of 3~10 ppm/K, and preferably the plastic sealing layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients, can effectively avoid the occurrence of panel component warping. Realize the packaging process using large panels.

At the same time, during the molding process, the molding pressure will produce pressure on the back of the die 113 toward the carrier 117. This pressure will easily press the die 113 into the adhesive layer 121, thereby causing the die 113 to form the plastic layer 123 during the process. is trapped in the adhesive layer 121. After the plastic layer 123 is formed, the die 113 and the front surface 1231 of the plastic layer are not in the same plane. The surface of the die 113 protrudes outside the front surface 1231 of the plastic layer, forming a step-like structure. In the subsequent formation process of the panel-level conductive layer, the panel-level conductive layer will also have a step-like structure, making the packaging structure unstable.

When the active surface of the crystal grain 1131 has a protective layer 107 with material characteristics, it can play a buffering role under the molding pressure, preventing the crystal grain 113 from sinking into the adhesive layer 121, thereby avoiding the generation of a step-like structure on the front side of the molding layer 1231.

In order to expose the metal frame 200, the plastic sealing layer 123 also needs to be thinned, which can be thinned by mechanical grinding or polishing the front side 1231 of the plastic sealing layer. The thickness of the plastic sealing layer 123 is reduced to the back side of the metal frame 200, thereby exposing the metal frame. 200 surface characteristics. As shown in FIG. 12 , when the thickness of the metal frame 200 is thicker than that of the die 113 , the plastic layer can be further thinned to the back side of the die 113 , then the metal frame 200 (shown as the connection pad of the connection pad 201 in the figure) The backside 2012) and the backside of die 113 are both exposed. For another example, if the die 113 is thicker than the metal frame 200 , the molding layer 123 is thinned until the back side of the connection pad 2012 is exposed from the molding layer 123 . During this process, the die 113 is further thinned to the same thickness as the connection pad 201 .

Therefore, it has a shorter conductive path and smaller resistance, which is suitable for power modules.

Step S107: Form the second conductive structure 140 on the back side of the die 1132 and the second dielectric layer 170.

The second conductive structure 140 may be formed by a panel-level method of patterning a conductive layer.

For example, the second conductive structure 140 may be formed by a photolithography process. Referring to FIG. 13 , a dry film 160 is formed to cover the back side of the die 1132 , the back side of the plastic layer 1232 and the back side of the connection pad 2012 . The dry film 160 is a photosensitive film that can be used as a plating mold. The dry film 160 may be adhered by a rolling process in which a heated roller applies controlled pressure to heat the dry film 160 while pressing the dry film 160 onto the die backside 1132 , the molding layer backside 1232 and the connection pad backside 2012 . Alternatively, the dry film 160 can be adhered by a vacuum process. When the air near the dry film 160 is sucked to form a vacuum, the elastic device presses the dry film 160 to the back side of the die 1132, the back side of the plastic layer 1232 and the back side of the connection pad. above 2012.

Referring to FIG. 14 , a photolithography process is performed on the dry film 160 to form a patterned dry film 162 . In photolithography, a mask (not shown) is positioned over dry film 160 to cover selected portions of dry film 160 , and unselected portions of dry film 160 are exposed to a light source through the mask to form patterned dry film 162 Multiple dry film openings 163. Accordingly, at least a portion of the die backside 1132 (all or part thereof) and the connection pad backside 2012 are exposed through the dry film openings 163 of the patterned dry film 162 .

Referring to Figure 15, the second panel level conductive trace (panel level trace) 142 is made by filling the dry film opening 163 of the patterned dry film 162 with materials such as copper, gold, silver, tin, aluminum or their combination materials. Other suitable conductive materials may also be formed by utilizing PVD, CVD, sputtering, electrolytic plating, electrodeless plating processes, or other suitable metal deposition processes.

Referring to FIG. 16 , another dry film 164 is formed to cover the patterned dry film 162 and the second panel-level conductive traces 142 . Similar to the dry film 160, the dry film 164 is a photosensitive film, which can be formed by a rolling process or a vacuum process as described above.

Referring to FIG. 17 , the dry film 164 may also undergo a photolithography process to form a patterned dry film 166 . Patterned dry film 166 has a plurality of dry film openings 167 from which at least a portion of second panel-level conductive traces 142 are exposed. Patterned dry film 162 may be fully or partially covered by patterned dry film 166 .

Referring to FIG. 18 , the second panel-level conductive pillar 144 is formed by filling the dry film opening 167 with a conductive material such as copper, gold, silver, tin and aluminum or a combination thereof, or by PVD, CVD, sputtering, electrolysis Electroplating, electroless plating or other suitable metal deposition processes from other suitable conductive materials. In this way, the second panel-level conductive pillar 144 is electrically connected to the second panel-level conductive trace 142 and further to the connection pad 201 of the metal frame 200 .

As shown in FIG. 19 , the patterned dry film 162 and the patterned dry film 166 are removed; at the same time, the second panel-level conductive traces 142 and the second panel-level conductive pillars 144 remain on the die backside 1132 and the connection pad backside 2012 . The second panel-level conductive traces 142 and the second panel-level conductive pillars 144 are collectively defined as the second conductive structure 140 . In particular, the second conductive structure 140 is manufactured at the panel level, thereby increasing throughput and reducing manufacturing costs.

The pattern of the second conductive structure 140 in FIG. 19 is only exemplary, and it may have various patterns according to the specific circuit design.

Referring to FIG. 20 , a second dielectric layer 170 is formed to completely encapsulate the second conductive structure 140 (including the second panel-level conductive trace 142 and the second panel-level conductive pillar 144 ). In addition, the second dielectric layer 170 may also cover the portions of the back side of the molding layer 1232 and the back side of the connection pad 2012 that are not covered by the second panel-level conductive traces 142 . The second dielectric layer 170 may include epoxy molding compound in the form of a film, particles, or liquid. As mentioned above, the second dielectric layer 170 may have similar compositions and characteristics as the molding layer 123 . For example, the second dielectric layer 170 has the same or similar coefficient of thermal expansion (CTE) as the plastic layer 123 , so that interface stress is less likely to occur between the second dielectric layer 170 and the plastic layer 123 .

In order to expose the second panel-level conductive pillars 144, the second dielectric layer 170 also needs to be thinned. Referring to FIG. 21 , the second dielectric layer 170 is thinned by mechanically grinding or polishing the back surface 1702 of the second dielectric layer, thereby exposing the second panel-level conductive pillar 144 from the second dielectric layer 170 .

Step S108: Peel off the carrier board (or first carrier board) 117 to form the panel assembly 150 having the second conductive structure 140.

Please refer to Figure 22. After peeling off the carrier board 117, the protective layer 107 on the die active surface 1131, the lower surface of the metal frame 200 (represented by the connection pad front 2011 of the connection pad 201 in the figure) and the plastic sealing layer front 1231 be exposed. The arrows in Figure 22 illustrate the separation of carrier plate 117 from panel assembly 150.

After the carrier board 117 is separated, the structure of the plastic encapsulation layer 123 covering the die 113 and the metal frame 200 is defined as a panel assembly 150, which has a second conductive structure 140.

13 to 22 show that the second panel-level conductive traces 142 and the second panel-level conductive pillars 144 each have a conductive layer. However, it is understood that before the first carrier board 117 is separated from the panel assembly 150, the second panel-level conductive traces 142 and the second panel-level conductive pillars 144 may also have multiple configurations by repeating FIGS. 13 to 20 . a conductive layer.

Step S109: As shown in FIG. 23a, the panel assembly 150 with the second conductive structure 140 is inverted onto another carrier board (also referred to as the second carrier board) 118.

In some embodiments, the adhesive layer 122 can be formed between the second carrier 118 and the back side of the second dielectric layer 1702 by lamination, printing, spraying, coating, etc. In order to facilitate the separation of the carrier board 118 and the back side of the second dielectric layer 1702 in the subsequent process, the adhesive layer 122 is preferably made of an easily separable material, for example, a thermal separation material is used as the adhesive layer 122 .

Step S110: Form the first conductive mechanism 129 on the die active surface 1131 through a panel-level process.

Referring to FIG. 23b , the protective layer opening 109 is filled to form a conductive filled via 124 . A panel-level conductive layer is formed on the surface of the protective layer 107. The panel-level conductive layer is connected to the electrical connection point 103 on the die active surface 1131 through the chip conductive layer 130 and/or the conductive filled through hole 124, and is connected to the metal frame 200 (in The connection is shown as connection pad 201). The panel-level conductive layer can be one layer or multiple layers.

As shown in Figure 23b, the panel-level conductive layer is embodied as a panel-level conductive trace 125 (or a first panel-level conductive trace). Optionally, conductive filled vias 124 and panel-level conductive traces 125 are performed in the same panel-level conductive layer formation step. Similar to the second panel-level conductive traces 142 , the conductive filled vias 124 and the panel-level conductive traces 125 may be formed using a patterned conductive layer formation method, such as a photolithography process. The conductive filled through holes 124 and the panel conductive traces 125 can be made of copper, gold, silver, tin, aluminum or other materials or combinations thereof, or other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, Electroless plating process, or other suitable metal deposition process.

At least a portion of the panel-level conductive traces 125 are connected to the electrical connection points 103 on the die active surface 1131 and connected to the connection pads 201 through the conductive filled vias 124. Electrical connection points 103 on the active side of the die lead to connection pads 201 . At the same time, the panel-level conductive traces 125 are also electrically connected to the second conductive structure 140 through the connection pads 201 . Therefore, die 113 can be electrically back-grounded via conductive filled vias 124 , panel-level conductive traces 125 , and connection pads 201 to the second conductive structure 140 (ie, the ground of die 113 is located at the backside 1132 of the die). Since the second conductive structure 140 can provide a large ground contact area for the electrically back-grounded die 113, the die 113 has superior electrical performance when used in a power module.

The pattern traces of the panel-level conductive traces 125 in Figure 23b are merely exemplary and may have a variety of pattern traces depending on the specific circuit design.

Optionally, the conductive filled vias 124 and the panel-level conductive traces 125 can also be formed in steps. The conductive filled vias 124 are formed first and then the panel-level conductive traces 125 are formed.

When the conductive filled through holes 124 have been formed in the previous step of applying the protective layer, the step of forming the panel-level conductive layer can be directly performed.

When the protective layer opening 109 has not been formed in the previous step of applying the protective layer, a step of forming the protective layer opening 109 needs to be included.

In some embodiments, the first panel-level conductive pillars 127 are formed on the first panel-level conductive traces 125 through a panel-level method of forming a patterned conductive layer.

For example, the first panel-level conductive pillars 127 can be formed by a photolithography process, similar to the second panel-level conductive pillars 144 . The first panel-level conductive pillar 127 can be made of copper, gold, silver, tin, aluminum or other materials or a combination thereof, or can be other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, and electrodeless plating processes. , or other suitable metal deposition processes. The panel-level conductive traces 125 and the first panel-level conductive pillars 127 are collectively defined as a first conductive structure 129 . Accordingly, die 113 may be electrically connected to an external component (eg, a printed circuit board (PCB)) through filled vias 124 and first conductive structures 129 , including panel-level conductive traces 125 and first panel-level conductive pillars 127 .

The pattern of first panel-level conductive pillars 127 in Figure 23b is only exemplary and may have various patterns depending on the specific circuit design.

A first dielectric layer 146 is formed to encapsulate the first conductive structure 129 , and after a grinding process (eg, mechanical grinding or polishing), the first panel-level conductive pillars 127 are exposed from the first dielectric layer 146 . The first dielectric layer 146 may include epoxy molding compound in film, granular, or liquid form. In addition, the first dielectric layer 146 may have similar compositions and characteristics as the above-mentioned molding layer 123 . For example, the first dielectric layer 146 has the same or similar coefficient of thermal expansion (CTE) as the plastic layer 123 , so that interface stress is less likely to occur between the first dielectric layer 146 and the plastic layer 123 .

Figure 24 shows that the first panel-level conductive trace 125 and the first panel-level conductive pillar 127 each have one conductive layer. However, it should be understood that the first panel-level conductive traces 125 and the first panel-level conductive pillars 127 may have multiple conductive layers by repeating the above process before separating the second carrier board 118 from the panel assembly 150 .

Additionally, the second carrier 118 is peeled off to form the panel assembly 150 having the second conductive structure 140 encapsulated in the second dielectric layer 170 and the first conductive structure encapsulated in the first dielectric layer 146 129.

Referring to FIG. 24 , after the second carrier board 118 is peeled off, the second dielectric layer 170 and the second panel-level conductive pillars 144 of the second conductive structure 140 are exposed. The arrows in Figure 24 illustrate the separation of the second carrier plate 118 from the panel assembly 150. Accordingly, die 113 may be electrically and thermally connected to external components via first conductive structure 129 of die active side 1131 and second conductive structure 140 of die backside 1132 .

Step S111: Cutting to form multiple package wafers 400.

Referring to FIG. 25 , the package monomer is separated by cutting the panel assembly 150 to form a plurality of package chips 400 . Cutting can be performed by machinery or laser, for example. The two-point chain line in Figure 25 shows the cutting line SL (also called the saw line) along which separation is performed.

When the plastic-sealed metal frame 200 is the metal frame 200 including the connecting rod 203 as shown in Figure 8a, when cutting and separating, it is necessary to cut around the connecting rod 203 to remove the connecting rod 203, so that the package can be completed. No connecting rods are included in the wafer 500 so that each metal feature in the metal unit of the metal frame 200 is independent.

Preferably, before or after the cutting separation step, a surface treatment layer 131 is formed on the first conductive structure 129 and/or the second conductive structure 140 exposed from the package wafer 400 . Optionally, the surface treatment layer 131 is formed using electroplating, electroless plating or other suitable methods. For example, the surface treatment layer 131 may be electroless nickel immersion gold (ENIG), electroless nickel electroless palladium immersion gold (ENEPIG), tin (Tin), or nickel gold (ENEPIG). NiAu plating) or their combination.

Optionally, the surface treatment layer 131 can also be configured to enable electrical back-grounding of the die 113 in the package chip 400 , that is, the surface treatment layer 131 connects the backside of the die 1132 to a specific connection according to the specific design of the circuit. The back-ground connection pads 201 are electrically connected together (specifically connecting the back-ground connection pads is: the connection pads are connected through the conductive structure and the back-ground electrical connection point on the active surface of the die).

Figure 26 is an exemplary schematic diagram of package wafer 400 separated from panel assembly 150 and in use. In use, the package chip 400 is connected to a printed circuit board (PCB) or substrate 410 via at least one metal feature, shown as a connection pad 201 . In addition, the passive component 420 can also be mounted on the second conductive structure 140 and electrically connected to the die 113 in the package chip 400 . Passive component 420 may be a resistor 740, a capacitor 742, an inductor 744, or a combination thereof.

In addition to dissipating heat to the printed circuit board (PCB) or substrate 410 through the first conductive structure 129 , the heat sink 430 may also be mounted on the second conductive structure 140 to conductively fill the via 124 , the first The conductive structure 129 , the connection pad 201 of the metal frame 200 and the second conductive structure 140 dissipate the heat generated by the die 113 . In particular, the connection pads 201 are exposed from the side surface of the package wafer 400 . Therefore, the package chip 400 has a three-side heat dissipation design, thereby having an efficient cooling function, that is, the first side dissipates heat from the active surface 1131 of the die through the first conductive structure 129; the second side dissipates heat from the second conductive structure on the back side of the die 1132 140 to dissipate heat; and a third side to dissipate heat from the side via the connection pad 201 .

In addition, ground label 440 shows that the package die 400 is electrically grounded from the backside 1132 of the die through the second conductive structure 140 . Compared with traditional grounding, the electrical back grounding of the second conductive structure 140 can provide a larger contact area, making the package chip 400 more stable and safer to electrically ground, especially for devices with large electric flux. Power module.

Instead of the passive component 420 and/or the heat sink 430 , another package die 400 may also be mounted on the second conductive structure 140 of the package die 400 to form a package-on-package (POP) configuration.

27 illustrates a flowchart of another wafer packaging method 20 according to an exemplary embodiment of the present disclosure. Compared with the wafer packaging method 10 , the wafer packaging method 20 includes all steps from S201 to S211 and an additional step AS between S206 and S207 , that is, forming and filling a plurality of voids 502 in the molding layer 123 .

28-30 illustrate additional schematic diagrams of panel assembly 152 fabricated using wafer packaging method 20. The wafer packaging method 20 has the same steps S201 to S211 and additional steps AS as the wafer packaging method 10 . Therefore, the second chip packaging method 20 will not repeat the same steps S201 to S211, and the same diagrammatic symbols in FIGS. 2 to 25 are also used here to illustrate the same or similar features. Additional steps AS are described below.

As shown in FIG. 28 , the height of the connection pad 201 is greater than the thickness of the die 113 ; causing the plastic layer 123 to become thinner until the backside 2012 of the connection pad is exposed from the plastic layer 123 , while the die 113 is still completely encapsulated in the plastic layer 123 . Then, a plurality of gaps 502 are formed through the plastic layer 123 until the backside 1132 of the die 113 . Therefore, a portion of the die backside 1132 is exposed from the molding layer 123 through the gap 502 . Void 502 may be formed by any suitable process, such as a laser patterning process, a mechanical patterning process, laser drilling, or a combination thereof.

Similar to conductively filled vias 124, voids 502 are also filled with conductive dielectric. The conductive medium can be gold, silver, copper, tin, aluminum and other materials or combinations thereof, or other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electrodeless plating processes, or other suitable A metal deposition process is used to fill the gap 502 with a conductive medium to form a conductive filled gap 504 .

Referring to FIG. 30 , a second panel-level conductive trace 142 is formed on and connected to the conductive fill void 504 . Therefore, the die 113 can still be electrically back-grounded from the backside 1132 of the die through the second panel-level conductive traces 142 and the second panel conductive pillars 144 of the second conductive structure 140 .

Similarly, the second dielectric layer 170 is formed to encapsulate the second conductive structure 140 , wherein the second conductive structure 140 is exposed from the second dielectric layer 170 after a grinding process (eg, mechanical grinding or polishing). Additionally, the second dielectric layer 170 may have similar compositions and characteristics as the molding layer 132 as described above.

Referring to FIG. 30 , the package monomer is separated by cutting the panel assembly 152 to form a plurality of package chips 500 . Cutting can be performed mechanically or laser-based, for example. The two-point chain line in Figure 30 shows the cutting line SL (also called the saw line) along which separation is performed.

FIG. 31 is a schematic diagram of the package wafer 500 formed after cutting the panel assembly 152 manufactured according to FIGS. 28 to 30 . The same drawing numbers as in FIG. 26 are also used herein to describe the same or similar features in FIG. 30 . Similar to the package wafer 400 , the connection pads 201 are also exposed on the side surfaces of the package wafer 500 . Therefore, the package chip 500 also has a three-sided heat dissipation design, which is conducive to efficient cooling function.

Compared to the package die 400 , when the void 502 is filled with the encapsulation layer 123 , the second panel-level conductive trace 142 has a larger contact area, so the second conductive structure 140 of the package die 500 moves from the die backside 1132 toward the die. 113 exerts less stress. In addition, the larger contact area will also more firmly connect the second panel-level conductive trace 142 and the molding layer 123, which allows the second panel-level conductive trace 142 to have a thinner thickness; and the second panel-level conductive trace 142 Wire 142 accordingly has a smaller weight, which further reduces the stress exerted on die 113 from die backside 1132 .

Instead of passive components 420 and/or heat sink 430, another package die 500 may be mounted on the second conductive structure 140 of the package die 500 to form a package-on-package (POP) configuration. Alternatively, a package wafer 400 may be mounted on the second conductive structure 140 of the package wafer 500 to form a package-on-package (POP) configuration. Alternatively, the package die 500 may be mounted on the second conductive structure 140 of one package die 400 to form a stacked package configuration.

32-34 are flow diagrams of another variation of the panel assembly 154 of FIGS. 28-30. Similarly, steps S101 to S111 of the chip packaging method 10 will not be described again; therefore, the same reference numerals are used here to describe the same or similar features in FIGS. 2 to 25 and 28 to 30 . Furthermore, compared with the panel assembly 152 shown in FIGS. 28 to 30 , the additional steps AS of the wafer packaging method 20 are changed to manufacture the panel assembly 154 . Accordingly, variations of additional steps AS for manufacturing panel assembly 154 are described below.

Referring to FIG. 32 , the panel assembly 154 has a similar structure to the panel assembly 152 in FIG. 28 , except that a molding layer 610 is formed on the die backside 1132 of the die 113 and is exposed from the molding layer 123 . The plastic sealing layer 610 can be formed by paste printing, injection molding, hot press molding, compression molding, transfer molding, liquid sealant molding, vacuum lamination, or other suitable molding methods. For example, the plastic encapsulation layer 610 is formed on the backside 1132 of the die by a film molding process.

The plastic sealing layer 610 can be made of the same material as the plastic sealing layer 123, such as organic composite materials, resin composite materials, polymer composite materials, polymer composite materials, such as epoxy resin with fillers, ABF (Ajinomoto build-up film) or other polymers with suitable fillers. Alternatively, the plastic layer 610 may be made of a different material than the plastic layer 123 . Compared with the molding layer 123 , different materials may have better compatibility with the second panel-level conductive traces 142 to more stably fix the second conductive structure 140 and the molding layer 123 .

Referring to FIG. 33 , the gap 502 is formed in the molding layer 610 by any suitable process, such as a laser patterning process, a mechanical patterning process, a laser drilling process or a combination thereof; therefore, the back side of the die 113 A portion of 1132 is exposed from the molding layer 610 through the gap 502 . Then the gap 502 is filled with a conductive medium. The conductive medium can be gold, silver, copper, tin, aluminum or other materials or a combination thereof. It can also be other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, Electroless plating process, or other suitable metal deposition process, and the conductive medium is filled in the gap 502 to form the conductive filled gap 504.

Referring to FIG. 34 , the package monomer is separated by cutting the panel assembly 154 to form a plurality of package chips 550 . Cutting can be performed by machinery or laser, for example. The two-point chain line in Figure 34 shows the cutting line SL (also called the saw line) along which separation is performed.

35 is a schematic diagram of a package wafer formed after cutting according to a variation of the panel assembly 154 manufactured in FIGS. 32 to 34 . Package wafer 550 has the same structure as package wafer 500 , except that voids 510 are formed in the molding layer 610 on the back side of the die 1132 as described above. Additionally, passive components 420 and/or heat sink 430 may be mounted on second conductive structure 140 of package wafer 550 .

Alternatively, another package die 550 may be mounted on the second conductive structure 140 of the package die 550 to form a package-on-package (POP) configuration. Alternatively, one package die 400, 500 may be mounted on the second conductive structure 140 of the package die 550 to form a stacked package configuration. Alternatively, the package wafer 550 may be mounted on the second conductive structure 140 of one of the package wafers 400, 500 to form a stacked package configuration.

In the case where the first conductive structure 129 and the second conductive structure 140 are made of metal or metallic materials (eg, copper), they are connected with the die 113 , the metal frame 200 (herein represented as connection pads 201 ), the molding layer 123 and Compared with the other components mentioned above (such as the protective layer 107 ), it has a relatively heavy weight. Preferably, the first conductive structure 129 and the second conductive structure 140 have substantially the same weight to balance the package wafers 400, 500, 550 as a whole. In other words, if both the first conductive structure 129 and the second conductive structure 140 are made of the same metal or metallic material (eg, copper), they are of substantially equal quality.

Figure 36a illustrates a schematic diagram of a packaged wafer 600 having a first die 602 and a second die 604 using the wafer packaging method 10 of Figure 1 . Dies 602, 604 may be traditional silicon cores, silicon carbide (SiC) cores, gallium nitride (GaN) cores, or combinations thereof. Dies 602, 604 may be of any suitable design depending on the desired application. For example, dies 602, 604 may be a first field effect transistor (FET) and a second field effect transistor (FET) placed side by side.

Package wafer 600 has a similar package structure as package wafer 400; therefore, the same drawing numerals are used herein to describe the same or similar features in FIG. 26 . The first conductive structure 129 and the second conductive structure 140 are formed on both sides of the first and second dies 602, 604. Therefore, the first conductive structure 129 is connected to the first die active surface 6021 of the first die 602 and the second die active surface 6041 of the second die 604; and the second conductive structure 140 is connected to the first die 602 The first die backside 6022 and the second die backside 6042 of the second die 604 .

Similarly, the first conductive structure 129 and the second conductive structure 140 are also connected through the connection pads 201 in the package chip 600 . Accordingly, the first and second die active surfaces 6021, 6041 are electrically connected to the second conductive structure 140 for achieving electrical back grounding of the first and second dies 602, 604 in the package wafer 600.

Similarly, the package chip 600 also has a three-side heat dissipation design, which is conducive to efficient cooling function, that is, the first side is from the active surfaces 6021 and 6041 of the die through the first conductive structure 129; the second side is from the backside 6022 and 6041 of the die. The back side of 6042 dissipates heat from the side via the second conductive structure 140; and the third side, via the connection pad 201. In addition, the heat sink 430 may be installed on the second conductive structure 140 to accelerate the dissipation of heat from the package wafer 600 .

Optionally, the package die 600 may include a large-sized heat spreader 430 (referred to as a large heat spreader), which may further enhance heat dissipation of the first and second dies 602, 604. For example, if first die 602 occupies more space than second die 604 , a large heat sink 430 may be mounted over first die 602 . In this case, the heat generated by the second die 604 can still be dissipated to the large heat sink 430 through the first conductive structure 129 , the connection pad 201 and the second conductive structure 140 .

Alternatively, a large-sized passive component 420 may be mounted on the second conductive structure 140 and the first die 602; and a small-sized heat sink 430 (referred to as a small heat sink) may be mounted on the second conductive structure 140 and on the second die 604. In this case, the heat generated by the first die 602 can still be dissipated to the small heat sink 430 through the first conductive structure 129 , the connection pad 201 and the second conductive structure 140 .

In particular, both the first die 602 and the second die 604 have a face-down configuration and are connected to external components (such as printed circuit boards) through a direct flip-chip process. circuit board (PCB) or substrate) without the use of solder bumps or solder balls. For example, the first die active surface 6021 and the second die active surface 6041 are directly connected to external components (such as a printed circuit board or a substrate) through the conductive filled vias 124 and the first conductive structure 129 . In other words, the packaged chip 600 using the direct flip-chip process no longer requires the bumping and reflowing process using solder bumps or solder balls in the traditional flip-chip process. Considering that the solder bumps or solder balls have low electrical and thermal conductivity, the direct flip-chip process of the present application enables the package chip 600 to have better electrical and thermal properties, which is useful for having larger electrical flux during operation. And the power module that comes with the heat is very important. Figure 36a shows that the package die 600 can be directly connected to a printed circuit board (PCB) or substrate 410 through the first panel-level conductive pillars 127 of the first conductive structure 129.

Alternatively, if desired, a conventional flip-chip process may be applied to the package wafer 600 . 36b shows solder bumps or balls 412 formed below the first panel-level conductive pillars 127 of the first conductive structure 129 for connecting the package die 600 to a printed circuit board (PCB) or substrate 410.

The face-down configuration of the first and second dies 602, 604 will make the panel level packaging approach easier and more efficient. For example, in step S105 (called a die transfer process (reconstruction process) of panel-level packaging), the first and second dies 602, 604 (die 113 in FIG. 10) may be accurately arranged and adhered to the carrier 117 because features on the active surfaces 6021, 6041 of the dies (e.g., alignment alignment marks (not shown)).

Instead of the passive component 420 and/or the heat sink 430 , another package die 600 may be mounted on the second conductive structure 140 of the package die 600 to form a package-on-package (POP) configuration. Alternatively, one or more package wafers 400, 500, 550 may be mounted on the second conductive structure 140 of the package wafer 600 to form a stacked package configuration.

Similarly, in the case where the first conductive structure 129 and the second conductive structure 140 are made of metal or metallic materials (such as copper), with the die 113 , the connection pads 201 , the molding layer 123 and the above-mentioned other components (such as the protective layer 107), it has a relatively heavy weight. Preferably, the first conductive structure 129 and the second conductive structure 140 have substantially the same weight to balance the package wafer 600 as a whole. In other words, if the first conductive structure 129 and the second conductive structure 140 are made of the same metal or metallic material (eg, copper), they have substantially equal qualities.

37a, 37b, and 37c are schematic diagrams of a chip package 700 for a power module proposed according to an exemplary embodiment of the present disclosure. The chip package 700 is manufactured by the chip package method 10 in FIG. 1 . Therefore, features that are identical or similar to those in FIGS. 2 to 25 are labeled with the same schematic symbols.

Figure 37a shows a top view of a panel assembly 710 including a plurality of wafer packages 700 (eg, the four wafer packages 700 shown in Figure 37a) prior to segmentation. A plurality of chip packages 700 are arranged in a matrix configuration. The chip package 700 includes a first die 602 and a second die 604 of a metal oxide semiconductor field effect transistor (MOSFET), and a drive circuit (also referred to as a drive circuit) for controlling the first die 602 and the second die 604 drive element) 720. Therefore, the chip package 700 can be used as a DrMOS power module. For example, the first die 602 is a low side MOSFET optimized for ultra-fast switching, while the second die 604 is a high side MOSFET optimized for minimal conduction losses.

Therefore, the metal frame 200 includes a plurality of metal units (for example, four metal units as shown in Figure 37a). Each metal unit surrounds the first die 602, the second die 604 and the driving circuit 720 to form the chip package 700. In addition, the chip package 700 is manufactured by cutting the panel assembly 710 . Figure 37a shows the cutting line SL (also called the saw line) along which the separation takes place.

Figure 37b shows a cross-sectional view of the chip package 700 along the dashed line L1 in Figure 37a. Chip package 700 has a similar structure to package die 600 , except that second die 604 is replaced by driver circuit 720 . The driving circuit 720 has a thickness thinner than the first die 602 , and the driving backside 7042 of the driving circuit 720 does not directly contact the second conductive structure 140 . Therefore, a space 730 is formed between the driving backside 7022 and the second conductive structure 140 . Using the chip packaging method 10, the space 730 is filled with the plastic encapsulation layer 123 as shown in Figure 11. In this way, heat can still be dissipated from the driving backside 7202 to the second conductive structure 140 through the plastic encapsulation layer 123 .

Passive components 420 may be mounted over the second conductive structure 140, such as a resistor 740 and a capacitor 742 mounted over the first die 602 and the drive circuit 720, respectively, and between the resistor 740 and the drive circuit 720. Inductor 744. Therefore, the first die 602 and the driving circuit 720 are electrically connected to the passive component 420 by filling the conductive via 124, the first conductive structure 129, the connection pad 201 and the second conductive structure 140 for transmitting electrical signals;

Similarly, the chip package 700 can also achieve electrical back grounding through the second conductive structure 140 .

In particular, the chip package 700 retains a three-sided heat dissipation design along the dotted line L1 in Figure 37a, thereby having an efficient cooling function, that is, the first side, from the first die active surface 6021 and the driving active surface 7201 of the driving circuit 720 Via the first conductive structure 129; the second side, from the second die active surface 6022 and the driving backside 7202 of the driving circuit 720 via the second conductive structure 140; and the third side, from the side heat dissipation by the connection pad 201.

Figure 37c shows a cross-sectional view of the chip package 700 along the dashed line L2 in Figure 37a. Chip package 700 has a similar structure to package die 600 such that first die 602 and second die 604 are in direct contact with second conductive structure 140 at first die backside 6022 and second die backside 6042, respectively. Inductor 744 is also mounted on second conductive structure 140 exposed from molding layer 123 .

Similarly, the chip package 700 still retains the three-sided heat dissipation design along the dotted line L2 in Figure 37a, thereby having an efficient cooling function, that is, the first side, from the first and second die active surfaces 6021, 6041 via the first conductive structure 129; a second side, from the first and second die backsides 6022, 6042 via the second conductive structure 140; and a third side, from the side via the exposed connection pads 201 of the molding layer 123 for heat dissipation.

Instead of passive components 420 (eg, resistors 740, capacitors 742, and inductors 744) and/or heat sink 430, another chip package 700 may be mounted on the second conductive structure 140 of the chip package 700 to form a stack of power modules. Package-on-package (POP) configuration.

38a and 38b are schematic diagrams of another chip package 800 for a power module proposed according to an exemplary embodiment of the present disclosure. The chip package 800 is manufactured by the chip package method 20 in FIG. 2 . Therefore, features that are the same as or similar to those in Figures 2 to 25 and Figures 28 to 30 are designated by the same figure numerals.

Similar to the chip package 700, the display chip package 800 is also manufactured by separating the panel assembly 710 as shown in the top view of FIG. 37a.

Figure 38a shows a cross-sectional view of the chip package 800 along the dashed line L1 in Figure 37a. The chip package 800 has a similar structure to the chip package 700 shown in FIG. 37b , that is, the space 730 formed between the driving backside 7022 and the second conductive structure 140 is filled with a plastic encapsulation layer 123 so that heat can still escape from the driver through the plastic encapsulation layer 123 The backside 7202 emanates to the second conductive structure 140 .

However, the plurality of voids 502 as shown in FIG. 28 may be formed in the molding layer 123 and extend to the first crystal through any suitable process, such as a laser patterning process, a mechanical patterning process, a drilling process or a combination thereof. The back of the grain is 6022. The void 502 is then filled with a conductive medium or other suitable conductive material such as gold, silver, copper, tin, aluminum, etc., or combinations thereof, as shown in FIG. 29 .

Figure 38b shows a cross-sectional view of the chip package 800 along the dashed line L2 in Figure 37a. Compared with the chip package 700 shown in FIG. 37c , the penetration molding layer 123 to the second die can be formed by any suitable process, such as a laser patterning process, a mechanical patterning process, a drilling process or a combination thereof. The backside 6042 has a plurality of voids 502 as described in Figure 28. Then, as shown in FIG. 29 , the void 502 is filled with a conductive medium or other suitable conductive material such as gold, silver, copper, tin, aluminum, etc. or a combination thereof, thereby forming a conductive filled void 504 .

Instead of passive components 420 (eg, resistors 740, capacitors 742, and inductors 744) and/or heat sink 430, another chip package 800 may be mounted on the second conductive structure 140 of the chip package 800 to form a stacked package (package- on-package, POP) configuration. Alternatively, a chip package 700 may be mounted on the second conductive structure 140 of the chip package 800 to form a package-on-package (POP) configuration. Alternatively, the chip package 800 may be mounted on the second conductive structure 140 of one chip package 700 to form a package-on-package (POP) configuration.

39a and 39b are schematic diagrams of another chip package 850 for a power module proposed according to an exemplary embodiment of the present disclosure. The chip package 850 is manufactured using the chip package method 20 in FIG. 27 . Therefore, the same or similar features are represented by the same diagrammatic symbols in FIGS. 2 to 25 and 32 to 34 .

Similar to the chip package 700, the display chip package 850 is also manufactured by separating the panel assembly 710 as shown in the top view of FIG. 37a.

Figure 39a shows a cross-sectional view of the chip package 850 along the dashed line L1 in Figure 37a. Chip package 850 has a similar structure to chip package 800 shown in Figure 38a. However, the space 730 in the chip package 800 is filled with the molding layer 123; the void 502 is formed in the molding layer 123 and then filled with a conductive medium to form the conductive filled void 504.

In contrast, as shown in FIG. 32 , the void 502 in the chip package 850 is formed in the molding layer 610 . The plastic sealing layer 610 can be formed by paste printing, injection molding, hot press molding, compression molding, transfer molding, liquid sealant molding, vacuum lamination, or other suitable molding methods. For example, the molding layer 610 is formed on the die backsides 6022 and 6042 of the first and second dies 602 and 604 by a film molding process.

Instead of passive components 420 (eg, resistors 740, capacitors 742, and inductors 744) and/or heat sink 430, another chip package 850 may be mounted on the second conductive structure 140 of the chip package 850 to form a stacked package (package- on-package, POP) configuration. Alternatively, one chip package 700, 800 may be mounted on the second conductive structure 140 of the chip package 850 to form a stacked package configuration. Alternatively, the chip package 850 may be mounted on the second conductive structure 140 of the chip packages 700, 800 to form a stacked package configuration.

In the case where the first conductive structure 129 and the second conductive structure 140 are made of metal or metallic materials (such as copper), compared with the die 113 , the connection pad 201 , the plastic encapsulation layer 123 and the above-mentioned other components (such as the protective layer 107 ) , which has a relatively heavy weight. Preferably, the first conductive structure 129 and the second conductive structure 140 have substantially the same weight to balance the chip package 700, 800, 850 as a whole. In other words, the first conductive structure 129 and the second conductive structure 140 are of substantially equal quality if they are made of the same metal or metallic material (eg, copper).

FIG. 40 is a schematic diagram of a conventional chip package 900 for a power module. The conventional chip package 900 has a first semiconductor die 902 in a face-down configuration, that is, the first die active surface 9021 of the first semiconductor die 902 faces the lead frame 912 and uses solder. Solder bumps or solder balls are connected to the lead frame 912 through a conventional flip-chip process; and a second semiconductor in a face-up configuration The die 904 , that is, the second die active surface 9041 of the second semiconductor die 904 faces away from the lead frame 912 and is connected to the lead frame 912 through wire bonding 910 . These two different configurations (i.e., the face-down configuration of the first semiconductor die 902 and the face-up configuration of the second semiconductor die 904) will make the manufacturing process of the conventional chip package 900 complex and costly, and the semiconductor In the die transfer process (reconstruction process) of transferring the die 902 and 904 to the carrier 117, the bonding accuracy of the first and second semiconductor die is low.

In contrast, the first and second dies 602, 604 in the chip packages 700, 800, 850 each have a face-down configuration, with direct contact without solder bumps or balls. A direct flip-chip process is connected to the first conductive structure 129 and further connected to a printed circuit board (PCB) or substrate 410; therefore, the chip packaging methods 10, 20 are used in manufacturing the chip packages 700, 800 , 850 is simpler, lower cost and more accurate, especially the die transfer process (reconstruction process) of the carrier board 117 to which the first and second die 602, 604 and the driving circuit 720 are bonded as shown in Figure 10 ) (die 113 represents the first and second die 602, 604 in Figure 10).

As shown in FIG. 40 , a copper clip (Cu clip) 906 is mounted on the first semiconductor die 902 and the second semiconductor die 904 . However, due to the large size of the copper clip 906, the conventional chip package 900 requires a thick profile. Therefore, the heavy weight of the copper clip 906 may cause the first and second semiconductor dies 902, 904 to break. Meanwhile, wires 910 are also commonly used in conventional chip packages 900 to connect the second semiconductor die 904 to the lead frame 912 . The leads 910 also require a larger space (both vertically and laterally), making the conventional chip package 900 thicker and larger.

In contrast, the present disclosure uses a direct flip-chip process without using solder bumps or balls to directly connect the first and second dies 602, 604 and the driver circuit 720 to the printed circuit board (PCB). ) or on the substrate 410. Therefore, the chip packages 700, 800, and 850 have a thinner and smaller appearance, and are more suitable for portable electronic devices that are increasingly popular today (such as mobile phones, touch pads, and notebook computers).

As shown in FIG. 40 , die attach material 916 is used to attach the first and second semiconductor dies 902 , 904 to the lead frame 912 . Die attach material 916 , although it may also be conductive (eg, conductive paste or solder), has a greater resistance than the conductive material used for first conductive structure 129 (eg, copper). Therefore, the conventional chip package 900 with the die attach material 916 is not suitable for power modules that require low resistance and high current. Alternatively, die attach material 916 may be made of non-conductive materials (such as adhesives or film adhesives), but these non-conductive materials cannot effectively dissipate heat. Therefore, the conventional chip package 900 with the non-conductive die attach material 916 is not suitable for power modules that generate a lot of heat due to large currents.

In contrast, in chip packages 700, 800, 850, the first and second dies 602, 604 and the driver circuit 720 are directly connected to the metal frame 200 (eg, leads) through the first and second conductive structures 129, 140. The connection pads 201 of the frame) do not require the die attach material 916 of the conventional chip package 900. The first and second conductive structures 129, 140 may be made of a conductive material with high conductivity, such as copper, which allows a large electrical flux to flow in the power module. At the same time, less heat will be generated due to the smaller resistance of the first and second conductive structures 129, 140.

In particular, in the conventional chip package 900, in order for current to flow vertically through the first and second semiconductor dies 902, 904, a die back metal layer must be added to the backsides of the first and second dies 9022, 9042 (die back metal layer) 908 (such as copper). For example, a die back metal layer 908 is applied to the first die backside 9022 for vertical conduction from the first die active surface 9021 to the first die backside 9022 . However, at the same time, the grinding process as shown in FIG. 12 cannot be used for the die back metal layer 908; therefore, the first and second semiconductor dies 902 and 904 cannot be thinned by the grinding process to reduce the resistance, which will reduce the use of traditional chip packaging. 900 power module performance.

In contrast, the chip packages 700, 800, 850 do not have the die back metal layer 908 because the vertical conduction is through the connection pads 201 of the metal frame 200 and the second conductive on the die backsides 6022, 6042 and the driving backside 7202 Structure 140 conductive. Therefore, the grinding process shown in FIG. 12 can be used to thin the first and second dies 602, 604 and the driving circuit 720 to enhance the electrical performance of the chip packages 700, 800, 850 when used as a power module.

Additionally, conventional chip packaging 900 uses discrete metal components (eg, copper clips 906 and leadframe 912) that are fabricated separately prior to packaging. Therefore, expensive metals such as silver or nickel-palladium gold (NiPdAu) are also required to connect any two discrete metal components during the packaging process. For example, a spot plating layer 918 is applied between the copper clip 906 and the lead frame 912 to mount the copper clip 906 over the lead frame 912 . For another example, a spot plating layer 918 (not shown) also needs to be applied between the copper clip 906 and the die back metal layer 908 so that the copper clip 906 is mounted on the first die backside 9022 of the first semiconductor die 902 .

In contrast, chip packages 700, 800, 850 do not use discrete metal components. In contrast, the metal components of chip packages 700, 800, 850 (eg, conductive filled vias 124, first and second conductive structures 129, 140) are formed during packaging by a suitable metal deposition process (eg, PVD, CVD, sputtering , electrolytic plating, electrodeless plating process) to form the ground. For example, the first panel-level conductive trace 125 is directly formed on the conductive filled via 124 and the connection pad front surface 2011; then, the first panel-level conductive pillar 127 is directly formed on the first panel-level conductive line 125. Therefore, all conductive components in the wafer packages 700, 800, 850 are directly connected, eliminating the need for a process of forming the spot plating 918 during packaging. Therefore, the above-mentioned direct connection in the chip package 700, 800, 850 improves the reliability and mechanical stability of the connection between the conductive parts, which further improves its performance in the moisture sensitivity level test (moisture senility level test).

Additionally, chip packages 700, 800, 850 do not require the solder bumps or balls 922 found in conventional chip packages 900 to connect to a printed circuit board (PCB) or substrate 410, passive components, or heat sinks. For example, the first and second dies 602, 604 and the driver circuit 720 are directly connected to the printed circuit board (PCB) or substrate 410 through the first conductive structure 129 without the use of solder bumps or balls. As another example, the first and second dies 602, 604 and the driving circuit 720 are directly connected to the passive component 420 (such as the resistor 740, the capacitor 742 and the inductor 744) or the heat sink 430 through the second conductive structure, nor the Use solder balls or solder balls. Direct connection has multiple benefits for chip packages 700, 800, 850 compared to traditional chip packages 900, especially when used as a power module.

Solder is soft in nature; therefore, the solder bumps or balls 922 are easily deformed when the components of the conventional chip package 900 (including the semiconductor die 902, 904, the copper clip 906, the lead frame 912, and the plastic encapsulation layer) are installed. In addition, the melting temperature of solder is low; when the conventional chip package (especially as a power module) generates a large amount of heat, the solder bumps or balls 922 may melt and move, which may affect or even destroy the electrical circuits in the conventional chip package 900 connection.

Solder also has high resistance and impedance to large electric flux currents, and electromigration may also occur when the electric flux of the power module is large. In comparison, the resistance and impedance of directly connected conductive materials (such as copper) in the chip packages 700, 800, 850 are much smaller and are not susceptible to electromigration, making them suitable for use as power modules.

In addition, the conventional chip package 900 has a long conductive path along the copper clip 906 and the wire bond 910, which may cause serious parasitic effects and conduction losses. In contrast, direct connections in chip packages 700, 800, 850 have shorter conductive paths through the first and second conductive structures 129, 140 and the connection pads 201 of the metal frame 200, thereby mitigating parasitics. effects and conduction losses.

Additionally, a seed layer (not shown) may be formed prior to forming the direct connection in the chip packages 700, 800, 850 to further enhance the direct connection. The seed layer can be formed by sputtering Ti/Cu, sputtering SUS/Cu/SUS, electroless copper plating, or a combination thereof.

Referring to FIG. 40 , the conventional chip package 900 mainly dissipates heat from the plastic packaging layer that completely encapsulates the first and second semiconductor dies 902 , 904 and the copper clip 906 . Therefore, heat generated by the first and second semiconductor dies 902, 904 and heat generated by the electrical flux flowing in the conventional chip package 900 may not be efficiently transferred to the surrounding environment. Therefore, the traditional chip package 900 is not suitable for power modules.

In contrast, the chip packages 700, 800, and 850 have the above-mentioned three-side heat dissipation design, which is conducive to efficient cooling function. That is, the first side is from the first and second die active surfaces 6021 and 6041 and the driving active surface 7201 of the driving circuit 720 through the first conductive structure 129; the second side is from the first and second die backsides 6022 and 6042 and the driving backside 7202 of the driving circuit 720, via the second conductive structure 140; and the third side, dissipating heat from the side surface via the connection pad 201. In addition, the heat sink 430 may be installed on the second conductive structure 140 to accelerate heat dissipation of the chip packages 700, 800, 850.

The purpose of the above-mentioned specific embodiments is to further describe the technical solutions and technical effects of the present disclosure in detail. However, those skilled in the art will understand that the above-mentioned specific embodiments are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the inventive idea of the present disclosure shall be included in the protection scope of the present disclosure.

10: Chip packaging method 100:wafer 1001:wafer active surface 1002:wafer backside 103: Electrical connection point 105:Insulation layer 106: Wafer conductive traces 107:Protective layer 109: Protective layer opening 109a: Lower surface of protective layer opening 109b: Upper surface of protective layer opening 109c: Protective layer opening side wall 111: Chip conductive bumps 113:Grain 1131: Active surface of grain 1132:Backside of grain 117: (first) carrier board 1171: Front of carrier board 1172: Back of carrier board 118: (Second) Carrier board 121: Adhesive layer 122: Adhesive layer 123:Plastic sealing layer 1231: Front of plastic sealing layer 1232: Back side of plastic sealing layer 124:Conductively filled vias 125: First panel level conductive trace 127: First panel level conductive pillar 129: First conductive structure 130:wafer conductive layer 131: Surface treatment layer 140: Second conductive structure 142: Second panel level conductive traces 144: Second panel level conductive pillar 146: First dielectric layer 150:Panel components 152:Panel components 154:Panel components 160:dry film 162:Patterned dry film 163: Dry film opening 164:Dry film 166:Patterned dry film 167: Dry film opening 170: Second dielectric layer 1702:Backside of the second dielectric layer 20: Chip packaging method 200:Metal frame 201:Connection pad 2011: Connection pad front 2012: Back of connection pad 202: Vacancy 203:Connecting rod 300: Temporary support plate 301: Adhesive layer 400: Packaged chip 410: Printed circuit board (PCB) or substrate 412: Solder bumps or balls 420: Passive components 430: Radiator 440: Ground tag 500: Packaged chip 502:gap 504: Conductive fill gap 550:Packaging wafer 600: Packaged chip 602:The first grain 6021: First grain active surface 6022:Backside of the first die 604: Second grain 6041:Second grain active surface 6042: Backside of the second die 610:Plastic sealing layer 700: Chip packaging 710:Panel components 720: Drive circuit 7201: Drive active surface 7202: Back of driver 730:Space 740:Resistor 742:Capacitor 744:Inductor 800: Chip packaging 850: Chip packaging 900: Traditional chip packaging 902:The first grain 9021: First grain active surface 9022:Backside of the first die 904:Second grain 9041: Second grain active surface 9042: Backside of the second die 906: Copper clip 908:Die back metal layer 910: Lead (bonding) 912:Lead frame 916:Die attachment materials 918:Point plating 922: Solder bumps or balls A: Schematic diagram of grains AS: additional steps B: Schematic diagram of grains C: Schematic diagram of grains L1: dashed line L2: dashed line S101~S111: steps S201~S211: steps SL: cutting line

[Fig. 1] is a flow chart of a chip packaging method proposed according to an exemplary embodiment of the present disclosure. [Fig. 2] to [Fig. 25] are flow diagrams of a panel assembly manufactured according to the chip packaging method in Fig. 1. [Fig. 26] is a schematic diagram of a package wafer formed after cutting the panel assembly manufactured according to Figs. 2 to 25. [Fig. [Fig. 27] is a flowchart of another chip packaging method proposed according to an exemplary embodiment of the present disclosure. [Fig. 28] to [Fig. 30] are additional flow diagrams of manufacturing another panel assembly (panel assembly) according to the chip packaging method in Fig. 27. [Fig. 31] is a schematic diagram of a package wafer formed after cutting the panel assembly manufactured according to Figs. 28 to 30. [Fig. [Fig. 32] to [Fig. 34] are flow diagrams of another modification of the panel assembly in Figs. 28 to 30. [Fig. 35] is a schematic diagram of a package wafer formed after cutting according to a modification of the panel assembly manufactured in Figs. 32 to 34. [Fig. [Fig. 36a, Fig. 36b] are schematic diagrams of a packaged wafer having two wafers manufactured according to the wafer packaging method in Fig. 1. [Fig. 37a, Fig. 37b, Fig. 37c] are schematic diagrams of a chip package for a power module proposed according to an exemplary embodiment of the present disclosure. [Fig. 38a, Fig. 38b] are schematic diagrams of another chip package for a power module proposed according to an exemplary embodiment of the present disclosure. [Fig. 39a, Fig. 39b] are schematic diagrams of another chip package for a power module proposed according to an exemplary embodiment of the present disclosure. [Figure 40] is a schematic diagram of a conventional chip package used for power modules.

200:Metal frame

201:Connection pad

202: Vacancy

602:The first grain

604: Second grain

710:Panel components

720: Drive circuit

L1: dashed line

L2: dashed line

SL: cutting line

Claims (20)

A chip package for a power module, including: at least one die having an opposite active surface of the die and a backside of the die, wherein the at least one die has a thinner thickness for reducing the The resistance of the power module; a drive circuit for controlling the at least one crystal grain, the drive circuit having an opposite driving active surface and a driving back side; a protective layer formed on the active surface of the crystal grain and the driving active surface on the surface, wherein the protective layer has a plurality of protective layer openings for exposing the die active surface and the driving active surface from the protective layer; a metal unit including at least one metal feature, wherein the at least one metal feature Having at least one connection pad, the at least one connection pad has an opposite connection pad front side and a connection pad back side; and a plastic encapsulation layer for encapsulating the at least one die, the driving circuit, the protective layer and the metal unit ; wherein the chip package is connected to an external circuit from the side of the die active surface through the at least one metal feature, and the at least one connection pad is exposed to the side of the chip package. The chip package of claim 1, wherein the at least one die includes a first die and a second die, and the first die and the second die respectively have a first die active surface and a second die. a second die active surface, wherein the first die, the second die and the drive circuit are surrounded by the metal unit, the first die active surface, the second die active surface and the drive active surface Virtually flush. The chip packaging as described in claim 1 also includes: A first conductive structure formed on the at least one metal feature, the protective layer and the plastic encapsulation layer of the metal unit, wherein the first conductive structure is connected to the die active surface and the driving active surface for connecting the At least one die and the driving circuit are connected to the metal unit. The chip package of claim 3, wherein the first conductive structure has a plurality of conductive filled vias connected to the die active surface and the driving active surface, and the at least one metal feature of the metal unit, the A panel-level conductive layer is formed on the protective layer and the plastic encapsulation layer, wherein the conductive filled vias are formed by filling the protective layer openings with a conductive material. The chip package of claim 3, further comprising: a second conductive structure formed on the at least one metal feature of the metal unit and the plastic encapsulation layer, the second conductive structure and the first conductive structure on the at least one An opposite side of a die, wherein the second conductive structure is connected to the first conductive structure through the at least one metal feature of the metal unit. The chip package of claim 5, wherein the first conductive structure and the second conductive structure have substantially the same weight for balancing the chip package from the die active surface and the die backside. The chip package of claim 5, wherein the second conductive structure is in direct contact with the backside of the at least one die for electrically grounding the chip package. The chip package of claim 5, further comprising: at least one gap formed in the molding layer for exposing the backside of the chip from the molding layer, wherein a conductive medium is filled in the at least one gap to At least one conductive filled void is formed for connection with the second conductive structure. The chip packaging as described in claim 5 also includes: An additional plastic encapsulation layer formed on the back side of the die of at least one die, the additional plastic encapsulation layer being encapsulated by the plastic encapsulation layer; and at least one gap in the additional plastic encapsulation layer for separating the back side of the die from the Exposed in the plastic sealing layer, a conductive medium is filled in the at least one gap to form at least one conductive filling gap for connecting with the second conductive structure. The chip package of claim 5, further comprising: a first dielectric layer for encapsulating the first conductive structure, wherein the first conductive structure is exposed from the first dielectric layer for communicating with the first dielectric layer. external circuit connection; and a second dielectric layer for encapsulating the second conductive structure, wherein the second conductive structure is exposed from the second dielectric layer for connection with an external component. A wafer structure, including: at least one crystal grain having an opposite active surface of the crystal grain and a back surface of the crystal grain; a protective layer formed on the active surface of the crystal grain and having a plurality of protective layer openings for connecting the crystal grain The active surface of the particle is exposed from the protective layer; a metal unit includes at least one metal feature, wherein the at least one metal feature has at least one connection pad, and the at least one connection pad has an opposite connection pad front side and a connection pad back side; a plastic sealing layer for encapsulating the die, the protective layer and the metal unit; a first conductive structure formed on the at least one metal feature of the metal unit, the protective layer and the plastic sealing layer, wherein the third A conductive structure is connected to the die active surface for connecting the at least one die to the metal unit; and a second conductive structure is formed on the at least one metal feature of the metal unit and the plastic layer, the The second conductive structure and the first conductive structure are on an opposite side of the at least one die, wherein The second conductive structure is connected to the at least one die through the first conductive structure and the at least one metal feature of the metal unit, and the second conductive structure covers the backside of the at least one die; The chip structure is connected to an external circuit from the side where the active surface of the chip is located through the at least one metal feature, and the at least one connection pad is exposed to the side of the chip structure. The chip structure of claim 11, wherein the external circuit includes a printed circuit board, and the first conductive structure is in direct contact with the printed circuit board for directly connecting the at least one die to the printed circuit board. The wafer structure of claim 12, wherein the second conductive structure is used to electrically back ground the wafer structure. The wafer structure of claim 13, wherein the second conductive structure is in direct contact with a die backside of the at least one die for conducting heat from the die backside out of the wafer structure. The chip structure of claim 14, wherein the first conductive structure and the second conductive structure have substantially the same weight for balancing the chip package from the die active surface and the die backside. A method of manufacturing a chip package for a power module, including: providing at least one die with an opposite die active surface and a die backside, wherein the die active surface of the at least one die and the die The thickness between the backsides of the dies is thin, used to reduce a resistance of the power module; a driving circuit for controlling the at least one die is provided, the driving circuit has an opposite driving active surface and a driving backside; A protective layer is formed on the active surface of the crystal grain and the active surface of the drive, and the protective layer has a plurality of protective layer openings for exposing the active surface of the crystal grain and the active surface of the drive from the protective layer; placing a metal The unit surrounds the at least one die and the driver circuit, wherein the metal unit has at least one metal feature, the at least one metal feature has at least one connection pad, and the at least one connection pad has an opposite connection pad front side and a connection pad The back side; forming a plastic encapsulation layer for encapsulating the at least one die, the driving circuit, the protective layer and the metal unit; and using the at least one metal feature of the metal unit to separate the active surface of the die from the The side of the chip package is connected to an external circuit, and the at least one connection pad is exposed to the side of the chip package. The manufacturing method of claim 16, further comprising: forming a first conductive structure so as to be connected with the front surface of the connection pad of the at least one connection pad, a second surface of the protective layer of the protective layer, and a plastic seal of the plastic seal layer. The front surfaces of the layers are in direct contact, wherein the front surface of the connection pad, the second surface of the protective layer and the front surface of the plastic sealing layer are substantially flush. The manufacturing method as claimed in claim 17, further comprising: forming a second conductive structure in direct contact with the back surface of the connection pad of the at least one connection pad and the back surface of the plastic sealing layer, wherein the back surface of the plastic sealing layer and the back surface of the plastic sealing layer The plastic layers face each other. The manufacturing method of claim 18, further comprising: forming at least one gap in the plastic layer for exposing the backside of the at least one die; and filling the at least one gap with a conductive medium. To form at least one conductive filled void connected to the second conductive structure. The manufacturing method of claim 16, further comprising: forming a first dielectric layer encapsulating the first conductive structure, wherein the first conductive structure is exposed from the first dielectric layer for communicating with the external The circuits are connected; and a second dielectric layer encapsulating the second conductive structure is formed, wherein the second conductive structure is exposed from the second dielectric layer for connecting to an external component.

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