TW202236562A - Chip packaging method and chip structure - Google Patents

Abstract

The present disclosure provides a chip package for power modules including at least one semiconductor die; a driver circuit for controlling the at least one semiconductor die; a protective layer formed on a die active surface of the at least one die and a driver active surface of the driver circuit; a metal unit having at least one metal feature; and a molding layer for encapsulating the at least one semiconductor die, the driver circuit, the protective layer and metal unit. The chip package is connected with an external circuit via the at least one metal feature. The present disclosure also provides a method of making the chip packages for power modules.

Description

Chip packaging method and chip structure

The present disclosure relates to the field of semiconductor technology, and in particular to a chip packaging method and a chip structure with an embedded lead frame.

Panel-level packaging (panel-level package) is to cut the wafer to separate many chips, arrange and paste the chips on the carrier board, and package many chips at the same time in the same process. As a rising technology in recent years, panel-level packaging has received widespread attention. Compared with traditional wafer-level packaging (wafer-level package), panel-level packaging has the advantages of high production efficiency, low production cost, and suitable for mass production.

At the same time, the demand for chip packaging in today's power modules has increased significantly. However, traditional chip packaging still uses copper clips (Cu clip) and wire bonding (wire bonding), so there are many disadvantages. For example, the bulky size of copper clips makes it difficult to thin conventional die packages. Also, in a conventional chip package, a copper clip positioned over a die may cause die cracking due to its weight. This disadvantage becomes more severe when power modules require thinner dies. Additionally, wire bonding can result in poorer electrical and thermal performance than conventional die packages.

Therefore, the present application discloses a corresponding chip structure and packaging chip to solve the defects of conventional chip packaging. Especially chip structures with embedded lead frames and packaged chips have better electrical and thermal performance for power modules.

The present disclosure aims to provide a chip package for a power module, including at least one die having opposite die active faces and die back faces, wherein the at least one die has a thinner thickness for reducing A resistance when used as a power module; a driving circuit for controlling the at least one crystal grain, which has an opposite driving active surface and a driving back surface; a protective layer formed on the crystal grain active surface and the driving active surface, It has a plurality of protective layer openings, which are used to expose the grain active surface and the driving active surface from the protective layer; a metal unit, the metal unit includes at least one metal feature, wherein the at least one metal feature has At least one connection pad, the at least one connection pad has a connection pad front and a connection pad back; and a plastic encapsulation layer for encapsulating the at least one crystal grain, the driving circuit, the protective layer and the metal unit. The chip package is connected with an external circuit through at least one metal feature.

In some embodiments, the at least one grain includes a first grain and a second grain, which respectively have a first grain active surface and a second grain active surface, wherein the first grain, the second The die and the driving circuit are surrounded by the metal unit, and the active face of the first die, the active face of the second die and the active face of the drive are substantially flush.

In some embodiments, the chip package further includes a first conductive structure formed on at least one metal feature of the metal unit, the protection layer and the plastic encapsulation layer, wherein the first conductive structure is connected to the die active and a driving active surface for connecting the at least one die and the driving circuit to the metal unit.

In some embodiments, the first conductive structure has a plurality of conductive filled vias connected to the active surface of the die and the active surface of the driver, and at least one metal feature, protection layer and plastic encapsulation layer of the metal unit A panel-level conductive layer is formed on it, wherein the conductive filled via hole is formed by filling the opening of the protection layer with a conductive material.

In some embodiments, the chip package further includes a second conductive structure formed on at least one metal feature of the metal unit and the plastic encapsulation layer, the second conductive structure and the first conductive structure are formed on the at least one die The opposite side of the particle, wherein the second conductive structure is connected to the first conductive structure by at least one metal feature of the metal unit.

In some embodiments, the first conductive structure and the second conductive structure have substantially the same weight for balancing the die package from the active side of the die and the back side of the die.

In some embodiments, the second conductive structure is in direct contact with a die backside of at least one die for electrically back-grounding the die package.

In some embodiments, the chip packaging further includes forming at least one void in the plastic encapsulation layer for exposing the backside of the die from the plastic encapsulation layer, wherein the at least one void is filled with a conductive medium to form The gap is filled with conduction, which is used for connecting with the second conduction structure.

In some embodiments, the chip package further includes an additional plastic encapsulation layer formed on the die backside of the at least one die and encapsulated by the plastic encapsulation layer; and at least one void in the additional plastic encapsulation layer, It is used for exposing the backside of the crystal grain from the plastic encapsulation layer, wherein the at least one void is filled with a conductive medium to form a conductive filled void for connecting with the second conductive structure.

In some embodiments, the chip package further includes a first dielectric layer for encapsulating the first conductive structure, wherein the first conductive structure is exposed from the first dielectric layer for use with the and a second dielectric layer for encapsulating the second conductive structure, wherein the second conductive structure is exposed from the second dielectric layer for connecting with an external component.

The present disclosure also aims to provide a wafer structure, including at least one crystal grain having an opposite crystal grain active surface and a crystal grain back surface; a protection layer formed on the crystal grain active surface has a plurality of protection layer openings for Exposing the grain active surface from the protective layer; a metal unit, the metal unit comprising at least one metal feature, wherein the at least one metal feature has at least one connection pad, and the at least one connection pad has an opposite The front side of the connection pad and the back side of the connection pad; a plastic encapsulation layer for encapsulating the crystal grain, the protective layer and the metal unit; and a first conductive structure formed on at least one metal feature of the metal unit, the protective layer and the plastic encapsulation layer , wherein the first conductive structure is connected to the active surface of the die for connecting the at least one die to the metal unit. The chip structure is connected to an external circuit through at least one metal feature.

In some embodiments, the external circuit includes a printed circuit board, and the first conductive structure is in direct contact with the printed circuit board for directly connecting the at least one die to the printed circuit board.

In some embodiments, the wafer structure further includes a second conductive structure formed on at least one metal feature of the metal unit and the plastic encapsulation layer, the second conductive structure and the first conductive structure are formed on the at least one crystal The opposite side of the die, wherein the second conductive structure is connected to the at least one die via the first conductive structure and at least one metal feature of the metal unit for electrically back-grounding the wafer structure.

In some embodiments, the second conductive structure is in direct contact with a die backside of at least one die for transferring heat from the die backside to out of the wafer structure.

In some embodiments, the first conductive structure and the second conductive structure have substantially the same weight for balancing the die package from the active side of the die and the back side of the die.

The present disclosure also aims to provide a method of manufacturing a chip package for a power module, comprising providing at least one die having opposite die active faces and die back faces, wherein the die active face of the at least one die The thickness between the crystal grain and the back surface is relatively thin, which is used to reduce the resistance of the power module; a driving circuit for controlling the at least one crystal grain is provided, which has an opposite driving active surface and a driving back surface; A protective layer is formed on the grain active surface and the driving active surface, which has a plurality of protective layer openings for exposing the grain active surface and the driving active surface from the protective layer; a metal unit is placed to surround the at least one A die and a driving circuit, wherein the metal unit has at least one metal feature, the at least one metal feature has at least one connection pad, and the at least one connection pad has an opposite connection pad front and connection pad back; forming a plastic encapsulation layer, for encapsulating the at least one die, driving circuit, protective layer and metal unit; and connecting the chip package to an external circuit through at least one metal feature of the metal unit.

In some embodiments, the manufacturing method further includes forming a first conductive structure so as to be in direct contact with the front surface of the connection pad of the at least one connection pad, the second surface of the protective layer of the protective layer, and the front surface of the plastic encapsulation layer, Wherein the front side of the connection pad, the second side of the protective layer and the front side of the plastic sealing layer are substantially flush.

In some embodiments, the manufacturing method further includes forming a second conductive structure, which is in direct contact with the back of the connection pad of the at least one connection pad and the back of the molding layer of the molding layer, wherein the back of the molding layer is opposite to the front of the molding layer .

In some embodiments, the manufacturing method further includes forming at least one void in the plastic encapsulant layer for exposing the backside of the at least one die therefrom; and filling the at least one void with conductive The medium is used to form a conductive filling void, and is connected to the second conductive structure.

In some embodiments, the manufacturing method further includes forming a first dielectric layer encapsulating the first conductive structure, wherein the first conductive structure is exposed from the first dielectric layer for communicating with the external and forming a second dielectric layer encapsulating the second conductive structure, wherein the second conductive structure is exposed from the second dielectric layer for connection to an external component.

In order to make the technical solutions of the present disclosure clearer and the technical effects more clear, the following descriptions and illustrations of the preferred embodiments of the present disclosure will be given in detail in conjunction with the drawings. It cannot be understood that the following descriptions are the only implementation forms of the present disclosure, or that they are the only implementation form of the present disclosure Public restrictions.

FIG. 1 is a flowchart of a chip packaging method 10 according to an embodiment of the disclosure. 2 to 25 are schematic flowcharts of a panel assembly manufactured according to the chip packaging method in FIG. 1 .

Please refer to FIG. 1, the chip packaging method 10 of the present disclosure includes the following steps:

Step S101: providing a wafer 100.

As shown in Figure 2, provide at least one wafer 100, this wafer 100 has wafer active surface 1001 and wafer back 1002, wafer 100 comprises a plurality of crystal grains 113, wherein the active surface of each crystal grain constitutes wafer active surface 1001, wafer The active surface of each crystal grain in 100 forms a series of active elements and passive elements through a series of processes such as doping, deposition, and etching. The active elements include diodes, triodes, etc., and the passive elements include voltage elements, Capacitors, resistors, inductors, etc., these active components and passive components are connected by connecting wires to form a functional circuit, thereby realizing various functions. The active surface 1001 of the wafer also includes an electrical connection point 103 for leading out a functional circuit and an insulating layer 105 for protecting the electrical connection point 103 .

Step S102: Apply a protective layer 107 on the active surface 1001 of the wafer.

Figures 3a and 3b show the process steps of optionally applying a protective layer 107 on the active surface 1001 of the wafer:

As shown in Figure 3a, a protective layer 107 is applied on the active side 1001 of the wafer.

Preferably, the protective layer 107 is applied to the active surface 1001 of the wafer by lamination.

Optionally, before the step of applying the protective layer 107 on the active surface 1001 of the wafer, the active surface 1001 of the wafer and/or the side on which the protective layer 107 is applied on the wafer 100 is subjected to physical and/or chemical treatment, so that the protective layer 107 and The bond between wafers 100 is tighter. The treatment method can optionally be plasma surface treatment to roughen the surface to increase the bonding area and/or chemically promote modifier treatment to introduce a promotional modification group between the wafer 100 and the protective layer 107, for example with an affinity organic Surface modifiers with affinity to inorganic groups to increase the adhesion between organic/inorganic interface layers.

As shown in FIG. 3 b , a protective layer opening 109 is formed on the surface of the protective layer 107 .

An opening 109 in the protective layer is formed at a position of the protective layer 107 corresponding to the electrical connection point 103 on the active surface 1001 of the wafer, exposing the electrical connection point 103 on the active surface 1001 of the wafer.

Preferably, there is a one-to-one correspondence between the openings 109 in the protective layer and the electrical connection points 103 on the active surface 1001 of the wafer.

Optionally, each protective layer opening 109 in at least a part of the protective layer openings 109 corresponds to a plurality of electrical connection points 103 .

Optionally, at least a part of the electrical connection points 103 corresponds to a plurality of protective layer openings 109 .

Optionally, at least a part of the protective layer openings 109 has no corresponding electrical connection points 103 , or at least a part of the electrical connection points 103 has no corresponding protective layer openings 109 .

The protective layer opening 109 is formed by laser patterning or photolithography patterning.

If the protective layer opening 109 is formed by laser patterning, preferably, before the protective layer 107 is applied on the active surface 1001 of the wafer, an electroless plating process step is performed on the active surface 1001 of the wafer to form a conductive covering on the electrical connection point 103. Floor. Optionally, the conductive covering layer is one or more layers of Cu, Ni, Pd, Au, Cr; preferably, the conductive protective layer is a Cu layer; the thickness of the conductive protective layer is preferably 2-3 μm. The conductive cover layer is not shown in the figure. The conductive covering layer can protect the electrical connection point 103 on the active surface 1001 of the wafer from laser damage in the subsequent step of forming the opening 109 of the protective layer.

Preferably, as shown in the partial enlarged view in FIG. 3 b , there is a gap between the lower surface 109 a of the protective layer opening and the insulating layer 105 , preferably, the lower surface 109 a of the protective layer opening is located near the center of the electrical connection point 103 .

In a preferred embodiment, the shape of the protective layer opening 109 is such that the area of the upper surface 109b of the protective layer opening is larger than the area of the lower surface 109a of the protective layer opening, and the area ratio of the lower surface 109a of the protective layer opening to the upper surface 109b of the protective layer opening is 60%~90%.

At this time, the slope of the sidewall 109c of the opening of the protective layer can facilitate the filling of the conductive material, and the conductive material will be uniformly and continuously formed on the sidewall during the filling process.

Optionally, the protective layer opening 109 may not be formed temporarily, and the protective layer opening 109 may be formed on the protective layer after the process of peeling off the carrier.

Optionally, a conductive medium is filled in the protective layer opening 109 , so that the protective layer opening 109 becomes a conductive filled via 124 . At least a portion of the conductive filled vias 124 are connected to the electrical connection points 103 on the active surface 1001 of the wafer. The conductive filled via hole 124 extends from the electrical connection point 103 on the active surface 1001 of the wafer to the surface of the protective layer, and the protective layer is formed around the conductive filled via hole 124 . The conductive medium can be materials such as gold, silver, copper, tin, aluminum or combinations thereof, and can also be other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable A metal deposition process forms a conductive filled via 124 in the passivation layer opening 109 .

Figures 4a to 4c show another optional process step for applying a protective layer 107 on the active surface 1001 of the wafer:

As shown in FIG. 4 a , a wafer conductive layer 130 is formed on the active surface 1001 of the wafer.

Wafer conductive layer 130 is wafer trace 106 . Chip conductive trace 106 can be copper, gold, silver, tin, aluminum and other materials or combinations thereof, and can also be other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or Other suitable metal deposition processes are formed.

At least some of the wafer conductive traces 106 are connected to at least some of the electrical connection points 103 on the active surface 1001 of the wafer.

Optionally, the conductive traces 106 of the wafer interconnect and lead out multiple electrical connection points 103 in at least a part of the active surface 1001 of the wafer. For the crystal grains formed by this, please refer to the grain diagram A in FIG. 6b.

The formation of the wafer conductive traces 106 can reduce the number of protective layer openings 109 formed in the subsequent process, and utilize the wafer conductive traces 106 to firstly interconnect a plurality of electrical connection points 103 with each other according to the circuit design, eliminating the need for an electrical connection at each electrical connection point. 103 to form protective layer openings 109 .

Optionally, the conductive traces 106 on the wafer independently lead out at least a part of the electrical connection points 103 on the active surface 1001 of the wafer. For the crystal grains thus formed, please refer to the grain diagram B in FIG. 6b.

The formation of the wafer conductive trace 106 helps to reduce the difficulty of forming the protective layer opening 109. Due to the existence of the wafer conductive trace 106, the lower surface 109a of the protective layer opening can have a larger area. Correspondingly, the lower surface 109a of the protective layer opening can be Making the protective layer opening 109 have a larger area, especially on the wafer 100 with smaller exposed electrical connection points 103 , makes the formation of the protective layer opening 109 possible.

Although not shown in the figure, it can be understood that the conductive traces 106 of the wafer independently lead out a part of the electrical connection points 103 on the active surface 1001 of the wafer and interconnect the other part of the electrical connection points 103 on the active surface 1001 of the wafer with each other. lead out.

As shown in FIG. 4 b , a protective layer 107 is applied on the active surface 1001 of the wafer and the conductive layer 130 of the wafer.

In one embodiment, the protective layer 107 is applied by lamination.

Optionally, before the step of applying the protective layer 107, the active surface 1001 of the wafer and/or the side on which the protective layer 107 is applied on the wafer 100 is subjected to physical and/or chemical treatment, so that the gap between the protective layer 107 and the wafer 100 more tightly combined. The treatment method can optionally be plasma surface treatment to roughen the surface to increase the bonding area and/or chemically promote modifier treatment to introduce a promotional modification group between the wafer 100 and the protective layer 107, for example with an affinity organic Surface modifiers with affinity to inorganic groups to increase the adhesion between organic/inorganic interface layers.

As shown in FIG. 4 c , a protective layer opening 109 is formed on the surface of the protective layer 107 .

At least a part of the protective layer opening 109 is located corresponding to the chip conductive layer 130, and the chip conductive layer 130 is exposed through the protective layer opening 109; the protective layer opening 109 has a protective layer opening lower surface 109a and a protective layer opening upper surface 109b.

In a preferred embodiment, the shape of the protective layer opening 109 is such that the area of the upper surface 109b of the protective layer opening is larger than the area of the lower surface 109a of the protective layer opening. It is easy to carry out, and the conductive material will be uniformly and continuously formed on the sidewall during the filling process.

Preferably, the contact area of a single contact area between the wafer conductive layer 130 and the electrical connection point 103 is smaller than the contact area of a single contact area between the wafer conductive layer 130 and the protective layer opening 109 .

When the type of the wafer 100 is that the area of the exposed electrical connection point 103 is small, a conductive layer is formed on the active surface 1001 of the wafer, and then the protective layer opening 109 is formed, which can effectively reduce the formation difficulty of the protective layer opening 109, and avoid the formation of the protective layer opening 109. The lower surface 109a of the opening is too small, making it difficult to form the protective layer opening 109 .

The protective layer opening 109 is formed by laser patterning or photolithography patterning.

Optionally, the protective layer opening 109 may not be formed temporarily, and the protective layer opening 109 may be formed on the protective layer after the process of peeling off the carrier.

Optionally, a conductive medium is filled in the protective layer opening 109, so that the protective layer opening 109 becomes a conductive filled via 124, at least a part of the conductive filled via 124 is connected to the wafer conductive layer 130, and the protective layer surrounds the conductive filled via 124 .

5a to 5c show yet another process step for optionally applying a protective layer 107 on the active surface 1001 of the wafer.

As shown in FIG. 5 a , wafer traces 106 are formed on the wafer active surface 1001 .

Chip conductive trace 106 can be copper, gold, silver, tin, aluminum and other materials or combinations thereof, and can also be other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or Other suitable metal deposition processes are formed.

The at least a part of the wafer conductive traces 106 may interconnect and lead out at least a part of the multiple electrical connection points 103 with each other.

The at least a part of the conductive traces 106 of the wafer can also lead out at least a part of the electrical connection points 103 separately. For the crystal grain formed by this, please refer to the schematic diagram B of the crystal grain in FIG. 6c.

As shown in FIG. 5 b , wafer studs 111 are formed on the pads or connection points of the wafer conductive traces 106 .

The shape of the chip conductive protrusion 111 may be round, or other shapes such as ellipse, square, line, etc. The conductive bump 111 of the chip can be one or more layers of copper, gold, silver, tin, aluminum and other materials or a combination thereof, and can also be other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electrodeless electroplating process, or other suitable metal deposition process.

Optionally, the conductive bumps 111 of the wafer can also be directly formed at the electrical connection point 103 on the active surface 1001 of the wafer to lead out the electrical connection point 103. For the crystal grain thus formed, please refer to the grain schematic diagram C in FIG. 6c.

The wafer conductive traces 106 and/or the wafer conductive bumps 111 are referred to as the wafer conductive layer 130 .

A protective layer 107 is applied over the wafer conductive layer 130 as shown in FIG. 5c.

The passivation layer 107 is applied on the wafer conductive layer 130 to cover the wafer conductive layer 130 .

In some embodiments, protective layer 107 is applied by lamination.

In some embodiments, the application of the protective layer 107 is such that the protective layer 107 completely covers the conductive layer 130 of the wafer. In this case, after the application of the protective layer 107, there will be a thinning of the protective layer 107 to expose the wafer. the surface of the conductive layer 130 .

In some other embodiments, the thickness of the protection layer 107 is just enough to expose the surface of the wafer conductive layer 130 .

Optionally, before the step of applying the protective layer 107, the active surface 1001 of the wafer formed with the wafer conductive layer 130 and/or the side of the protective layer 107 applied to the wafer 100 are subjected to physical and/or chemical treatment, so that the protective layer The bond between 107 and wafer 100 is tighter. The treatment method can optionally be plasma surface treatment to roughen the surface to increase the bonding area and/or chemically promote modifier treatment to introduce a promotional modification group between the wafer 100 and the protective layer 107, for example with an affinity organic Surface modifiers with affinity to inorganic groups to increase the adhesion between organic/inorganic interface layers.

In step S102, during the process of applying the protective layer 107 on the active surface 1001 of the wafer, the protective layer 107 can protect the active surface 1131 of the crystal grain from infiltration of the molding material during the molding process so as to protect the active surface 1131 of the crystal grain from damage; meanwhile, during the molding process, The molding pressure is not easy to cause the die 113 to move on the carrier (or called the first carrier) 117; in addition, it can also reduce the alignment accuracy requirement of the subsequent panel-level conductive layer formation process.

The protective layer 107 adopts an insulating material, optionally such as BCB benzocyclobutene, PI polyimide, PBO polybenzoxazole, a polymer matrix dielectric film, an organic polymer film, or other materials with similar insulation and structure The characteristic material is formed by lamination, coating, printing and other methods.

Preferably, the Young's modulus of the protective layer 107 is in the range of 1000~20000 MPa, more preferably the Young's modulus of the protective layer 107 is in the range of 1000~10000 MPa; further preferably the Young's modulus of the protective layer 107 The modulus is 1000~7000, 4000~7000 or 4000~8000 MPa; in the best embodiment, the Young's modulus of the protective layer 107 is 5500 MPa.

Preferably, the thickness of the protective layer 107 is in the range of 15-50 μm; more preferably the thickness of the protective layer is in the range of 20-50 μm; in a preferred embodiment, the thickness of the protective layer 107 is 35 μm ; In another preferred embodiment, the thickness of the protective layer 107 is 45 μm; In yet another preferred embodiment, the thickness of the protective layer 107 is 50 μm.

When the Young's modulus value range of the protective layer 107 is 1000-20000 MPa, on the one hand, the protective layer 107 is soft and has good flexibility and elasticity; on the other hand, the protective layer can provide enough supporting force to make the protection Layer 107 has sufficient support for the conductive layer formed on its surface. At the same time, when the thickness of the protective layer 107 is 15-50 μm, it is ensured that the protective layer 107 can provide sufficient cushioning and support.

Especially in some types of chips, it is necessary to use thin crystal grains for packaging, and the conductive layer needs to reach a certain thickness to form a large electric flux. At this time, the thickness range of the protective layer 107 is selected to be 15-50 μm. The value range of the Young's modulus of the protective layer 107 is 1000-10000 MPa. The protective layer 107 that is soft and flexible can form a buffer layer between the crystal grains 113 and the conductive layer formed on the surface of the protective layer, so that during the use of the wafer, the conductive layer on the surface of the protective layer will not excessively press the crystal. grains 113, to prevent the pressure of the thick conductive layer from breaking the grains 113. At the same time, the protective layer 107 has sufficient material strength, and the protective layer 107 can provide sufficient support for the thick conductive layer.

When the Young's modulus of the protective layer 107 is 1000-20000 MPa, especially when the Young's modulus of the protective layer 107 is 4000-8000 MPa, when the thickness of the protective layer 107 is 20-50 μm, due to the protective layer 107 The material properties enable the protective layer 107 to effectively protect the die against the ejector pin pressure of the die transfer device during the subsequent die transfer process.

The die transfer process is the process of rearranging and bonding the cut and separated die 113 on the carrier plate 117 (reconstruction process). The die transfer process requires the use of a die transfer device (bonder machine). The die transfer device includes thimbles, The die 113 on the wafer 100 is lifted up by a thimble, and the lifted die 113 is picked up by a bonder head, transferred and bonded to the carrier 117 .

During the process of lifting the crystal grain 113 by the thimble, the crystal grain 113, especially the thin grain 113, is brittle and is easily broken by the pressure of the ejector pin. The protective layer 107 with material properties can protect the brittle crystal grain 113 in this process. The grain 113 can maintain the integrity of the crystal grain 113 even under a relatively large jacking pressure.

Preferably, the protective layer 107 is an organic/inorganic composite material layer including filler particles. Further, the filler particles are inorganic oxide particles; further, the filler particles are SiO2 particles; in one embodiment, the filler particles in the protective layer 107 are two or more different types of inorganic oxide particles, for example SiO2 mixed with TiO2 particles. Preferably, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO2 particles, such as SiO2 mixed with TiO2 particles, are spherical or quasi-spherical. In a preferred embodiment, the filling amount of the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO2 particles, such as SiO2 mixed with TiO2 particles, is more than 50%.

Organic materials have the advantages of easy operation and easy application. The crystal grain 113 to be encapsulated is made of inorganic materials such as silicon. When the protective layer 107 uses organic materials alone, due to the difference between the material properties of organic materials and inorganic materials , which will make the packaging process difficult and affect the packaging effect. The use of organic/inorganic composite materials in which inorganic particles are added to organic materials will modify the material properties of organic materials, making the materials have both the characteristics of organic materials and inorganic materials.

Especially the coefficient of thermal expansion (CTE) of the material, the silicon material grain 113 has a relatively low coefficient of thermal expansion, usually about 3 ppm/K, and the protective layer 107 is an organic/inorganic composite material layer including filler particles, which can make the protective layer 107 The coefficient of thermal expansion is reduced, so that the property difference between the organic layer and the inorganic layer in the encapsulation structure is reduced.

In a preferred embodiment, when (T<Tg), the thermal expansion coefficient of the protective layer 107 ranges from 3 to 10 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 5 ppm/K; In a preferred embodiment; the thermal expansion coefficient of the protective layer 107 is 7 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 10 ppm/K.

In the subsequent molding process, the crystal grains 113 with the protective layer 107 will expand and shrink accordingly during the heating and cooling process of the molding process, when the thermal expansion coefficient of the protective layer 107 is in the range of 3-10 ppm/K , the degree of expansion and contraction between the protective layer 107 and the crystal grain 113 remains relatively consistent, the connection interface between the protective layer 107 and the crystal grain 113 is not easy to generate interface stress, and is not easy to damage the combination between the protective layer 107 and the crystal grain 113, so that after packaging The chip structure is more stable.

The packaged chip often needs to go through hot and cold cycles during use. The thermal expansion coefficient of the protective layer 107 ranges from 3 to 10 ppm/K and the crystal grain 113 has the same or similar thermal expansion coefficient. During the hot and cold cycles, the protection The layer 107 and the die 113 maintain a relatively consistent expansion and contraction, avoiding the accumulation of interface fatigue at the interface between the protective layer 107 and the die 113 , making the packaged chip durable and prolonging the service life of the chip.

On the other hand, if the thermal expansion coefficient of the protective layer is too small, it is necessary to fill the composite material of the protective layer 107 with too many filler particles, which will increase the Young's modulus of the material while further reducing the thermal expansion coefficient, so that the protective layer material The flexibility is reduced, the rigidity is too strong, and the cushioning effect of the protective layer 107 is not good. It is optimal to limit the coefficient of thermal expansion of the protective layer to 5-10 ppm/k.

When the step of forming the protective layer opening 109 by means of laser patterning is included, preferably, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO2 particles, have a diameter of less than 3 μm, preferably in the protective layer 107 The filler particles, such as inorganic oxide particles, such as SiO2 particles, have a diameter between 1 and 2 μm.

Controlling the diameter of the filler particles to be less than 3 μm is conducive to the formation of protective layer openings 109 with smoother sidewalls on the protective layer 107 during the laser patterning process, so that the material can be fully filled in the conductive material filling process and avoid The sidewall 109 c of the protective layer opening with large concave-convex shape cannot be filled with conductive material behind the sidewall covered by the convexity, which affects the conductive performance of the conductively filled via hole 124 .

At the same time, the filling size of 1-2 μm will expose the filler with small particle size during the laser patterning process, so that the side wall 109c of the protective layer opening has a certain roughness, and the side wall with a certain roughness will be in contact with the conductive material. The contact surface is larger, the contact is closer, and the conductive filled through hole 124 with good electrical conductivity is formed.

The diameter size of the fillers mentioned above is the average value of particle diameter.

Optionally, the tensile strength of the protective layer 107 ranges from 20 to 50 MPa; in a preferred embodiment, the tensile strength of the protective layer 107 is 37 MPa.

Optionally, after the protective layer 107 is applied on the active surface 1001 of the wafer, the back surface 1002 of the wafer is ground to thin the wafer 100 to a required thickness.

Modern electronic equipment is small and lightweight, and the wafer has a thinning trend. In this step, the wafer 100 sometimes needs to be thinned to a very thin thickness. However, the processing and transfer of the thin wafer 100 is difficult, and the grinding and thinning process process Difficulty is great, and it is often difficult to thin the wafer 100 to a desired thickness. When the surface of the wafer 100 has a protective layer 107 , the protective layer 107 with material properties will support the wafer 100 , reducing the difficulty of processing, transferring and thinning the wafer 100 .

Step S103 : dicing the wafer 100 applied with the protection layer 109 to form crystal grains 113 with the protection layer 109 .

As shown in FIG. 6 a , the wafer 100 coated with the protective layer 107 is cut along the dicing line to obtain a plurality of crystal grains 113 formed with the protective layer. The crystal grains 113 have a crystal grain active surface 1131 and a crystal grain back surface 1132 .

As shown in Figure 6b, the wafer 100 formed with a wafer conductive layer 130, applied with a protective layer 107 and formed with a protective layer opening 109 is cut along the dicing line to obtain a plurality of crystal grains 113, and the crystal grains 113 have a crystal grain active surface. 1131 and die backside 1132 .

Wherein, the schematic diagram A of the grain in FIG. 6 b is that the conductive traces 106 of the wafer interconnect and lead out the plurality of electrical connection points 103 on the active surface 1131 of the grain.

The schematic diagram B of the grain in FIG. 6 b is that the conductive trace 106 of the wafer leads out the electrical connection point 103 on the active surface 1131 of the grain separately.

As shown in Figure 6c, the wafer 100 formed with the wafer conductive layer 130 and the applied protective layer 107 is cut along the dicing line to obtain a plurality of crystal grains 113, and the crystal grains 113 have a crystal grain active surface 1131 and a crystal grain back surface 1132 .

Wherein, the schematic diagram A of the crystal grain in FIG. 6c is that the conductive traces 106 of the wafer interconnect and lead out a plurality of electrical connection points 103 on the active surface 1131 of the crystal grain.

The schematic diagram B of the grain in FIG. 6c is that the conductive trace 106 of the wafer leads out the electrical connection point 103 on the active surface 1131 of the grain separately.

The crystal grain schematic diagram C in FIG. 6 c shows that the conductive protrusion 111 of the wafer is directly formed at the electrical connection point 103 on the active surface 1001 of the wafer, and leads out the electrical connection point 103 .

Optionally, before the step of cutting the wafer 100 to separate the crystal grains 113, it also includes performing plasma surface treatment on the side with the protective layer 107 of the wafer 100 applied with the protective layer 107 to increase the surface roughness, so that in the subsequent process The adhesiveness of the die 113 on the carrier 117 is increased, and it is difficult for the die 113 to move under the molding pressure.

Due to the material properties of the protective layer, during the dicing process of the wafer 100 , the separated crystal grains 113 are free from burrs and chippings.

It can be understood that, if the process permits, the wafer 100 can be optionally cut into dies 113 to be packaged according to specific actual conditions, and a wafer conductive layer 130 is formed on the die active surface 1131 of each die 113 and/or protective layer 107 . The wafer conductive layer 130 refers to the conductive layer formed before the die 113 cut from the wafer 100 is attached to the carrier 117 .

Step S104: providing a metal structure.

According to the embodiment shown in FIG. 7 , the metal structure is a metal frame 200 composed of a metal unit array. The metal frame 200 may use an existing lead frame in the industry, or may be formed by etching or mechanically stamping a piece or/one piece of metal according to actual needs. The metal to be patterned can be a single metal, such as copper, or an alloy. The surface of the metal can be partially or completely coated with a second metal, such as nickel and/or gold, to protect the metal sheet from environmental corrosion, such as oxidation. In some embodiments, the thickness of the metal is not less than the thickness of the grains 113 . In yet other embodiments, the thickness of the metal may initially be less than that of the die 113, but after the die 113 is ground to reduce the thickness of the package die, both the metal and the die 113 will be substantially the same thickness. The engraved metal can be rectangular, square or other shapes. As shown in FIG. Exemplarily, the number of metal units is not limited to 4, and can be set according to actual needs. The shape of the metal unit can also be a rectangle or other shapes. The blank area in the metal unit indicates that the metal is completely etched away, and the remaining metal part includes metal features. , different metal features can lead to different performance enhancements.

The lead frame will be embedded in the plastic encapsulation layer 123 described below; therefore, it is also called an embedded lead frame. Alternatively, the metal frame 200 may also include a molded interconnect substrate or other conductive substrates having the same or similar functions as the above-mentioned lead frame.

In FIG. 7, the metal feature includes at least one connection pad 201, and these connection pads 201 are arranged inside the contour edge of the metal frame 200, and can also be arranged at other positions according to actual needs. Rod 203 is connected. The connection pads 201 are equivalent to the pins of the packaged die. According to the present disclosure, after the die 113 is packaged, the connection pads 201 are in an exposed state, and the packaged die 113 is soldered to the circuit board through these connection pads 201 On, realize the connection with other circuit components. When the metal is engraved, the connecting rod 203 is reserved to ensure that the connection pads 201 and other features formed by the engraving are connected to the outer contour of the metal frame 200, so that when the metal frame 200 is transferred, the engraving can be guaranteed to be on the other side. The traits on will not drop. Optionally, the metal sheet can be first attached to a temporary support for engraving. After the engraving is completed, the position of the metal frame can be transferred by means of the support. This method does not require engraved connecting wires/connecting rods.

As shown in FIG. 7, each metal unit in the metal frame 200 includes a vacancy 202. The vacancy 202 is shown as a blank area in the figure. The blank area is formed by completely etching part of the metal, and its area is larger than the crystal grain 113. The surface area is so that the die 113 and the metal frame 200 will not touch the die 113 when sticking the die 113 and the metal frame 200 to the carrier 117 in the subsequent steps. According to the example in the figure, each metal unit includes one vacancy 202 , in another example, a metal unit may also include two or more vacancies 202 , and each vacancy 202 accommodates one or more crystal grains 113 . Adjacent metal frames 200 have a common outer contour edge, as shown in Figure 7, the metal frame 200 in the upper left corner, and the metal frame 200 on the right side and the lower side have a common outer contour edge, so that all metal frames 200 connected to become one.

The metal frame 200 of the present disclosure as shown in FIG. 7 is only exemplary, and the area of a whole piece of metal can be the same as the surface area of the carrier 117, and the shape is also the same as that of the carrier 117, preferably rectangular or rectangular, but It can also be designed into other shapes according to actual needs. However, it has been found in the course of the experiment that when the area of the carrier plate 117 is relatively large, if the same large metal as the carrier plate 117 is used to etch the metal frame 200, since the metal is relatively thin, when the area of the carrier plate 117 is relatively large, the transfer process It is easy to cause deformation and difficult to operate. Therefore, preferably, two or more pieces of metal whose total area is the same as the surface area of the carrier plate 117 can be used, and one or more metal frames 200 are etched on each piece of metal. During the manufacturing process, each piece of metal after etching is sequentially It is arranged on the carrier board 117, and the surface area of the carrier board 117 is the same when put together.

Step S105 : placing the crystal grain 113 with the protection layer 107 and the metal structure on the carrier 117 .

8a to 9 show a preferred embodiment of disposing the metal frame 200 on the carrier 117 in step S105.

Since the metal material used in the metal frame 200 is relatively thin, especially when the area is relatively large, the surface is easy to be bent and deformed when it is taken and placed. Therefore, in order to more conveniently attach the metal frame 200 to the carrier board 117 in a flat state. , which can be done in the following ways:

As shown in Figure 8a and Figure 8b, a temporary support plate 300 is provided, an adhesive layer 301 is formed on its surface, and the engraved metal frame 200 is attached to the temporary support plate 300 by pasting, optional Alternatively, instead of using the temporary support plate 300 , the thick adhesive layer 301 can be directly used as the temporary support plate 300 to transport the engraved metal frame 200 . Preferably, the shape and size of the temporary support plate 300 , the adhesive layer 301 and the carrier plate 117 are consistent. In addition, two opposite surfaces of the connection pad 201 of the metal frame 200 in contact with and away from the adhesive layer 301 are respectively defined as the connection pad back 2012 and the connection pad front 2011 .

Preferably, as shown in FIG. 8 a , after the metal frame 200 is pasted on the temporary support plate 300 , the connecting rod 203 is cut to separate the metal frame 200 . Optionally, each connecting rod 203 connecting each metal unit is cut, thereby, each metal unit pasted on the temporary support plate 300 is separated from each other; it is also possible to cut the connecting rod 203 of a specific area, and the entire temporary The metal frame 200 on the support plate 300 is split into two parts, four parts, six parts, or any other number of parts. Preferably, the cutting line SL is along the centerline of the connecting rod 203 . The advantage of this method is that in the packaging process, it is often necessary to undergo heating and cooling steps, and a whole metal frame 200 is separated into units with smaller areas, or directly separated into metal units separated from each other, so that in the heating and cooling steps of packaging Among them, the smaller metal frame 200 or metal units expand and contract independently of each other. Due to the smaller area, the degree of expansion and contraction of each unit or unit is smaller, making the packaging process easier to control and operate.

Preferably, as shown in Figure 8b, after the metal frame 200 is pasted on the temporary support plate 300, the connecting rod 203 is separated and removed from the metal frame 200, so that the metal units in the metal frame 200 are separated, as shown in Figure 8b In order to connect the pads 201 into separate parts. Since the features on the metal frame can be independent of each other, board-level testing can be performed before cutting, which can greatly reduce the cost and time of testing.

As shown in FIG. 9 , a carrier board 117 is provided, and the carrier board 117 has a carrier board front side 1171 and a carrier board back side 1172 . The shape of the carrier 117 is: circular, triangular, quadrilateral or any other shape. The size of the carrier 117 can be a small-sized wafer substrate, or a rectangular carrier of various sizes, especially a large size. The material of the plate 117 can be metal, non-metal, plastic, resin, glass, stainless steel and so on. Preferably, the carrier plate 117 is a quadrangular large-size panel made of stainless steel.

The carrier 117 has a carrier front 1171 and a carrier back 1172 , and the carrier front 1171 is a plane.

The die 113 is bonded and fixed on the carrier 117 by the adhesive layer 121 .

The adhesive layer 121 can be formed on the front surface 1171 of the carrier by lamination, printing, spraying, coating and the like. In order to facilitate the separation of the carrier board 117 and the die 113 that has been molded on the back in the subsequent process, the adhesive layer 121 is preferably made of an easily separable material, for example, a heat-separatable material is used as the adhesive layer 121 .

Place the side of the temporary support board 300 on which the metal frame 200 is mounted facing the front surface 1171 of the carrier board. The surface area of the temporary support board 300 is the same as that of the carrier board 117, and the shape is also the same. Align and contact the two, and the metal frame 200 can be pasted. Attach to the adhesive layer 121 , then peel off the temporary support plate 300 , and remove the adhesive layer 301 on the metal frame 200 , that is, the attachment of the metal frame 200 is completed.

In this step, preferably, the metal frame 200 is aligned on the carrier board 117 by pre-formed alignment marks on the carrier board 117 and the metal frame 200 (the mark is not shown in the figure), by The adhesive layer 301 adheres the metal frame 200 to the carrier 117 .

In addition, the metal foil or metal sheet can also be attached to the temporary support plate 300 through the adhesive layer 301 on the temporary support plate 300, and then the metal foil or metal sheet can be etched into a desired pattern to form a patterned metal frame. 200, and then transfer the metal frame 200 to the carrier 117.

The side of the metal frame 200 facing the carrier 117 is defined as the front of the metal frame, and the side facing away from the carrier 117 is defined as the back of the metal frame. Metal structure front and metal structure back, metal unit front and metal unit back, metal feature front and metal feature back are defined accordingly.

FIG. 10 shows an embodiment of disposing the die 113 on the carrier 117 in step S105 .

Since the metal frame 200 has been attached to the adhesive layer 121 on the front surface 1171 of the carrier board, which is shown as the connection pad 201 in FIG. , in the present disclosure, the die 113 is pasted in the vacancy 202 of the metal frame 200 , and optionally one vacancy 202 corresponds to one die 113 or one vacancy 202 corresponds to a plurality of die 113 . Preferably, position marks for arrangement of crystal grains 113 are set on the carrier board 117, and the marks can be formed on the carrier board 117 by means of laser, mechanical engraving, etc. When pasting, aim and align with the pasting position on the carrier board 117 . FIG. 10 is only an exemplary diagram. FIG. 10 only shows that the form of the crystal grain 113 pasted on the adhesive layer 121 of the carrier 117 is a crystal grain with a protective layer 107 and a protective layer opening 109 as shown in FIG. 6a. grains 113; the grains attached to the adhesive layer 121 of the carrier plate 117 can also be in the form of grains with the chip conductive layer 130, the protective layer 107 and the protective layer opening 109 shown in FIG. A grain form with wafer conductive layer 130 and protective layer 107 is shown in 6c. Meanwhile, the metal frame 200 pasted on the adhesive layer 121 can also be a metal frame 200 that only cuts but does not remove the connecting rod 203 as shown in FIG. 8 a , or can be a metal frame 200 with a complete connecting rod 203 .

As shown in Figure 10, one metal unit corresponds to one crystal grain 113, the number of crystal grains 113 on the carrier plate 117 is the same as the number of metal units on the carrier plate 117, and the arrangement of the crystal grains 113 is the same as that of the metal units on the carrier plate 117. corresponding to the arrangement. The number and arrangement of the metal units are not limited to the one shown in FIG. 10 , but can be customized according to actual needs.

In addition, one metal unit can correspond to multiple crystal grains 113, and the multiple crystal grains 113 are placed in the predetermined vacancy 202, especially the multiple crystal grains are multiple crystal grains with different functions, arranged according to the actual product requirements In the metal unit on the carrier board 117, it is packaged, and after the package is completed, it is cut into multiple packages; thus one package includes multiple dies to form a multi-chip module (multi-chip module, MCM) , and the positions of multiple grains can be freely set according to the needs of actual products.

The installation sequence shown in FIGS. 9 to 10 is to first install the metal frame 200 on the carrier 117, and then install the die 113 on the carrier 117, but it is only exemplary here, and it can also be the first to install the die 113 on the carrier 117. The particles 113 are installed on the carrier 117, and then the metal frame 200 is installed on the carrier 117.

Step S106 : Form a plastic encapsulation layer 123 on the carrier 117 .

As shown in FIG. 11 , the plastic encapsulation layer 123 covers the entire carrier 117 for encapsulating all the die 113 and the metal frame 200, which is shown as a connection pad 201 in FIG. After the carrier plate 117 is peeled off, the next packaging step can be continued on the restructured flat plate structure.

The side of the molding layer 123 in contact with the front side 1171 of the carrier board or the adhesive layer 121 is defined as the front side 1231 of the molding layer. The side of the plastic encapsulation layer 123 facing away from the front surface 1171 of the carrier board or the adhesive layer 121 is defined as the back surface 1232 of the plastic encapsulation layer.

Preferably, the front side 1231 of the molding layer and the back side 1232 of the molding layer are substantially flat and parallel to the front side 1171 of the carrier.

The plastic sealing layer 123 can be formed by paste printing, injection molding, thermocompression molding, compression molding, transfer molding, liquid sealant molding, vacuum lamination, or other suitable molding methods. The plastic sealing layer 123 can be made of organic composite materials, resin composite materials, polymer composite materials, polymer composite materials, such as epoxy resin with fillers, Ajinomoto buildup film (ABF) or other polymers with suitable fillers.

In one embodiment, the plastic sealing layer 123 is formed by using an organic/inorganic composite material by molding.

Optionally, before forming the plastic encapsulation layer 123, some pretreatment steps can be performed, such as chemical cleaning and plasma cleaning, to remove impurities on the surface of the crystal grain 113 and the metal frame 200, so that the plastic encapsulation layer 123 and the crystal grain 113, the metal frame 200 and the carrier 117 can be connected more closely without delamination or cracking.

Preferably, the thermal expansion coefficient of the plastic sealing layer 123 is 3~10 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the plastic sealing layer 123 is 5 ppm/K; in another preferred embodiment, the thermal expansion coefficient of the plastic sealing layer 123 is 7 ppm/K; in yet another preferred embodiment, the thermal expansion coefficient of the plastic encapsulation layer 123 is 10 ppm/K.

Preferably, the plastic encapsulation layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients.

The thermal expansion coefficient of the plastic sealing layer 123 is selected as 3~10 ppm/K and the thermal expansion coefficient of the protective layer 107 is selected to be the same or similar. During the heating and cooling process of the molding process, the expansion and contraction between the protective layer 107 and the plastic sealing layer 123 The degree is consistent, the two materials are not easy to generate interface stress, and the low thermal expansion coefficient makes the thermal expansion coefficients of the plastic sealing layer 123, the protective layer 107 and the crystal grain 113 close, so that the interface of the plastic sealing layer 123, the protective layer 107 and the crystal grain 113 is closely combined. Avoid interface layer separation.

During the use of the packaged chip, it is often necessary to undergo thermal cycles. Since the thermal expansion coefficients of the protective layer 107, the plastic sealing layer 123 and the die 113 are similar, during the thermal cycle, the protective layer 107, the plastic sealing layer 123 and the die 113 The interface fatigue of 113 is small, and the interface gap between the protective layer 107, the plastic encapsulation layer 123 and the crystal grain 113 is not easy to appear, so that the service life of the chip is increased, and the chip can be used in a wide range of fields.

The difference in thermal expansion coefficient between the crystal grain 113 and the plastic encapsulation layer 123 will also cause warping of the panel assembly after plastic encapsulation. Due to the warping phenomenon, it is difficult to accurately position the crystal grain 113 in the panel assembly in the subsequent conductive layer formation process. The position has a great influence on the formation process of the conductive layer.

In particular, in the large panel packaging process, due to the large size of the panel, even a slight warpage of the panel will cause the grains of the outer peripheral part of the panel to be far away from the center, resulting in a larger size than before molding. Therefore, in the large-scale panel packaging process, solving the warpage problem has become one of the keys to the entire process. The warpage problem even limits the enlargement of the panel size and becomes a technical barrier in large-size panel packaging.

The thermal expansion coefficient of the protective layer 107 and the plastic sealing layer 123 is limited within the range of 3-10 ppm/K, and preferably the plastic sealing layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients, which can effectively avoid the occurrence of warpage of the panel assembly, Encapsulation processes using large panels are realized.

At the same time, during the molding process, since the molding pressure will generate pressure on the back of the die 113 toward the carrier 117, this pressure is easy to press the die 113 into the adhesive layer 121, so that the die 113 is formed in the process of forming the molding layer 123. After the molding layer 123 is formed, the crystal grain 113 and the front surface 1231 of the molding layer are not in the same plane, and the surface of the crystal grain 113 protrudes from the front surface 1231 of the molding layer, forming a stepped structure. In the subsequent formation process of the panel-level conductive layer, the panel-level conductive layer will correspondingly have a stepped structure, making the packaging structure unstable.

When the active surface 1131 of the die has a protective layer 107 with material properties, it can act as a buffer under the molding pressure to prevent the die 113 from sinking into the adhesive layer 121, thereby avoiding the formation of a stepped structure on the front side of the molding layer 1231.

In order to expose the metal frame 200, the plastic sealing layer 123 also needs to be thinned, which can be reduced by mechanically grinding or polishing the front side 1231 of the plastic sealing layer, and the thickness of the plastic sealing layer 123 is reduced to the back of the metal frame 200, thereby exposing the metal frame 200 surface features. As shown in FIG. 12, when the thickness of the metal frame 200 is thicker than that of the die 113, the plastic encapsulation layer can be further thinned to the back of the die 113, and the metal frame 200 (shown as the connection pad of the connection pad 201 in the figure) backside 2012) and the backside of die 113 are exposed. For another example, if the die 113 is thicker than the metal frame 200 , then the molding layer 123 is thinned until the connection pad backside 2012 is exposed from the molding layer 123 . During this process, the die 113 is further thinned to the same thickness as the connection pad 201 .

Therefore, it has a shorter conductive path and lower resistance, which is suitable for power modules.

Step S107 : forming a second conductive structure 140 on the back surface 1132 of the die and the second dielectric layer 170 .

The second conductive structure 140 may be formed by patterning a conductive layer at the panel level.

For example, the second conductive structure 140 can be formed by a photolithography process. Referring to FIG. 13 , a dry film (dry film) 160 is formed to cover the backside of the die 1132 , the backside of the plastic encapsulation layer 1232 and the backside of the connection pad 2012 . The dry film 160 is a photosensitive film that can be used as a plating mold. Dry film 160 may be adhered by a rolling process in which heated rollers apply controlled pressure to press dry film 160 onto die backside 1132 , encapsulant backside 1232 , and connection pad backside 2012 while heating dry film 160 . Alternatively, the dry film 160 can be adhered by a vacuum process, when the air near the dry film 160 is sucked to create a vacuum, the elastic device presses the dry film 160 to the die backside 1132, the mold backside 1232 and the connection pad backside 2012 onwards.

Referring to FIG. 14 , a photolithography process is performed on the dry film 160 to form a patterned dry film 162 . In photolithography, a mask (not shown) is positioned over dry film 160 to cover selected portions of dry film 160, while unselected portions of dry film 160 are exposed to a light source through the mask to form patterned dry film 162. A plurality of dry film openings 163 . Thus, at least a portion of the die backside 1132 (in whole or in part) and the connection pad backside 2012 is exposed through the dry film opening 163 of the patterned dry film 162 .

Referring to FIG. 15 , the second panel level trace (panel level trace) 142 is formed by filling the dry film opening 163 of the patterned dry film 162 with materials such as copper, gold, silver, tin, aluminum or a combination thereof, Other suitable conductive materials may also be formed by using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition processes.

Referring to FIG. 16 , another dry film 164 is formed to cover the patterned dry film 162 and the second panel-level conductive trace 142 . Similar to the dry film 160 , the dry film 164 is a photosensitive film that can be formed by a rolling process or a vacuum process as described above.

Referring to FIG. 17 , the dry film 164 can also be subjected to a photolithography process to form a patterned dry film 166 . The patterned dry film 166 has a plurality of dry film openings 167 from which at least a portion of the second panel level conductive trace 142 is exposed. The patterned dry film 162 may be completely or partially covered by the patterned dry film 166 .

18, the second panel level conductive pillar 144 is formed by filling the dry film opening 167 with conductive material such as copper, gold, silver, tin and aluminum or a combination thereof, or by PVD, CVD, sputtering, electrolysis Electroplating, electroless plating, or other suitable metal deposition processes from other suitable conductive materials. In this way, the second panel-level conductive posts 144 are electrically connected to the second panel-level conductive traces 142 , and further electrically connected to the connection pads 201 of the metal frame 200 .

As shown in FIG. 19 , the patterned dry film 162 and the patterned dry film 166 are removed; while the second panel level conductive trace 142 and the second panel level conductive pillar 144 remain on the die backside 1132 and the connection pad backside 2012 . The second panel-level conductive trace 142 and the second panel-level conductive pillar 144 collectively define a second conductive structure 140 . In particular, the second conductive structure 140 is manufactured at the panel level, thereby increasing throughput and reducing manufacturing cost.

The pattern of the second conductive structure 140 in FIG. 19 is only exemplary, and it may have various patterns according to specific circuit designs.

Referring to FIG. 20 , the second dielectric layer 170 is formed to completely encapsulate the second conductive structure 140 (including the second panel-level conductive trace 142 and the second panel-level conductive post 144 ). In addition, the second dielectric layer 170 can also cover the portion of the plastic encapsulation layer backside 1232 and the connection pad backside 2012 not covered by the second panel-level conductive traces 142 . The second dielectric layer 170 may include epoxy molding compound in film, particle or liquid form. As mentioned above, the second dielectric layer 170 may have similar composition and properties as the encapsulant layer 123 . For example, the second dielectric layer 170 has the same or similar coefficient of thermal expansion (CTE) as that of the plastic encapsulation layer 123 , so that the interfacial stress between the second dielectric layer 170 and the plastic encapsulation layer 123 is less likely to occur.

In order to expose the second panel-level conductive pillars 144 , the second dielectric layer 170 needs to be thinned. Referring to FIG. 21 , the second dielectric layer 170 is thinned by mechanically grinding or polishing the back surface 1702 of the second dielectric layer, so that the second panel-level conductive pillars 144 are exposed from the second dielectric layer 170 .

Step S108 : peeling off the carrier (or referred to as the first carrier) 117 to form the panel assembly 150 with the second conductive structure 140 .

Please refer to FIG. 22 , after the carrier plate 117 is peeled off, the protective layer 107 on the active surface 1131 of the die, the lower surface of the metal frame 200 (represented by the front side 2011 of the connection pad 201 in the figure) and the front side 1231 of the plastic encapsulation layer be exposed. Arrows in FIG. 22 show separation of the carrier plate 117 from the panel assembly 150 .

After the carrier board 117 is separated, the structure of the plastic encapsulation layer 123 covered with the die 113 and the metal frame 200 is defined as the panel assembly 150 , which has the second conductive structure 140 .

13 to 22 show that the second panel-level conductive trace 142 and the second panel-level conductive pillar 144 respectively have a conductive layer. However, it can be understood that before separating the first carrier 117 from the panel assembly 150, the second panel-level conductive traces 142 and the second panel-level conductive posts 144 can also have multiple layers by repeating FIGS. 13 to 20 . a conductive layer.

Step S109 : as shown in FIG. 23 a , invert the panel assembly 150 having the second conductive structure 140 onto another carrier (also referred to as a second carrier) 118 .

In some embodiments, the adhesive layer 122 can be formed between the second carrier 118 and the back surface of the second dielectric layer 1702 by lamination, printing, spraying, coating and the like. In order to facilitate the separation of the carrier 118 and the back surface of the second dielectric layer 1702 in the subsequent process, the adhesive layer 122 is preferably made of an easily separable material, for example, a heat-separatable material is used as the adhesive layer 122 .

Step S110 : forming the first conductive structure 129 on the active surface 1131 of the die by panel-level process.

Referring to FIG. 23 b , the protective layer opening 109 is filled to form a conductive filled via hole 124 . A panel-level conductive layer is formed on the surface of the protective layer 107, and the panel-level conductive layer is connected to the electrical connection point 103 on the active surface 1131 of the crystal grain through the chip conductive layer 130 and/or the conductive filling via 124, and is connected to the metal frame 200 (in The connection is shown as connection pad 201). The panel-level conductive layer can be one layer or multiple layers.

As shown in FIG. 23 b , the panel-level conductive layer is embodied in the figure as a panel-level conductive trace 125 (or referred to as a first panel-level conductive trace). Optionally, the conductive filling of the vias 124 and the panel-level conductive traces 125 are performed in the same panel-level conductive layer formation step. Similar to the second panel-level conductive traces 142 , the conductive filled vias 124 and the panel-level conductive traces 125 can be formed using a method of forming a patterned conductive layer, such as a photolithography process. The conductive filled via hole 124 and the panel conductive trace 125 can be made of materials such as copper, gold, silver, tin, aluminum or a combination thereof, and can also be other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, Electroless plating process, or other suitable metal deposition process.

At least a portion of the panel-level conductive traces 125 are connected to the electrical connection points 103 on the active surface 1131 of the die through the conductive filled vias 124 and connected to the connection pads 201, and the panel-level conductive traces 125 and the conductive filled vias 124 connect Electrical connection points 103 on the active side of the die lead to connection pads 201 . Meanwhile, the panel-level conductive trace 125 is also electrically connected to the second conductive structure 140 through the connection pad 201 . Thus, the die 113 can be electrically backgrounded (ie, the ground of the die 113 is at the backside of the die 1132 ) via the conductive filled vias 124 , the panel level conductive traces 125 and the connection pads 201 to the second conductive structure 140 . Since the second conductive structure 140 can provide a large ground contact area for the electrically back-grounded die 113 , the die 113 has superior electrical performance when used in a power module.

The pattern traces of the panel-level conductive traces 125 in FIG. 23b are merely exemplary, and may have various pattern traces depending on the specific circuit design.

Optionally, the conductive filled vias 124 and the panel-level conductive traces 125 may also be formed in steps, first forming the conductive filled vias 124 and then forming the panel-level conductive traces 125 .

When the conductive filled via hole 124 has been formed in the previous step of applying the protective layer, the step of forming the panel-level conductive layer can be directly performed.

When the protective layer opening 109 has not been formed in the previous step of applying the protective layer, a step of forming the protective layer opening 109 needs to be included.

In some embodiments, the first panel-level conductive pillars 127 are formed on the first panel-level conductive traces 125 by a panel-level method of forming a patterned conductive layer.

For example, the first panel-level conductive pillar 127 can be formed by a photolithography process, similar to the second panel-level conductive pillar 144 . The first panel-level conductive pillars 127 can be made of copper, gold, silver, tin, aluminum and other materials or combinations thereof, and can also be other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electroless plating process , or formed by other suitable metal deposition processes. The panel-level conductive trace 125 and the first panel-level conductive pillar 127 together define a first conductive structure 129 . Therefore, the die 113 can be electrically connected to an external component (eg, a printed circuit board (PCB)) by filling the via 124 and the first conductive structure 129 (including the panel-level conductive trace 125 and the first panel-level conductive post 127 ).

The pattern of the first panel-level conductive pillars 127 in FIG. 23b is only exemplary, and it may have various patterns according to specific circuit designs.

The first dielectric layer 146 is formed to encapsulate the first conductive structure 129 , and the first panel-level conductive pillars 127 are exposed from the first dielectric layer 146 after a grinding process (eg, mechanical grinding or polishing). The first dielectric layer 146 may include epoxy molding compound in film, particle or liquid form. In addition, the first dielectric layer 146 may have similar composition and properties as the above-mentioned plastic encapsulation layer 123 . For example, the first dielectric layer 146 has the same or similar coefficient of thermal expansion (CTE) as that of the plastic encapsulation layer 123 , so that the interfacial stress between the first dielectric layer 146 and the plastic encapsulation layer 123 is less likely to occur.

FIG. 24 shows that the first panel-level conductive trace 125 and the first panel-level conductive post 127 each have a conductive layer. However, it should be understood that the first panel-level conductive traces 125 and the first panel-level conductive pillars 127 may have multiple conductive layers by repeating the above process before separating the second carrier 118 from the panel assembly 150 .

In addition, the second carrier 118 is stripped to form a panel assembly 150 having the second conductive structure 140 encapsulated in the second dielectric layer 170 and the first conductive structure encapsulated in the first dielectric layer 146 129.

Referring to FIG. 24 , after the second carrier 118 is peeled off, the second dielectric layer 170 and the second panel-level conductive pillar 144 of the second conductive structure 140 are exposed. The arrows in FIG. 24 show the separation of the second carrier plate 118 from the panel assembly 150 . Thus, the die 113 may be electrically and thermally connected to external components via the first conductive structure 129 on the active side 1131 of the die and the second conductive structure 140 on the back side 1132 of the die.

Step S111 : dicing to form a plurality of packaging chips 400 .

Referring to FIG. 25 , a plurality of packaging chips 400 are formed by cutting the panel assembly 150 to separate the packaging monomers. Cutting can be performed by, for example, mechanical or laser. The two-dot chain line in Fig. 25 shows the cutting line SL (also called sawing line) along which the separation takes place.

When the plastic-encapsulated metal frame 200 is a metal frame 200 including connecting rods 203 as shown in FIG. The wafer 500 does not include connecting rods, so that each metal feature in the metal unit of the metal frame 200 is independent.

Preferably, before or after the dicing and separation step, a surface treatment layer 131 is formed on the first conductive structure 129 and/or the second conductive structure 140 exposed from the packaging wafer 400 . Optionally, the surface treatment layer 131 is formed by electroplating, electroless electroplating or other suitable methods. For example, the surface treatment layer 131 adopts electroless nickel immersion gold (electroless nickel immersion gold, ENIG), electroless nickel electroless palladium immersion gold (electroless nickel electroless palladium immersion gold, ENEPIG), tin (Tin), nickel gold ( NiAu plating) or their combination.

Optionally, the surface treatment layer 131 can also be configured to realize the electrical back-grounding (electrical back-grounding) of the die 113 in the package chip 400, that is, the surface treatment layer 131 connects the backside of the die 1132 to a specific connection according to the specific design of the circuit. The connection pads 201 on the backside ground are electrically connected together (specifically connecting the connection pads on the backside ground is: the connection pads are connected to the electrical connection point on the active surface of the die through the conductive structure).

FIG. 26 is an exemplary schematic illustration of packaged die 400 detached from panel assembly 150 and in use. In use, the packaged chip 400 is connected to a printed circuit board (PCB) or substrate 410 by at least one metal feature, represented as a connection pad 201 in the figure. In addition, the passive element 420 can also be mounted on the second conductive structure 140 and electrically connected to the die 113 in the packaging chip 400 . Passive element 420 may be a resistor 740, a capacitor 742, an inductor 744, or a combination thereof.

In addition to dissipating heat to the printed circuit board (PCB) or substrate 410 through the first conductive structure 129, a heat sink 430 can also be mounted on the second conductive structure 140, thereby filling the via hole 124, the first The conductive structure 129 , the connection pad 201 of the metal frame 200 and the second conductive structure 140 dissipate the heat generated by the die 113 . In particular, the connection pads 201 are exposed from the side surfaces of the package wafer 400 . Therefore, the packaging chip 400 has a three-side heat dissipation design, thereby having an efficient cooling function, that is, the first side dissipates heat from the active surface 1131 of the die through the first conductive structure 129; 140 for dissipating heat; and the third side, dissipating heat from the side through the connection pad 201 .

In addition, the ground label 440 shows that the package chip 400 is electrically back-grounded from the die backside 1132 through the second conductive structure 140 . Compared with traditional grounding, the electrical back grounding of the second conductive structure 140 can provide a larger contact area, making the package chip 400 more stable and safer electrical grounding, especially for large electric flux (electric flux) power module.

Instead of the passive component 420 and/or the heat sink 430 , another package die 400 may also be mounted on the second conductive structure 140 of the package die 400 to form a package-on-package (POP) configuration.

FIG. 27 shows a flowchart of another wafer packaging method 20 according to an exemplary embodiment of the present disclosure. Compared with the chip packaging method 10 , the chip packaging method 20 includes all the steps from S201 to S211 , and an additional step AS between S206 and S207 , namely forming and filling a plurality of voids 502 in the plastic encapsulation layer 123 .

28 to 30 show additional schematic diagrams of making the panel assembly 152 using the wafer packaging method 20 . The chip packaging method 20 has the same steps S201 to S211 and an additional step AS as the chip packaging method 10 . Therefore, the second chip packaging method 20 will not repeat the same steps S201 to S211 , and the same reference numerals in FIGS. 2 to 25 are used here to illustrate the same or similar features. Additional steps AS are described below.

As shown in FIG. 28 , the height of the connection pad 201 is greater than the thickness of the die 113 ; so that the plastic layer 123 becomes thinner until the backside 2012 of the connection pad is exposed from the plastic layer 123 , while the die 113 is still completely encapsulated in the plastic layer 123 . Then a plurality of voids 502 are formed up to the die backside 1132 of the die 113 by the molding layer 123 . Therefore, a portion of the die backside 1132 is exposed from the mold encapsulation layer 123 through the void 502 . Void 502 may be formed by any suitable process, such as laser patterning, mechanical patterning, laser drilling, or a combination thereof.

Similar to conductive filled via 124 , void 502 is also filled with a conductive medium. The conductive medium can be materials such as gold, silver, copper, tin, aluminum or combinations thereof, and can also be other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable A metal deposition process is formed to fill the void 502 with a conductive medium to form a conductive filled void 504 .

Referring to FIG. 30 , the second panel-level conductive trace 142 is formed on the conductive fill void 504 and connected to the conductive fill void 504 . Therefore, the die 113 can still be electrically backgrounded from the die backside 1132 via the second panel-level conductive trace 142 and the second panel conductive pillar 144 of the second conductive structure 140 .

Similarly, a second dielectric layer 170 is formed to encapsulate the second conductive structure 140 , wherein the second conductive structure 140 is exposed from the second dielectric layer 170 after a grinding process (eg, mechanical grinding or polishing). Additionally, the second dielectric layer 170 may have similar composition and properties as the encapsulant layer 132 described above.

Referring to FIG. 30 , a plurality of package chips 500 are formed by cutting the panel assembly 152 to separate the package monomers. Cutting can be performed using, for example, mechanical or laser. The two-dot chain line in Fig. 30 shows the cutting line SL (also called sawing line) along which the separation takes place.

FIG. 31 is a schematic diagram of a packaging chip 500 formed after cutting the panel assembly 152 manufactured according to FIGS. 28 to 30 . The same reference numerals as in FIG. 26 are also used herein to describe the same or similar features in FIG. 30 . Similar to the package chip 400 , the connection pads 201 are also exposed on the side surface of the package chip 500 . Therefore, the packaged chip 500 also has a three-sided heat dissipation design, which is beneficial to the efficient cooling function.

Compared with the package chip 400, when the void 502 is filled by the plastic encapsulation layer 123, the second panel-level conductive trace 142 has a larger contact area, so the second conductive structure 140 of the package chip 500 is from the die backside 1132 to the die 113 exerts less stress. In addition, the larger contact area also connects the second panel-level conductive trace 142 and the molding layer 123 more firmly, which allows the second panel-level conductive trace 142 to have a thinner thickness; and the second panel-level conductive trace The wires 142 have correspondingly less weight, which further reduces the stress exerted on the die 113 from the die backside 1132 .

Instead of the passive components 420 and/or the heat sink 430 , another package die 500 may be mounted on the second conductive structure 140 of the package die 500 to form a package on package (POP) configuration. Alternatively, one package chip 400 may be mounted on the second conductive structure 140 of the package chip 500 to form a package-on-package (POP) configuration. Alternatively, the packaged die 500 may be mounted on the second conductive structure 140 of a packaged die 400 to form a package-on-package configuration.

32 to 34 are schematic flow diagrams illustrating variations of another panel assembly 154 in FIGS. 28 to 30 . Similarly, steps S101 to S111 of the chip packaging method 10 will not be repeated; therefore, the same reference numerals are used here to describe the same or similar features in FIGS. 2 to 25 and FIGS. 28 to 30 . Furthermore, the additional steps AS of the chip packaging method 20 are changed to manufacture the panel assembly 154 compared to the panel assembly 152 shown in FIGS. 28 to 30 . Accordingly, variations of the additional steps AS for manufacturing the panel assembly 154 are described below.

Referring to FIG. 32 , the panel assembly 154 has a structure similar to that of the panel assembly 152 in FIG. 28 , except that an encapsulation layer 610 is formed on the die backside 1132 of the die 113 , which is exposed from the encapsulation layer 123 . The molding layer 610 can be formed by paste printing, injection molding, thermocompression molding, compression molding, transfer molding, liquid sealant molding, vacuum lamination, or other suitable molding methods. For example, the plastic encapsulation layer 610 is formed on the die backside 1132 by film molding.

The plastic sealing layer 610 can be made of the same material as the plastic sealing layer 123, such as organic composite materials, resin composite materials, polymer composite materials, polymer composite materials, such as epoxy resin with fillers, ABF (Ajinomoto build-up film) Or other polymers with suitable fillers. Alternatively, the plastic encapsulation layer 610 may be made of a material different from that of the plastic encapsulation layer 123 . Compared with the molding layer 123 , a different material may have better compatibility with the second panel-level conductive trace 142 to more stably fix the second conductive structure 140 and the molding layer 123 .

Referring to FIG. 33 , voids 502 are formed in the plastic encapsulant layer 610 by any suitable process, such as laser patterning, mechanical patterning, laser drilling or a combination thereof; therefore, the backside of the die 113 A portion of 1132 is exposed from the molding layer 610 through the void 502 . Then fill the conductive medium in the gap 502, the conductive medium can be materials such as gold, silver, copper, tin, aluminum or their combination materials, and can also be other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, Electroless plating process, or other suitable metal deposition process, and the conductive medium is filled in the void 502 to form the conductive filled void 504 .

Referring to FIG. 34 , the packaging monomers are separated by cutting the panel assembly 154 to form a plurality of packaging chips 550 . Cutting can be performed by, for example, mechanical or laser. The two-dot chain line in Figure 34 shows the cutting line SL (also called sawing line) along which the separation takes place.

FIG. 35 is a schematic diagram of packaged wafers formed after dicing of the modification of the panel assembly 154 manufactured according to FIGS. 32 to 34 . Packaged die 550 has the same structure as packaged die 500 except that a void 510 is formed in the molded encapsulation layer 610 on the die backside 1132 as described above. In addition, the passive components 420 and/or the heat sink 430 may be mounted on the second conductive structure 140 of the package die 550 .

Alternatively, another package chip 550 may be mounted on the second conductive structure 140 of the package chip 550 to form a package-on-package (POP) configuration. Alternatively, one packaged die 400, 500 may be mounted on the second conductive structure 140 of the packaged die 550 to form a package-on-package configuration. Alternatively, the packaging die 550 may be mounted on the second conductive structure 140 of a packaging die 400, 500 to form a layer stack package configuration.

In the case that the first conductive structure 129 and the second conductive structure 140 are made of metal or metal material (such as copper), they are connected with the die 113, the metal frame 200 (represented as the connection pad 201 here), the plastic encapsulation layer 123 and Compared with other elements mentioned above (such as the protective layer 107), it has a relatively heavy weight. Preferably, the first conductive structure 129 and the second conductive structure 140 have substantially the same weight to balance the packaging die 400 , 500 , 550 as a whole. In other words, if both the first conductive structure 129 and the second conductive structure 140 are made of the same metal or metallic material, such as copper, they are of substantially equal quality.

FIG. 36 a illustrates a schematic diagram of a packaged wafer 600 having a first die 602 and a second die 604 , using the die packaging method 10 of FIG. 1 . Dies 602, 604 may be conventional silicon cores, silicon carbide (SiC) cores, gallium nitride (GaN) cores, or combinations thereof. Die 602, 604 may be of any suitable design depending on the desired application. For example, the die 602, 604 may be a first field effect transistor (FET) and a second field effect transistor (FET) placed side by side.

The packaged chip 600 has a package structure similar to that of the packaged chip 400 ; therefore, the same reference numerals are used herein to describe the same or similar features in FIG. 26 . The first conductive structure 129 and the second conductive structure 140 are formed on both sides of the first and second crystal grains 602 , 604 . Therefore, the first conductive structure 129 is connected to the first die active surface 6021 of the first die 602 and the second die active face 6041 of the second die 604; and the second conductive structure 140 is connected to the first die 602 The first die back side 6022 of the second die and the second die back side 6042 of the second die 604 .

Similarly, the first conductive structure 129 and the second conductive structure 140 are also connected by the connection pad 201 in the package chip 600 . Thus, the first and second die active faces 6021 , 6041 are electrically connected to the second conductive structure 140 for enabling electrical back grounding of the first and second die 602 , 604 in the package wafer 600 .

Similarly, package chip 600 also has a three-side heat dissipation design, which is conducive to efficient cooling function, that is, the first side, from the active surface 6021, 6041 of the die via the first conductive structure 129; the second side, from the back side of the die 6022, The back side of the 6042 passes through the second conductive structure 140 ; and the third side dissipates heat from the side through the connection pad 201 . In addition, the heat sink 430 can be installed on the second conductive structure 140 to accelerate the dissipation of the heat from the packaging chip 600 .

Optionally, the packaged chip 600 may include a large-sized heat sink 430 (referred to as a large heat sink), which can further enhance the heat dissipation of the first and second dies 602 , 604 . For example, if the first die 602 takes up more space than the second die 604 , the large heat sink 430 may be mounted over the first die 602 . In this case, the heat generated by the second die 604 can still be dissipated to the large heat sink 430 through the first conductive structure 129 , the connection pad 201 and the second conductive structure 140 .

Alternatively, a large-sized passive component 420 may be mounted on the second conductive structure 140 and the first die 602; and a small-sized heat sink 430 (called a small heat sink) may be mounted on the second conductive structure 140 and on the second die 604 . In this case, the heat generated by the first die 602 can still be dissipated to the small heat sink 430 through the first conductive structure 129 , the connection pad 201 and the second conductive structure 140 .

In particular, both the first die 602 and the second die 604 have a face-down configuration (face-down configuration), which are connected to external components (such as printed circuit board (PCB) or substrate (substrate)), and does not use solder bumps (solder bumps) or solder balls (solder balls). For example, both the first active surface of the die 6021 and the active surface of the second die 6041 are directly connected to an external component (such as a printed circuit board or a substrate) through the conductive filled via 124 and the first conductive structure 129 . In other words, the packaged chip 600 using the above-mentioned direct flip-chip process no longer needs the bumping and reflowing process using solder bumps or solder balls in the conventional flip-chip process. Considering the low electrical and thermal conductivity of solder bumps or solder balls, the direct flip-chip process of the present application enables the packaged chip 600 to have better electrical and thermal properties, which is essential for greater electrical flux during operation And the power module that comes with heat is very important. FIG. 36 a shows that the packaged chip 600 can be directly connected to the printed circuit board (PCB) or substrate (substrate) 410 via the first panel-level conductive pillar 127 of the first conductive structure 129 .

Alternatively, a conventional flip-chip process may also be applied to packaged wafer 600, if desired. FIG. 36 b shows that solder bumps or balls 412 are formed under the first panel-level conductive pillars 127 of the first conductive structure 129 for connecting the package die 600 to a printed circuit board (PCB) or substrate 410 .

The face-down configuration of the first and second die 602, 604 will make the panel level packaging method easier and more efficient. For example, in step S105 (called the panel level packaging die transfer process (reconstruction process)), the first and second dies 602, 604 (in FIG. 10, die 113) can be accurately arranged and adhered to the carrier 117, because the features (such as alignment alignment marks (not shown)).

Instead of the passive component 420 and/or the heat sink 430 , another package die 600 may be mounted on the second conductive structure 140 of the package die 600 to form a package-on-package (POP) configuration. Alternatively, one or more package dies 400, 500, 550 may be mounted on the second conductive structure 140 of the package die 600 to form a layer stack package configuration.

Similarly, in the case where the first conductive structure 129 and the second conductive structure 140 are made of metal or a metal material (such as copper), the crystal grain 113, the connection pad 201, the plastic encapsulation layer 123 and the above-mentioned other elements (such as the protective layer 107), which has a relatively heavy weight, compared to . Preferably, the first conductive structure 129 and the second conductive structure 140 have substantially the same weight to balance the packaging chip 600 as a whole. In other words, the first conductive structure 129 and the second conductive structure 140 are of substantially equal quality if they are made of the same metal or metallic material such as copper.

Fig. 37a, Fig. 37b and Fig. 37c are schematic diagrams of a chip package 700 for a power module proposed according to an exemplary embodiment of the present disclosure. The chip package 700 is fabricated by the chip package method 10 in FIG. 1 . Accordingly, identical or similar features to those in FIGS. 2 to 25 are labeled with the same reference numerals.

Fig. 37a shows a top view of a panel assembly 710 comprising a plurality of die packages 700 (eg, four die packages 700 shown in Fig. 37a) prior to singulation. A plurality of chip packages 700 are arranged in a matrix configuration. The chip package 700 includes a first die 602 and a second die 604 of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and a driving circuit (also referred to as drive element) 720. Therefore, the chip package 700 can be used as a DrMOS power module. For example, the first die 602 is a low side MOSFET optimized for ultra-fast switching, while the second die 604 is a high side MOSFET optimized for minimal conduction losses.

Therefore, the metal frame 200 includes a plurality of metal units (eg, four metal units as shown in FIG. 37 a ). Each metal unit surrounds the first die 602 , the second die 604 and the driving circuit 720 to form a chip package 700 . In addition, the chip package 700 is manufactured by cutting the panel assembly 710 . Fig. 37a shows the cutting line SL (also called sawing line) along which the separation takes place.

FIG. 37b shows a cross-sectional view of the die package 700 along the dashed line L1 in FIG. 37a. The chip package 700 has a similar structure to the packaged chip 600 except that the second die 604 is replaced by the driving circuit 720 . The driving circuit 720 is thinner than the first die 602 , and the driving back surface 7042 of the driving circuit 720 does not directly contact the second conductive structure 140 . Therefore, a space 730 is formed between the driving back surface 7022 and the second conductive structure 140 . Using the chip packaging method 10 , the space 730 is filled with the plastic encapsulation layer 123 as shown in FIG. 11 . In this way, heat can still be dissipated from the driving back surface 7202 to the second conductive structure 140 through the plastic encapsulation layer 123 .

Passive components 420 may be mounted on the second conductive structure 140, such as a resistor 740 and a capacitor 742 mounted above the first die 602 and the driving circuit 720, respectively, and a capacitor mounted between the resistor 740 and the driving circuit 720. Inductor 744 . Therefore, the first die 602 and the driving circuit 720 are electrically connected to the passive element 420 by filling the conductive via 124, the first conductive structure 129, the connection pad 201 and the second conductive structure 140 for transmitting electrical signals;

Likewise, the chip package 700 can also implement electrical back grounding through the second conductive structure 140 .

In particular, the chip package 700 retains a three-side heat dissipation design along the dotted line L1 in FIG. Via the first conductive structure 129 ; the second side, from the active surface 6022 of the second die and the driving back surface 7202 of the driving circuit 720 via the second conductive structure 140 ; and the third side, the connection pad 201 dissipates heat from the side.

Fig. 37c shows a cross-sectional view of the die package 700 along the dotted line L2 in Fig. 37a. Die package 700 has a similar structure to packaged wafer 600 such that first die 602 and second die 604 are in direct contact with second conductive structure 140 at first die backside 6022 and second die backside 6042 , respectively. An inductor 744 is also mounted on the second conductive structure 140 exposed from the molding layer 123 .

Similarly, the chip package 700 still retains the three-side heat dissipation design along the dotted line L2 in FIG. structure 129 ; the second side, from the first and second die backsides 6022 , 6042 via the second conductive structure 140 ; and the third side, heat dissipation from the side via the connection pad 201 exposed by the plastic encapsulation layer 123 .

Instead of passive components 420 (such as resistors 740, capacitors 742, and inductors 744) and/or heat sink 430, another die package 700 may be mounted on the second conductive structure 140 of the die package 700 to form a stack of power modules. Package (package-on-package, POP) configuration.

38a and 38b are schematic diagrams of another chip package 800 for a power module proposed according to an exemplary embodiment of the present disclosure. The chip package 800 is manufactured by the chip package method 20 in FIG. 2 . Accordingly, identical or similar features to those in Figures 2 to 25 and Figures 28 to 30 are indicated by the same reference numerals.

Similar to the chip package 700, the display chip package 800 is also fabricated by separating the panel assembly 710 as shown in the top view of FIG. 37a.

Fig. 38a shows a cross-sectional view of the die package 800 along the dashed line L1 in Fig. 37a. The chip package 800 has a structure similar to that of the chip package 700 shown in FIG. The backside 7202 emanates to the second conductive structure 140 .

However, a plurality of voids 502 as depicted in FIG. 28 may be formed in the plastic encapsulation layer 123 and extend to the first die by any suitable process, such as a laser patterning process, a mechanical patterning process, a drilling process, or a combination thereof. Grain back 6022. The void 502 is then filled with a conductive medium such as gold, silver, copper, tin, aluminum, etc., or combinations thereof, or other suitable conductive material, as shown in FIG. 29 .

Fig. 38b shows a cross-sectional view of the die package 800 along the dashed line L2 in Fig. 37a. Compared with the chip package 700 shown in FIG. 37c, the through plastic encapsulation layer 123 to the second die can be formed by any suitable process, such as a laser patterning process, a mechanical patterning process, a drilling process or a combination thereof. The backside 6042 has a plurality of voids 502 as described in FIG. 28 . The void 502 is then filled with a conductive medium such as gold, silver, copper, tin, aluminum, etc., or combinations thereof, or other suitable conductive material, as shown in FIG. 29 , thereby forming a conductively filled void 504 .

Instead of passive components 420 (such as resistors 740, capacitors 742, and inductors 744) and/or heat sink 430, another chip package 800 may be mounted on the second conductive structure 140 of the chip package 800 to form a package-on-package (package- on-package, POP) configuration. Alternatively, one die package 700 may be mounted on the second conductive structure 140 of the die package 800 to form a package-on-package (POP) configuration. Alternatively, the chip package 800 may be mounted on the second conductive structure 140 of a chip package 700 to form a package-on-package (POP) configuration.

Fig. 39a and Fig. 39b are schematic diagrams of another chip package 850 for a power module proposed according to an exemplary embodiment of the present disclosure. The chip package 850 is fabricated using the chip package method 20 in FIG. 27 . Accordingly, identical or similar features are denoted by the same reference numerals in FIGS. 2-25 and 32-34.

Similar to the chip package 700, the display chip package 850 is also fabricated by separating the panel assembly 710 as shown in the top view of FIG. 37a.

Fig. 39a shows a cross-sectional view of the die package 850 along the dashed line L1 in Fig. 37a. The chip package 850 has a similar structure to the chip package 800 shown in FIG. 38a. However, the space 730 in the chip package 800 is filled with the molding layer 123 ; and the void 502 is formed in the molding layer 123 and then filled with a conductive medium to form the conductive filled void 504 .

In contrast, as shown in FIG. 32 , the void 502 in the chip package 850 is formed in the plastic encapsulation layer 610 . The molding layer 610 can be formed by paste printing, injection molding, thermocompression molding, compression molding, transfer molding, liquid sealant molding, vacuum lamination, or other suitable molding methods. For example, the plastic encapsulation layer 610 is formed by film molding onto the die backsides 6022 , 6042 of the first and second dies 602 , 604 .

Instead of passive components 420 (such as resistors 740, capacitors 742, and inductors 744) and/or heat sink 430, another die package 850 may be mounted on the second conductive structure 140 of the die package 850 to form a package-on-package (package- on-package, POP) configuration. Alternatively, one die package 700, 800 may be mounted on the second conductive structure 140 of the die package 850 to form a stacked package configuration. Alternatively, the die package 850 may be mounted on the second conductive structure 140 of the die package 700, 800 to form a stacked package configuration.

In the case where the first conductive structure 129 and the second conductive structure 140 are made of metal or a metallic material (such as copper), compared to the die 113, the connection pad 201, the plastic encapsulation layer 123 and the above-mentioned other elements (such as the protective layer 107) , which has a relatively heavy weight. Preferably, the first conductive structure 129 and the second conductive structure 140 have substantially the same weight to balance the chip package 700 , 800 , 850 as a whole. In other words, if the first conductive structure 129 and the second conductive structure 140 are made of the same metal or metallic material, such as copper, they are of substantially equal quality.

FIG. 40 is a schematic diagram of a conventional chip package 900 for a power module. The conventional chip package 900 has the first semiconductor die 902 in a face-down configuration, that is, the first die active surface 9021 of the first semiconductor die 902 faces the lead frame (lead frame) 912 and uses solder Bumps (solder bumps) or solder balls (solder balls) are connected to the lead frame 912 by a conventional flip-chip process; and the second semiconductor is configured in a face-up configuration The die 904 , that is, the second die active surface 9041 of the second semiconductor die 904 faces away from the lead frame 912 and is connected to the lead frame 912 by wire bonding 910 . These two different configurations (i.e., the face-down configuration of the first semiconductor die 902 and the face-up configuration of the second semiconductor die 904) will make the manufacturing process of the conventional chip package 900 complicated and costly, and the semiconductor During the reconstruction process of transferring the dies 902 , 904 to the carrier 117 , the bonding accuracy of the first and second semiconductor dies is relatively low.

In contrast, both the first and second die 602, 604 in the chip packages 700, 800, 850 have a face-down configuration, with no solder bumps or balls directly The direct flip-chip process is connected to the first conductive structure 129 and further connected to the printed circuit board (PCB) or substrate (substrate) 410; , 850 is simpler, less costly and more accurate, especially the die transfer process (reconstruction process) of the carrier 117 to which the first and second die 602, 604 and the driving circuit 720 are bonded as shown in FIG. ) (die 113 represents the first and second die 602, 604 in FIG. 10).

As shown in FIG. 40 , a copper clip (Cu clip) 906 is mounted on the first semiconductor die 902 and the second semiconductor die 904 . However, the conventional chip package 900 requires a thick profile due to the bulky size of the copper clip 906 . Therefore, the weight of the copper clip 906 is heavy, which may cause cracking of the first and second semiconductor dies 902 , 904 . Meanwhile, wires 910 are commonly used in the conventional chip package 900 to connect the second semiconductor die 904 to the lead frame 912 . Leads 910 also require a larger space (vertically and laterally), making conventional die package 900 thicker and larger.

In contrast, the present disclosure directly connects the first and second die 602, 604 and the driving circuit 720 to a printed circuit board (PCB) using a direct flip-chip process that does not use solder bumps or solder balls. ) or on the substrate (substrate) 410 . Therefore, the chip packages 700 , 800 , and 850 have thinner and smaller profiles, and are more suitable for portable electronic devices (such as mobile phones, touch panels, and notebook computers) that are becoming more and more popular today.

As shown in FIG. 40 , a die attach material 916 is used to attach the first and second semiconductor die 902 , 904 to the lead frame 912 . Die attach material 916 , although possibly also conductive (eg, conductive paste or solder), has a higher electrical resistance than the conductive material (eg, copper) used for first conductive structure 129 . Therefore, the conventional die package 900 with die attach material 916 is not suitable for power modules that require low resistance and high current. Alternatively, the die attach material 916 can also use non-conductive materials (such as adhesives or film adhesives), but these non-conductive materials cannot effectively dissipate heat. Therefore, the conventional chip package 900 with non-conductive die attach material 916 is also not suitable for power modules that generate more heat due to high current.

In contrast, in the chip packages 700, 800, 850, the first and second dies 602, 604 and the driving circuit 720 are directly connected to the metal frame 200 (such as lead wires) via the first and second conductive structures 129, 140 The connection pads 201 of the frame) do not require the die attach material 916 of the conventional die package 900 . The first and second conductive structures 129 , 140 may be made of a conductive material with high conductivity, such as copper, which allows a high flux of current to flow in the power module. At the same time, due to the lower resistance of the first and second conductive structures 129, 140, less heat will be generated.

In particular, in the conventional chip package 900, in order to allow current to flow vertically through the first and second semiconductor die 902, 904, a die back metal layer must be added on the first and second die backsides 9022, 9042. (die back metal layer) 908 (eg copper). For example, a die back metal layer 908 is applied to the first die back side 9022 for vertical conduction from the first die active side 9021 to the first die back side 9022 . But at the same time, the grinding process shown in FIG. 12 cannot be used for the die back metal layer 908; thus the first and second semiconductor die 902, 904 cannot be thinned by the grinding process to reduce the resistance, which will reduce the use of traditional chip packaging. 900 power module performance.

In contrast, the chip packages 700, 800, 850 do not have the die back metal layer 908 because the vertical conduction is through the connection pads 201 of the metal frame 200 and the second conduction on the die back 6022, 6042 and drive back 7202. Structure 140 is conductive. Therefore, the grinding process shown in FIG. 12 can be used to thin the first and second dies 602 , 604 and the driving circuit 720 to enhance the electrical performance of the chip package 700 , 800 , 850 when used as a power module.

Furthermore, conventional die package 900 uses discrete metal components (eg, copper clip 906 and lead frame 912 ) that are fabricated separately prior to packaging. Therefore, expensive metals such as silver or nickel-palladium-gold (NiPdAu) also need to be used in the packaging process to connect any two discrete metal components. For example, a spot plating layer 918 is applied between the copper clip 906 and the lead frame 912 to mount the copper clip 906 on the lead frame 912 . For another example, a spot plating layer 918 (not shown) is also applied between the copper clip 906 and the die back metal layer 908 to mount the copper clip 906 on the first die backside 9022 of the first semiconductor die 902 .

In contrast, chip packages 700, 800, 850 do not use discrete metal components. Instead, the metal elements of chip packages 700, 800, 850 (eg, conductive filled via 124, first and second conductive structures 129, 140) are deposited during packaging by a suitable metal deposition process (eg, PVD, CVD, sputtering , electrolytic plating, electroless plating process) and formed. For example, the first panel-level conductive trace 125 is directly formed on the conductive filled via 124 and the connection pad front surface 2011 ; then, the first panel-level conductive post 127 is directly formed on the first panel-level conductive line 125 . Therefore, all conductive elements in the chip packages 700, 800, 850 are directly connected, and the process of forming spot plating 918 is not required during packaging. Therefore, the above-mentioned direct connection in the chip package 700, 800, 850 improves the reliability and mechanical stability of the connection between the conductive parts, which further improves its performance in the moisture senility level test.

Furthermore, chip packages 700 , 800 , 850 do not require solder bumps or balls 922 as in conventional chip package 900 to connect to printed circuit board (PCB) or substrate 410 , passive components or heat sinks. For example, the first and second die 602 , 604 and the driving circuit 720 are directly connected to the printed circuit board (PCB) or substrate 410 through the first conductive structure 129 without using solder bumps or solder balls. As another example, the first and second die 602, 604 and the drive circuit 720 are directly connected to the passive element 420 (such as the resistor 740, the capacitor 742 and the inductor 744) or the heat sink 430 through the second conductive structure, and neither Use solder balls or solder balls. The direct connection to the chip package 700, 800, 850 has several benefits compared to the conventional chip package 900, especially when used as a power module.

Solder is relatively soft in nature; therefore, solder bumps or balls 922 are easily deformed when mounting components of conventional chip package 900 , including semiconductor die 902 , 904 , copper clip 906 , lead frame 912 and plastic encapsulation layer. In addition, the melting temperature of solder is low; when a conventional chip package (especially as a power module) generates a lot of heat, the solder bump or solder ball 922 may melt and move, which may affect or even destroy the electrical circuit in the conventional chip package 900. connect.

Solder also has high resistance and impedance for a large electric flux current, and when the electric flux of the power module is large, electromigration may also occur. In contrast, the directly connected conductive material (such as copper) in the chip packages 700, 800, 850 has much lower resistance and impedance, and is not easily affected by electromigration, and is suitable for use as a power module.

In addition, the conventional chip package 900 has long conductive paths along the copper clips 906 and wire bonds 910 , which may cause serious parasitic effects and conduction losses. In contrast, the direct connection in the chip package 700, 800, 850 has a shorter conductive path through the first and second conductive structures 129, 140 and the connection pad 201 of the metal frame 200, thereby reducing parasitic effect and conduction loss.

In addition, a seed layer (not shown) may also be formed before forming the direct connection in the die package 700 , 800 , 850 to further enhance the direct connection. The seed layer may be formed by sputtering Ti/Cu, sputtering SUS/Cu/SUS, electroless copper plating, or a combination thereof.

Referring to FIG. 40 , the conventional chip package 900 mainly dissipates heat from the plastic encapsulation layer that fully encapsulates the first and second semiconductor die 902 , 904 and the copper clip 906 . Therefore, the heat generated by the first and second semiconductor die 902, 904 and the heat generated by the electrical flux flowing in the conventional chip package 900 may not be efficiently transferred to the surrounding environment. Therefore, the conventional chip package 900 is not suitable for power modules.

In contrast, chip packages 700, 800, 850 have the above-mentioned three-side heat dissipation design, which is conducive to efficient cooling function. That is, the first side, from the first and second die active surfaces 6021, 6041 and the driving active surface 7201 of the driving circuit 720, via the first conductive structure 129; the second side, from the first and second wafer back surfaces 6022, 6042 and the driving back surface 7202 of the driving circuit 720 through the second conductive structure 140 ; and the third side through the connection pad 201 to dissipate heat from the side surface. In addition, the heat sink 430 can be installed on the second conductive structure 140 to accelerate the heat dissipation of the chip package 700 , 800 , 850 .

The purpose of the specific embodiments described above is to further describe the technical solutions and technical effects of the present disclosure in detail, but those skilled in the art will understand that the specific embodiments described above are not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the inventive idea of the present disclosure shall be included in the protection scope of the present disclosure.

10: Chip packaging method 100: chip 1001: wafer active surface 1002: wafer back 103: Electrical connection point 105: insulation layer 106: Wafer Conductive Traces 107: protective layer 109: protective layer opening 109a: the lower surface of the protective layer opening 109b: the upper surface of the protective layer opening 109c: protective layer opening side wall 111: chip conductive bump 113: grain 1131: grain active surface 1132: the back of the grain 117: (first) carrier board 1171: The front of the carrier board 1172: The back of the carrier board 118: (second) carrier board 121: Adhesive layer 122: Adhesive layer 123: Plastic layer 1231: Front side of the plastic layer 1232: The back of the plastic layer 124: Conductive filled vias 125: First panel level conductive trace 127: The first panel-level conductive column 129: The first conductive structure 130: wafer conductive layer 131: surface treatment layer 140: second conductive structure 142:Second panel level conductive trace 144: Second panel-level conductive column 146: the first dielectric layer 150: panel assembly 152:Panel assembly 154:Panel assembly 160: dry film 162: Patterned dry film 163: dry film opening 164: dry film 166: Patterned dry film 167: dry film opening 170: second dielectric layer 1702: The back of the second dielectric layer 20: Chip packaging method 200: metal frame 201: connection pad 2011: Connection pad front 2012: Back of connection pad 202: Vacancy 203: connecting rod 300: Temporary support plate 301: Adhesive layer 400: package chip 410: Printed Circuit Board (PCB) or Substrate 412: Solder bumps or solder balls 420: Passive components 430: Radiator 440: Grounding Labels 500: package chip 502: Gap 504: Conductive fill void 550: package chip 600: package chip 602: The first grain 6021: The active surface of the first grain 6022: The first die backside 604: Second grain 6041: second grain active surface 6042: Second Die Back 610: Plastic layer 700: chip packaging 710: panel assembly 720: drive circuit 7201: drive active surface 7202: Drive back 730: space 740: Resistor 742: Capacitor 744: Inductor 800: chip packaging 850: chip package 900: Traditional chip packaging 902: The first grain 9021: The active surface of the first grain 9022: The back side of the first die 904: Second grain 9041: second grain active surface 9042: Second Die Back 906: copper clip 908: Die back metal layer 910: Leads (bonding) 912: Lead frame 916: Die Attach Materials 918: point coating 922: Solder bumps or solder balls A: Schematic diagram of grain AS: additional steps B: Schematic diagram of grain C: Schematic diagram of grain L1: dotted line L2: dotted line S101~S111: steps S201~S211: steps SL: cutting line

[ FIG. 1 ] is a flowchart of a chip packaging method proposed according to an exemplary embodiment of the present disclosure. [ FIG. 2 ] to [ FIG. 25 ] are schematic flowcharts of a panel assembly manufactured according to the chip packaging method in FIG. 1 . [ FIG. 26 ] is a schematic diagram of packaged wafers formed after dicing the panel assembly manufactured according to FIGS. 2 to 25 . [ FIG. 27 ] is a flowchart of another chip packaging method proposed according to an exemplary embodiment of the present disclosure. [ FIG. 28 ] to [ FIG. 30 ] are additional flowcharts of manufacturing another panel assembly according to the chip packaging method in FIG. 27 . [ FIG. 31 ] is a schematic diagram of packaged wafers formed after dicing the panel assembly manufactured according to FIGS. 28 to 30 . [ FIG. 32 ] to [ FIG. 34 ] are schematic flowcharts of modifications of another panel assembly in FIGS. 28 to 30 . [ FIG. 35 ] is a schematic view of package wafers formed after dicing according to the modification of the panel assembly manufactured in FIGS. 32 to 34 . [FIG. 36a, FIG. 36b] are schematic diagrams of a packaged chip with two chips manufactured according to the chip packaged method in FIG. 1 . [FIG. 37a, FIG. 37b, FIG. 37c] are schematic diagrams of a chip package for a power module proposed according to an exemplary embodiment of the present disclosure. [FIG. 38a, FIG. 38b] are schematic diagrams of another chip package for a power module proposed according to an exemplary embodiment of the present disclosure. [FIG. 39a, FIG. 39b] are schematic diagrams of another chip package for a power module proposed according to an exemplary embodiment of the present disclosure. [ Fig. 40 ] is a schematic diagram of a conventional chip package used in a power module.

200: metal frame

201: connection pad

202: Vacancy

602: The first grain

604: Second grain

710: panel assembly

720: drive circuit

L1: dotted line

L2: dotted line

SL: cutting line

Claims (20)

A chip package for a power module, comprising: At least one crystal grain has an opposite crystal grain active surface and a crystal grain back surface, wherein the at least one crystal grain has a relatively thin thickness for reducing resistance when used as the power module; a driving circuit for controlling the at least one die, the driving circuit having a driving active surface and a driving back surface opposite; A protective layer formed on the grain active surface and the driving active surface, wherein the protective layer has a plurality of protective layer openings for exposing the crystal grain active surface and the driving active surface from the protective layer; a metal unit comprising at least one metal feature, wherein the at least one metal feature has at least one connection pad, the at least one connection pad has a connection pad front and a connection pad back; and a plastic encapsulation layer for encapsulating the at least one die, the driving circuit, the protection layer and the metal unit; Wherein the chip package is connected with an external circuit through the at least one metal feature. The chip package as claimed in claim 1, wherein the at least one die includes a first die and a second die, and the first die and the second die respectively have a first die active surface and a A second crystal grain active surface, wherein the first crystal grain, the second crystal grain and the drive circuit are surrounded by the metal unit, the first crystal grain active surface, the second crystal grain active surface and the drive active surface substantially flush. The chip package as described in claim 1, further comprising: A first conductive structure formed on the at least one metal feature of the metal unit, the protection layer and the plastic encapsulation layer, wherein the first conductive structure is connected to the grain active surface and the driving active surface for the At least one die and the driving circuit are connected to the metal unit. The chip package as claimed in claim 3, wherein the first conductive structure has a plurality of conductive filled vias connected to the active surface of the die and the active surface of the drive, and the at least one metal feature of the metal unit, the A panel-level conductive layer is formed on the protection layer and the plastic encapsulation layer, wherein the conductive filling via holes are formed by filling the openings of the protection layer with a conductive material. The chip package as described in claim 3, further comprising: A second conductive structure formed on the at least one metal feature of the metal unit and the plastic encapsulation layer, the second conductive structure and the first conductive structure are on an opposite side of the at least one die, wherein the second conductive structure The structure is connected to the first conductive structure through the at least one metal feature of the metal unit. The chip package as claimed in claim 5, wherein the first conductive structure and the second conductive structure have substantially the same weight for balancing the chip package from the active surface of the die and the back surface of the die. The chip package as claimed in claim 5, wherein the second conductive structure is in direct contact with the die backside of the at least one die for electrically back-grounding the chip package. The chip package as described in Claim 5, further comprising: At least one void formed in the plastic encapsulation layer is used to expose the backside of the crystal grain from the plastic encapsulation layer, wherein a conductive medium is filled in the at least one void to form at least one conductive filled void, which is used to communicate with the second Conductive structures are connected. The chip package as described in Claim 5, further comprising: an additional molding layer formed on the backside of the die of the at least one die, the additional molding layer being encapsulated by the molding layer; and At least one void in the additional plastic encapsulation layer is used to expose the backside of the die from the plastic encapsulation layer, wherein a conductive medium is filled in the at least one void to form at least one conductive filled void for use with the second Conductive structures are connected. The chip package as described in Claim 5, further comprising: a first dielectric layer for encapsulating the first conductive structure, wherein the first conductive structure is exposed from the first dielectric layer for connecting with the external circuit; and A second dielectric layer for encapsulating the second conductive structure, wherein the second conductive structure is exposed from the second dielectric layer for connecting with an external component. A wafer structure comprising: at least one grain having oppositely a grain active face and a die back face; A protective layer, formed on the active surface of the crystal grain, has a plurality of protective layer openings for exposing the active surface of the crystal grain from the protective layer; A metal unit comprising at least one metal feature, wherein the at least one metal feature has at least one connection pad, the at least one connection pad has a connection pad front and a connection pad back; a plastic encapsulation layer for encapsulating the die, the protection layer and the metal unit; and A first conductive structure formed on the at least one metal feature of the metal unit, the protective layer and the plastic encapsulation layer, wherein the first conductive structure is connected to the active surface of the die for connecting the at least one die to the metal unit; Wherein the chip structure is connected with an external circuit through the at least one metal feature. The chip structure as claimed in claim 11, wherein the external circuit includes a printed circuit board, and the first conductive structure is in direct contact with the printed circuit board for directly connecting the at least one die to the printed circuit board. The chip structure as described in claim 12, further comprising: A second conductive structure formed on the at least one metal feature of the metal unit and the plastic encapsulation layer, the second conductive structure and the first conductive structure are on an opposite side of the at least one die, wherein the second conductive structure The structure is connected to the at least one crystal grain through the first conductive structure and the at least one metal feature of the metal unit, and is used for electrically back-grounding the chip structure. The wafer structure as claimed in claim 13, wherein the second conductive structure is in direct contact with a die backside of the at least one die for conducting heat from the die backside out of the wafer structure. The chip structure of claim 14, wherein the first conductive structure and the second conductive structure have substantially the same weight for balancing the chip package from the active side of the die and the back side of the die. A method for manufacturing a chip package for a power module, comprising: providing at least one die with an opposite die active face and a die back face, wherein the thickness between the die active face and the die back face of the at least one die is relatively thin for reducing the power supply A resistance of the module; providing a drive circuit for controlling the at least one die, the drive circuit having oppositely a drive active surface and a drive back surface; A protective layer is formed on the crystal grain active surface and the driving active surface, and the protective layer has a plurality of protective layer openings for exposing the crystal grain active surface and the driving active surface from the protective layer; placing a metal unit around the at least one die and the drive circuit, wherein the metal unit has at least one metal feature, the at least one metal feature has at least one connection pad, and the at least one connection pad has a connection pad front surface and an opposite connection pad surface and - the back of the connection pad; forming a plastic encapsulation layer for encapsulating the at least one die, the driving circuit, the protection layer and the metal unit; and The chip package is connected to an external circuit through the at least one metal feature of the metal unit. The manufacturing method as described in Claim 16, further comprising: A first conductive structure is formed so as to be in direct contact with the front surface of the connection pad of the at least one connection pad, the second surface of the protective layer of the protective layer, and the front surface of a plastic sealing layer of the plastic sealing layer, wherein the front surface of the connecting pad, the protective layer The second side of the layer is substantially flush with the front side of the plastic sealing layer. The manufacturing method as described in claim 17, further comprising: A second conductive structure is formed to be in direct contact with the back of the connection pad of the at least one connection pad and the back of the molding layer of the molding layer, wherein the back of the molding layer is opposite to the front of the molding layer. The manufacturing method as described in Claim 18, further comprising: forming at least one void in the encapsulation layer for exposing the die backside of the at least one die therefrom; and A conductive medium is filled in the at least one void to form at least one conductive filled void, which is connected to the second conductive structure. The manufacturing method as described in Claim 16, further comprising: forming a first dielectric layer encapsulating the first conductive structure, wherein the first conductive structure is exposed from the first dielectric layer for connection to the external circuit; and A second dielectric layer encapsulating the second conductive structure is formed, wherein the second conductive structure is exposed from the second dielectric layer for connecting with an external component.

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