TWI756076B - Chip packaging structure - Google Patents

Abstract

A chip packaging method and a chip packaging structure are disclosed. The chip packaging method includes: forming a wafer conductive layer on an wafer active surface of a wafer; forming a protective layer having material properties on the wafer conductive layer; sawing the wafer into several dies and mounting the several dies on a carrier; forming a plastic encapsulating layer which has material properties and encapsulates the die; peeling of the carrier; forming a panel-level conductive layer and a dielectric layer; the packaging method can reduce or eliminate the warpage in the panel packaging process, reduce the precision requirement on the dies on the panel, reduce the difficulty of the panel packaging process, and make the packaged chip structure have a long lifetime, especially suitable for large panel-level package and large electric flux, thin chip package.

Description

Chip package structure

The present disclosure relates to the field of semiconductor technology, and in particular, to a chip packaging method and a packaging structure.

Panel-level package is to cut the wafer to separate many dies, arrange and paste the dies on the carrier board, and package many dies simultaneously in the same process flow. As a technology emerging in recent years, panel-level packaging has received extensive attention. Compared with traditional wafer-level packaging, panel-level packaging has the advantages of high production efficiency, low production cost and suitable for mass production.

However, there are many technical barriers in panel packaging, such as the problem of warpage of the panel and the accuracy of die alignment on the panel.

Especially in the current trend of small and lightweight electronic equipment, small and thin chips are increasingly favored by the market. However, the packaging process of using large panel packaging technology to package small and thin chips cannot be underestimated.

The present disclosure aims to provide a semiconductor chip packaging method and a chip packaging structure, the packaging method can reduce or eliminate warpage during the panel packaging process, reduce the precision requirements of the die on the panel, reduce the difficulty of the panel packaging process, and The packaged chip structure has a durable service cycle, and is especially suitable for large-scale panel-level packaging and packaging of large electric flux and thin chips.

The present disclosure provides a chip package structure, comprising: at least one die, the die includes an active surface of the die and a back surface of the die; a conductive structure is formed on one side of the active surface of the die; and a protective layer is formed on the side of the active surface of the die one side of the active surface of the die; a plastic encapsulation layer, the plastic encapsulation layer is used to encapsulate the die; and a dielectric layer.

In one embodiment, the conductive structure includes a wafer conductive layer, a conductively filled via, and a panel-level conductive layer; the conductively filled via is formed in the protective layer.

In another embodiment, the conductively filled via has a lower surface of the conductively filled via and an upper surface of the conductively filled via, and the area of the lower surface of the conductively filled via is smaller than that of the upper surface of the conductively filled via.

In yet another embodiment, the active surface of the die includes an electrical connection point and an insulating layer; at least a part of the wafer conductive layer and at least a part of the electrical connection point are electrically connected for connecting at least a part of the electrical connection point Lead out from the active surface of the die; the lower surface of the conductively filled through hole is electrically connected to the wafer conductive layer; the upper surface of the conductively filled through hole is electrically connected to the panel-level conductive layer.

In one embodiment, at least a part of the conductive layer of the wafer leads out at least a part of the electrical connection points individually.

In another embodiment, at least a portion of the wafer conductive layer interconnects and leads out at least a portion of the plurality of electrical connection points to each other.

In yet another embodiment, a contact area of the wafer conductive layer with a single contact area of the electrical connection point is smaller than a contact area of the wafer conductive layer with a single contact area of the conductive filled via.

In one embodiment, the panel-level conductive layer includes conductive traces and/or conductive bumps; the conductive bumps are formed on pads or connection points of the conductive traces; the dielectric layer includes Covering the panel-level conductive layer; the panel-level conductive layer is one or more layers.

In one embodiment, at least a portion of the conductive traces closest to the active surface of the die are formed on the front side of the molding layer and extend to the edge of the package body.

In another embodiment, the backside of the die is exposed from the molding layer.

In yet another embodiment, the surface of the dielectric layer has grooves at positions corresponding to the conductive layers.

In one embodiment, the at least one die is a plurality of die, and the plurality of die is electrically connected according to product design.

In another embodiment, the plurality of dies are dies with different functions to form a multi-chip module.

In another embodiment, the material of the protective layer is an organic/inorganic composite material.

In one embodiment, the Young's modulus of the protective layer is any one of the following ranges or values: 1000-20000 MPa, 1000-10000 MPa, 4000-8000 MPa, 1000-7000 MPa, 4000-7000 MPa, 5500 MPa.

In yet another embodiment, the thickness of the protective layer is any one of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, and 50 μm.

In one embodiment, the thermal expansion coefficient of the protective layer is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In another embodiment, the thermal expansion coefficient of the plastic sealing layer is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In yet another embodiment, the protective layer and the plastic sealing layer have the same or similar thermal expansion coefficients.

In one embodiment, the protective layer includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm.

In one embodiment, the diameter of the inorganic filler particles is 1-2 μm.

The present disclosure provides a chip packaging method, including: providing a wafer, the wafer has a wafer active surface and a wafer back surface, the wafer active surface includes electrical connection points and an insulating layer; on the wafer active surface of the wafer forming a wafer conductive layer; forming a protective layer on the wafer conductive layer; cutting the wafer to form die and attaching it to a carrier; forming a plastic encapsulating layer for encapsulating the die; peeling off the carrier; forming a panel level Conductive and dielectric layers.

In one embodiment, at least a part of the wafer conductive layers in the formed wafer conductive layers lead out at least a part of the electrical connection points individually and/or at least a part of the wafer conductive layers lead out at least a part of the electrical connection points. The electrical connection points are interconnected and led out.

In one embodiment, the method further includes the step of forming a protective layer opening on the protective layer, the area of the lower surface of the protective layer opening is smaller than the area of the upper surface of the protective layer opening, and the protective layer opening is opened at the surface of the wafer. at the corresponding position of the conductive layer.

In one embodiment, the protective layer opening is formed by laser patterning.

In one embodiment, the method further includes the step of forming a conductively filled via in the opening of the protective layer, one end of the conductively filled via is connected to the wafer conductive layer, and one end of the conductively filled via is connected to the wafer conductive layer. The panel-level conductive layer is connected; the contact area of the wafer conductive layer with the single contact area of the electrical connection point is smaller than the contact area of the wafer conductive layer with the single contact area of the conductive filled via.

In one embodiment, the method further includes the step of thinning the backside of the plastic encapsulation layer to expose the backside of the die.

In one embodiment, the method further includes the step of forming grooves at positions corresponding to the panel-level conductive layer on the dielectric layer by metal etching.

In one embodiment, the method further includes the step of subjecting the wafer and/or the surface of the protective layer to a plasma surface treatment and/or a chemically accelerated modifier treatment.

In one embodiment, the Young's modulus of the protective layer is any one of the following ranges or values: 1000-20000 MPa, 1000-10000 MPa, 4000-8000 MPa, 1000-7000 MPa, 4000-7000 MPa, 5500 MPa.

In another embodiment, the thickness of the protective layer is any one of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, 50 μm.

In yet another embodiment, the thermal expansion coefficient of the protective layer is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K, and/or the The thermal expansion coefficient of the plastic sealing layer 123 is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, and 10 ppm/K.

In one embodiment, the material of the protective layer is an organic/inorganic composite material.

In one embodiment, the protective layer and the plastic sealing layer have the same or similar thermal expansion coefficients.

In one embodiment, the protective layer includes inorganic filler particles.

In one embodiment, the diameter of the inorganic filler particles is less than 3 μm or the diameter of the inorganic filler particles is 1 to 2 μm.

In order to make the technical solutions of the present disclosure clearer and the technical effects clearer, the preferred embodiments of the present disclosure will be described and explained in detail below with reference to the accompanying drawings. public restrictions.

1 to 14 are flowcharts of a chip packaging method proposed according to an exemplary embodiment of the present disclosure.

As shown in FIG. 1, at least one wafer 100 is provided, the wafer 100 has a wafer active surface 1001 and a wafer backside 1002, the wafer 100 includes a plurality of dies 113, wherein the active surface of each die constitutes a The active surface 1001 of the wafer, the active surface of each die in the wafer 100 is formed by a series of processes such as doping, deposition, and etching to form a series of active components and passive components, and the active components include diodes, triodes, etc. The passive components include voltages, capacitors, resistors, inductors, etc. These active components and passive components are connected by connecting wires to form functional circuits, thereby realizing various functions of the chip. The wafer active surface 1001 further includes an electrical connection point 103 for drawing out the functional circuit and an insulating layer 105 for protecting the electrical connection point 103 .

As shown in FIG. 2a and FIG. 2b, a wafer conductive layer 106 is formed on the active surface 1001 of the wafer.

The wafer conductive layer 106 can be made of materials such as copper, gold, silver, tin, aluminum or a combination thereof, or other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, and electroless plating processes, or other suitable metal deposition process.

At least a part of the conductive layer 106 of the wafer is electrically connected to at least a part of the electrical connection points 103 on the active surface 1001 of the wafer.

Optionally, as shown in FIG. 2 a , the wafer conductive layer 106 interconnects and leads out a plurality of the electrical connection points 103 in at least a part of the wafer active surface 1001 .

The formation of the wafer conductive layer 106 can reduce the number of protective layer openings 109 formed in the subsequent process. The wafer conductive layer 106 is used to first interconnect the plurality of electrical connection points 103 according to the circuit design, eliminating the need for each electrical connection point. 103 to form protective layer openings 109 .

Optionally, as shown in FIG. 2b, at least a part of the electrical connection points 103 on the active surface 1001 of the wafer are independently drawn out by the conductive layer 106 of the wafer.

The formation of the wafer conductive layer 106 helps to reduce the difficulty of the subsequent formation of the protective layer opening 109. Due to the existence of the wafer conductive layer 106, the lower surface 109a of the protective layer opening can have a larger area. Correspondingly, it can be Having the protective layer openings 109 with a larger area, especially on wafers 100 with smaller exposed electrical connection points 103, enables the formation of the protective layer openings.

Although it is not shown in the figure, it can be understood that the conductive layer 106 of the wafer independently leads out a part of the electrical connection points 103 on the active surface 1001 of the wafer and connects the electrical connection points 103 on the active surface 1001 of the wafer. Another part of the electrical connection points 103 are interconnected and led out.

As shown in FIG. 3 , a protective layer 107 is applied on the active surface 1001 of the wafer and the conductive layer 106 of the wafer.

The protective layer 107 adopts an insulating material, such as BCB (benzocyclobutene), PI (polyimide), PBO (polybenzoxazole), polymer matrix dielectric film, organic polymer film, or Other materials with similar insulating and structural properties are formed by lamination, coating, printing, etc.

In one embodiment, the protective layer is applied by lamination.

Optionally, before the step of applying the protective layer 107, physical and/or chemical treatment is performed on the active surface 1001 of the wafer and/or the surface of the protective layer 107 applied on the wafer 100 to The bonding between the protective layer 107 and the wafer 100 is made tighter. Optionally, the treatment method is plasma surface treatment to roughen the surface to increase the bonding area and/or chemical promotion modifier treatment, and a promotion modification group is introduced between the wafer 100 and the protective layer 107, For example, surface modifiers with both organic affinity and affinity inorganic groups increase the adhesion between organic/inorganic interface layers.

The protective layer 107 can be used to protect the active surface 1131 of the die. In the subsequent molding process, due to the molding pressure, the molding material flowing under heating conditions tends to penetrate into the gap between the die 113 and the carrier plate 117, especially when the wafer conductive layer 106 is formed on the die active surface 1131, so that the The gap between the die and the carrier becomes larger, and the plastic sealing material is easy to infiltrate during plastic sealing. When the die active surface 1131 has a protective layer, the protective layer 107 can protect the die active surface 1131 from infiltrating the molding material so as to protect the die active surface 1131 from damage.

The existence of the protective layer 107 can also make the adhesion between the die 113 and the adhesive layer 121 stronger, so that during the plastic sealing process, the plastic sealing pressure is not easy to cause the die 113 to be stuck on the carrier board. A position shift occurs on 117.

In a preferred embodiment, the Young's modulus of the protective layer 107 is in the range of 1000-20000 MPa, more preferably the Young's modulus of the protective layer 107 is in the range of 1000-10000 MPa; further preferred The Young's modulus of the protective layer 107 is 1000-7000, 4000-7000 or 4000-8000 MPa; in a preferred embodiment, the Young's modulus of the protective layer 107 is 5500 MPa.

In a preferred embodiment, the thickness of the protective layer 107 is in the range of 15-50 μm; more preferably, the thickness of the protective layer is in the range of 20-50 μm; in a preferred embodiment, the protective layer The thickness of the protective layer 107 is 35 μm; in another preferred embodiment, the thickness of the protective layer 107 is 45 μm; in another preferred embodiment, the thickness of the protective layer 107 is 50 μm.

When the Young's modulus of the protective layer 107 ranges from 1000 to 20000 MPa, on the one hand, the protective layer 107 is soft and has good flexibility and elasticity; on the other hand, the protective layer can provide sufficient support Acting force enables the protective layer 107 to have sufficient support for the conductive layer formed on its surface. Meanwhile, when the thickness of the protective layer 107 is 15-50 μm, it is ensured that the protective layer 107 can provide sufficient buffer and support.

Especially in some types of chips, it is necessary to use thin die for packaging, and the conductive layer needs to reach a certain thickness to form a large electric flux. In this case, the thickness of the protective layer 107 is selected to be in the range of 15-50 μm , the value of the Young's modulus of the protective layer 107 ranges from 1000 to 10000 MPa. The soft and flexible protective layer 107 can form a buffer layer between the crystal grains 113 and the conductive layer formed on the surface of the protective layer, so that during the use of the wafer, the conductive layer on the surface of the protective layer is not damaged. The die 113 will be compressed excessively to prevent the die 113 from being broken by the pressure of the thick conductive layer. At the same time, the protective layer 107 has sufficient material strength, and the protective layer 107 can provide sufficient support for the thick conductive layer.

When the Young's modulus of the protective layer 107 is 1000-20000 MPa, especially when the Young's modulus of the protective layer 107 is 4000-8000 MPa, and the thickness of the protective layer 107 is 20-50 μm, due to the The material properties of the protective layer 107 enable the protective layer 107 to effectively protect the die against the thimble pressure of the die transfer equipment in the subsequent die transfer process;

The die transfer process is a process of rearranging and adhering the cut and separated die 113 to the carrier plate 117 (reconstruction process). The die transfer process requires the use of a bonder machine, which includes an ejector pin. , the die 113 on the wafer 100 is lifted up by an ejector pin, and the lifted die 113 is sucked up by a bonder head, transferred and bonded to the carrier board 117 .

During the process of ejecting the crystal grains 113 by the ejector pins, the crystal grains 113, especially the thin-type crystal grains 113, are brittle and are easily broken by the ejection pressure of the ejector pins. The protective layer 100 with material characteristics can protect the brittle crystal grains in this process. The grains 113 can maintain the integrity of the crystal grains 113 even under a relatively large jacking pressure.

In a preferred embodiment, the protective layer 107 is an organic/inorganic composite material layer including filler particles. Further, the filler particles are inorganic oxide particles; further, the filler particles are SiO ₂ particles; in one embodiment, the filler particles in the protective layer 107 are two or more different types of inorganic oxide particles, such as _SiO2 mixed with _TiO2 particles. Preferably, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO ₂ particles, such as SiO ₂ mixed TiO ₂ particles, are spherical or spherical-like. In a preferred embodiment, the filling amount of filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO ₂ particles, such as SiO ₂ mixed TiO ₂ particles, is more than 50%.

The organic material has the advantages of easy operation and application. The die 113 to be encapsulated is made of an inorganic material, such as silicon material. When the protective layer 107 is made of an organic material alone, due to the difference between the material properties of the organic material and the material properties of the inorganic material. The difference will make the packaging process difficult and affect the packaging effect. The use of organic/inorganic composite materials in which inorganic particles are added to organic materials can modify the material properties of organic materials, so that the materials have both the characteristics of organic materials and inorganic materials.

In a preferred embodiment, when (T<Tg), the thermal expansion coefficient of the protective layer 107 ranges from 3 to 10 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 5 ppm/K; in a preferred embodiment; the thermal expansion coefficient of the protective layer 107 is 7 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 10 ppm/K.

In the ensuing molding process, the die 113 to which the protective layer 107 is applied will expand and contract correspondingly during the heating and cooling process of the molding process. When the thermal expansion coefficient of the protective layer 107 is in the range of 3-10 ppm/K , the degree of expansion and contraction between the protective layer 107 and the die 113 remains relatively consistent, the connection interface between the protective layer 107 and the die 113 is not easy to generate interface stress, and it is not easy to destroy the combination between the protective layer 107 and the die 113. The wafer structure is more stable.

In the process of using the packaged chip, it is often necessary to undergo cold and thermal cycles. The thermal expansion coefficient of the protective layer 107 ranges from 3 to 10 ppm/K and the die 113 has the same or similar thermal expansion coefficient. During the cold and thermal cycle, the protective layer 107 Maintaining a relatively consistent expansion and contraction degree with the die 113 , avoiding the accumulation of interface fatigue at the interface between the protective layer 107 and the die 113 , making the packaged chip durable and prolonging the service life of the chip.

On the other hand, if the thermal expansion coefficient of the protective layer is too small, it is necessary to fill the composite material of the protective layer 107 with too many filler particles, which will further reduce the thermal expansion coefficient and also increase the Young's modulus of the material, so that the protective layer material is The flexibility is reduced, the stiffness is too strong, and the buffering effect of the protective layer 107 is not good. It is optimal to limit the thermal expansion coefficient of the protective layer to 5~10ppm/k.

In a preferred embodiment, the diameter of the filler particles in the protective layer 107 , such as inorganic oxide particles, such as SiO ₂ particles is less than 3 μm, preferably the filler particles in the protective layer 107 , such as inorganic oxide particles , for example, the diameter of SiO ₂ particles is between 1 and 2 μm.

Controlling the diameter of the filler particles to be less than 3 μm is conducive to forming a protective layer opening with smooth sidewalls on the protective layer 107 in the laser patterning manufacturing process, so that the material can be fully filled in the conductive material filling process to avoid large The sidewalls 109c of the protective layer opening with uneven size cannot be filled with the conductive material on the backside of the sidewalls shielded by the protrusions, which affects the conductivity of the conductive filled vias 111 .

At the same time, the filling size of 1-2 μm will expose the filler with small particle size during the laser patterning process, so that the sidewall 109c of the opening of the protective layer has a certain roughness. The contact surface is larger and the contact is tighter, and the conductive filled through hole 111 with good conductivity is formed.

The diameter size of the above-mentioned filler is the average value of the particle diameter.

In a preferred embodiment, the tensile strength of the protective layer 107 ranges from 20 to 50 MPa; in a preferred embodiment, the tensile strength of the protective layer 107 is 37 MPa.

Optionally, after the process of applying the protective layer 107 on the active surface 1001 of the wafer, the back surface 1002 of the wafer is ground and thinned to a desired thickness.

Modern electronic devices are small and lightweight, and wafers tend to be thinned. In this step, the wafer 100 sometimes needs to be thinned to a very thin thickness. However, the processing and transfer of thin wafers 100 are difficult, and grinding The thinning process is difficult, and it is often difficult to thin the wafer 100 to a desired thickness. When the protective layer 107 is provided on the surface of the wafer 100 , the protective layer 107 with material properties will support the wafer 100 , thereby reducing the difficulty of processing, transferring and thinning the wafer 100 .

As shown in FIG. 4 a and FIG. 4 b , protective layer openings 109 are formed on the surface of the protective layer 107 .

At least a part of the protective layer opening 109 is located corresponding to the wafer conductive layer 106, and the wafer conductive layer 106 is exposed through the protective layer opening 109; the protective layer opening 109 has a protective layer opening lower surface 109a and a protective layer opening upper surface 109b.

In a preferred embodiment, the shape of the protective layer opening 109 is such that the area of the upper surface 109b of the protective layer opening is larger than the area of the lower surface 109a of the protective layer opening. It is easy to perform, and the conductive material is formed uniformly and continuously on the sidewalls during the filling process.

Optionally, each wafer conductive layer 106 in at least a part of the wafer conductive layers 106 corresponds to one or more protective layer openings 109 .

Optionally, the contact area α1 of the single contact area between the wafer conductive layer 106 and the electrical connection point 103 is smaller than the contact area β1 between the wafer conductive layer 106 and the single contact area of the protective layer opening 109 .

When the type of the wafer 100 is that the exposed electrical connection points 103 have a small area, a conductive layer is formed on the active surface 1001 of the wafer, and then a protective layer opening is formed, which can effectively reduce the difficulty of forming the protective layer opening and avoid the protective layer opening. The opening lower surface 109a is too small, making it difficult to form the protective layer opening 109 .

Preferably, the protective layer opening is formed by laser patterning.

Corresponding to the wafer conductive layer 106 in FIG. 2a, FIG. 4a shows that the protective layer 107 is formed on the wafer conductive layer 106 that interconnects and leads out a plurality of the electrical connection points 103 to each other, as shown in the figure Since each wafer conductive layer 106 corresponds to a plurality of protective layer openings 109, it can be understood that each wafer conductive layer 106 may correspond to one protective layer opening 109, or a part of the wafer conductive layer 106 may correspond to one protective layer opening 109 , and another part of the wafer conductive layer 106 corresponds to a plurality of protective layer openings 109 .

Corresponding to the wafer conductive layer 106 in FIG. 2b, FIG. 4b shows that the protective layer 107 is formed on the wafer conductive layer 106 from which the electrical connection points 103 are individually drawn out. Preferably, each wafer conductive layer 106 may correspond to one protective layer opening 109 .

Optionally, as shown in FIG. 5 , the protective layer opening 109 is filled with a conductive medium, so that the protective layer opening 109 becomes a conductively filled through hole 111 , and at least a part of the conductively filled through hole 111 is connected to the wafer. The conductive layer 106 is electrically connected, and the protective layer surrounds the conductive filled through hole 111 . The conductive medium can be gold, silver, copper, tin, aluminum and other materials or a combination of materials, or other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metals A deposition process is formed to form conductive filled vias 111 in the protective layer openings 109 .

The filling of the conductive medium may be to completely fill the protective layer opening 109 , or to form a layer of conductive material only in the protective layer opening 109 , which can be electrically connected to the panel-level conductive layer. Correspondingly, the conductive filled via 111 is understood as long as the protective layer opening has a conductive medium that can be electrically connected to the panel-level conductive layer, and it is not necessary to completely fill the protective layer opening.

First, the wafer conductive layer 106 is electrically connected to the electrical connection points 103. Since the wafer conductive layer 106 is formed at the wafer level, the alignment accuracy between the wafer conductive layer 106 and the electrical connection points 103 is high, and then the protective layer opening is formed on the protective layer 107. 109 and/or filling with a conductive medium, so that the position of the wafer conductive layer 106 can be precisely positioned through the protective layer opening 109 .

As shown in FIG. 6 , the wafer 100 on which the wafer conductive layer 106 and the protective layer 107 are applied is cut along the dicing line to obtain a plurality of die 113 , the die 113 has a die active surface 1131 and Die backside 1132.

In one embodiment, the wafer 100 having the wafer conductive layer 106 and the protective layer 107 as shown in FIG. 3 is cut to form the die 113 .

In one embodiment, the wafer 100 having the wafer conductive layer 106 , the protective layer 107 and the protective layer opening 109 as shown in FIGS. 4 a and 4 b is cut to form the die 113 .

In one embodiment, the wafer 100 having the wafer conductive layer 106 , the protective layer 107 and the conductive filled vias 111 as shown in FIG. 5 is diced to form the die 113 .

Due to the material properties of the protective layer, in the dicing process of the wafer 100 , the separated dies 113 are free of burrs and die chips.

In one embodiment, before the step of dicing the wafer 100 to separate the die 113 , the method further includes performing plasma surface treatment on the side of the wafer 100 having the protective layer 107 applied with the protective layer 107 , The surface roughness is increased to increase the adhesion of the die 113 on the carrier plate 117 in the subsequent process, and it is difficult to cause the die movement of the die 113 under the molding pressure.

It can be understood that, if the process allows, after the wafer 100 can be selectively cut into the die 113 to be packaged according to the specific actual situation, a die is formed on the die active surface 1131 of each die 113. Round conductive layer 106 and/or protective layer 107 . The wafer conductive layer 106 refers to the conductive layer formed before the wafer 100 is cut into dies 113 and mounted on the carrier.

As shown in Fig. 7a, Fig. 7b and Fig. 7c, a carrier board 117 is provided, the carrier board 117 has a carrier board front 1171 and a carrier back side 1172, which are arranged and divided on preset positions of the carrier board front 1171 For the die 113 , the die active surface 1131 faces the carrier board 117 , and the die back surface 1132 is arranged away from the carrier board 117 .

The shape of the carrier board 117 is: circular, triangular, quadrilateral or any other shape. The size of the carrier board 117 can be a wafer substrate of small size, or a rectangular carrier board of various sizes, especially a large size. The material of 117 can be metal, non-metal, plastic, resin, glass, stainless steel, etc. Preferably, the carrier plate 117 is a large-sized quadrilateral panel made of stainless steel.

The carrier 117 has a front side 113 of the carrier and a back side 115 of the carrier. The front side 113 of the carrier is preferably a plane.

In one embodiment, the die 113 is bonded and fixed on the carrier board 117 by using the adhesive layer 121 .

The adhesive layer 121 may be formed on the front surface 1171 of the carrier board by lamination, printing, spraying, coating, or the like. In order to facilitate the separation of the carrier board 117 and the back-molded die 113 in the subsequent process, the adhesive layer 121 is preferably made of an easily separable material, for example, a thermal separation material is used as the adhesive layer 121 .

Preferably, the position where the die 113 is arranged can be pre-marked on the carrier board 117 , and the marking can be formed on the carrier board 117 by means of laser, mechanical engraving, etc. At the same time, the die 113 is also provided with an alignment mark. , so as to be aligned with the pasting position on the carrier board 117 when pasting.

The die 113 arranged on the carrier 117 may be in the form of the wafer conductive layer 106 on the die 113 as shown in FIG. The electrical connection points 103 are interconnected and drawn out in the form of die; it can also be the wafer conductive layer 106 as shown in FIG. 7b to electrically connect at least a part of the active surface 1131 of the die The form of the die that the point 103 leads out alone; it can also be in the form of the die 113 formed by cutting the wafer 100 with the wafer conductive layer 106 and the protective layer 107 as shown in FIG. 3 ; cutting as shown in FIG. 5 The wafer 100 having the wafer conductive layer 106 , the protective layer 107 and the conductive filled vias 111 is formed in the form of a die 113 .

Optionally, as shown in FIG. 7c , in one encapsulation process, a plurality of dies 113a and 113b with different functions, two of which are shown in the figure, or more than two, may be assembled according to The actual product requirements are arranged on the carrier board 117 and packaged, and after the package is completed, it is cut into a plurality of packages; thus, one package includes a plurality of the dies 113a and 113b to form a multi-chip module (multi-chip module, MCM), and the positions of the plurality of the dies 113a and 113b can be freely set according to the needs of the actual product.

As shown in FIG. 8 , the molding layer 123 is formed.

A plastic encapsulation layer 123 is formed around the to-be-packaged die 113 and the exposed surface of the front surface 1171 of the carrier board or the adhesive layer 121 . The plastic encapsulation layer 123 is used to completely encapsulate the front surface 1171 of the carrier board and the die 113 to be packaged, so as to reconstruct a flat structure, so that after the carrier board 117 is peeled off, the next steps can be performed on the reconstructed flat structure. packaging steps.

The surface of the plastic sealing layer 123 in contact with the front surface 1171 of the carrier or the adhesive layer 121 is defined as the front surface 1231 of the plastic sealing layer. The side of the plastic sealing layer 123 facing away from the front surface 1171 of the carrier or the adhesive layer 121 is defined as the back surface 1232 of the plastic sealing layer.

Preferably, the front surface 1231 of the plastic sealing layer and the back surface 1232 of the plastic sealing layer are substantially flat and parallel to the front surface 1171 of the carrier board.

The plastic sealing layer 123 may adopt paste printing, injection molding, thermocompression molding, compression molding, transfer molding, liquid sealant molding, vacuum lamination, or other suitable molding methods. The plastic encapsulation layer 123 may be an organic composite material, a resin composite material, a polymer composite material, or a polymer composite material, such as epoxy resin with filler, ABF (Ajinomoto buildup film) or other polymers with suitable filler.

In one embodiment, the plastic sealing layer 123 is formed by using an organic/inorganic composite material by molding.

Preferably, the thermal expansion coefficient of the plastic sealing layer 123 is 3-10 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the plastic sealing layer 123 is 5 ppm/K; in another preferred embodiment, the plastic sealing layer The thermal expansion coefficient of 123 is 7 ppm/K; in another preferred embodiment, the thermal expansion coefficient of the plastic sealing layer 123 is 10 ppm/K.

Preferably, the plastic sealing layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients.

The thermal expansion coefficient of the plastic sealing layer 123 is selected to be 3~10 ppm/K and the thermal expansion coefficient of the selected protective layer 107 is the same or similar. During the heating and cooling process of the plastic sealing process, the expansion and contraction between the protective layer 107 and the plastic sealing layer 123 The two materials are not easy to produce interface stress. The low thermal expansion coefficient makes the thermal expansion coefficient of the plastic sealing layer, the protective layer and the die close to each other, so that the interface of the plastic sealing layer 123, the protective layer 107 and the die 113 is closely combined to avoid the occurrence of an interface. layer separation.

In the process of using the packaged chip, it is often necessary to go through cold and heat cycles. Since the thermal expansion coefficients of the protective layer 107 , the plastic sealing layer 123 and the die 113 are similar, during the cold and heat cycle, the protective layer 107 , the plastic sealing layer 123 and the die 113 have similar thermal expansion coefficients. The interface fatigue is small, and the interface gap is not easy to appear between the protective layer 107 , the plastic sealing layer 123 and the die 113 , so that the service life of the chip is prolonged, and the chip can be applied in a wide range of fields.

The difference in thermal expansion coefficient between the die 113 and the plastic sealing layer 123 will also cause warping of the panel module after plastic sealing. Due to the warping phenomenon, it is difficult to locate the die 113 in the panel module in the subsequent conductive layer forming process. The precise position of the conductive layer has a great influence on the formation process of the conductive layer.

In particular, in the large-panel packaging process, due to the large size of the panel, even a slight panel warpage will cause the die of the outer and surrounding parts of the panel far from the center to have a larger size than before molding. Therefore, in the large-scale panel packaging process, solving the warpage problem has become one of the keys to the entire process. The warpage problem even limits the enlarged development of the panel size and becomes a technical barrier in the large-scale panel packaging.

The thermal expansion coefficients of the protective layer 107 and the plastic sealing layer 123 are limited within the range of 3 to 10 ppm/K, and preferably the plastic sealing layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients, which can effectively Avoid the warpage of the panel module, and realize the packaging process using a large panel.

At the same time, in the process of plastic sealing, since the plastic sealing pressure will generate pressure on the back of the die 113 , the pressure is easy to press the die 113 into the adhesive layer 121 , so that the die 113 is trapped in the process of forming the plastic sealing layer 123 . In the adhesive layer 121, after the plastic sealing layer 123 is formed, the die 113 and the front surface 1231 of the plastic sealing layer are not in the same plane, and the surface of the die 113 protrudes beyond the front surface 1231 of the plastic sealing layer, forming a stepped structure. During the formation of the conductive layer, the conductive traces 125 also have a stepped structure correspondingly, which makes the package structure unstable.

When the active surface 1131 of the die has a protective layer 107 with material properties, it can play a buffering role under the plastic sealing pressure to prevent the die 113 from sinking into the adhesive layer 121, thereby avoiding the generation of a stepped structure on the front surface 1231 of the plastic sealing layer.

As shown in FIG. 9a, the thickness of the plastic sealing layer 123 can be reduced by grinding or polishing the back surface 1232 of the plastic sealing layer.

In one embodiment, as shown in FIG. 9 b , the thickness of the plastic encapsulation layer 123 may be reduced to the backside 1132 of the die 113 , thereby exposing the backside 1132 of the die. The packaged chip structure is shown in Figure 15b.

As shown in FIG. 10 , the carrier plate 117 is peeled off to expose the front surface 1231 of the plastic sealing layer and the protective layer 107 .

In one embodiment, when the die 113 arranged on the carrier 117 has a protective layer opening 109 , the carrier 117 is peeled off, and the protective layer opening 109 is also exposed.

In one embodiment, when the die 113 arranged on the carrier 117 has not yet formed a protective layer opening on the protective layer 107 , after the carrier 117 is peeled off, there is still a The step of forming the protective layer opening on the protective layer 107 on the die 113 covered by the plastic sealing layer 123 is described above.

In one embodiment, when the die 113 arranged on the carrier 117 is the die 113 having the conductive filled via 111 , the conductive filled via 111 is also exposed.

After the carrier board 117 is separated, the structure of the plastic encapsulation layer 123 covered with the die 113 is defined as a panel module 150 .

FIGS. 11 and 12 illustrate one embodiment of a process of forming a patterned panel-level conductive layer on the die 113 in the molding layer 123 .

When the protective layer 107 covering the surface of the die 113 in the plastic encapsulation layer 123 has not yet formed conductive filled vias 111 , the protective layer openings 109 are filled with a conductive medium, so that the protective layer openings 109 become conductive filled vias 111 , at least a part of the conductively filled vias 111 are electrically connected to the wafer conductive layer 106 , and the protective layer surrounds the conductively filled vias 111 . The conductive medium can be gold, silver, copper, tin, aluminum and other materials or a combination of materials, or other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metals A deposition process is formed to form conductive filled vias 111 in the protective layer openings 109 .

The filling of the conductive medium may be to completely fill the protective layer opening 109 , or to form a layer of conductive material only in the protective layer opening 109 , which can be electrically connected to the panel-level conductive layer. Correspondingly, the conductive filled via 111 is understood as long as the protective layer opening has a conductive medium that can be electrically connected to the panel-level conductive layer, and it is not necessary to completely fill the protective layer opening.

11 shows the formation of conductive traces 125 on die 113 in plastic encapsulation layer 123; at least a portion of said conductive traces 125 is formed on the surface of protective layer 107 on said die active surface 1131, and At least a portion of the conductive filled vias 111 are electrically connected; in one embodiment, the conductive traces 125 extend along the surface of the protective layer 107 and the front side 1231 of the molding layer, and extend to the edge of the chip package when the package is completed, and the package is molded The wafer structure is shown in Figure 15b. The conductive traces 125 extend to the edge of the package body. At this time, the conductive traces 125 cover and connect the interface between the protective layer 107 and the plastic sealing layer 132, which increases the stability of the packaged chip structure.

The conductive traces 125 may be one or more layers of copper, gold, silver, tin, aluminum, etc. materials or combinations thereof, or may be other suitable conductive materials by utilizing PVD, CVD, sputtering, electrolytic plating, electroless plating processes , or other suitable metal deposition processes.

Preferably, the formation process of the conductive traces 125 and the filling process of the conductive material for the conductive filling of the vias 111 are formed in the same metal layer formation process.

Of course, the process of forming the conductive traces 125 and the process of filling the conductive material of the conductive vias 111 can also be performed in steps.

FIG. 12 shows the formation of conductive studs 127 on the pads or connection points of the conductive traces 125; the shape of the conductive studs 127 may be round, or other shapes such as oval, square, line, etc. . The conductive bumps 127 can be one or more layers of copper, gold, silver, tin, aluminum and other materials or a combination of materials, or can be other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electroless plating process , or other suitable metal deposition processes.

The panel-level conductive layer is composed of conductive traces 125 and/or conductive bumps 127, and the panel-level conductive layer may be one layer or multiple layers. The panel-level conductive layer may have the function of fan-out RDL.

As shown in Figures 13a, 13b and 13c, a dielectric layer 129 is formed on the panel level conductive layer.

One or more dielectric layers 129 are formed on the surface of the panel-level conductive layer using lamination, coating, spraying, printing, molding, and other suitable methods.

The dielectric layer 129 can be BCB (benzocyclobutene), PI (polyimide), PBO (polybenzoxazole), ABF, silicon dioxide, silicon nitride, silicon oxynitride, tantalum pentoxide , alumina, polymer matrix dielectric film, organic polymer film; can also be organic composite materials, resin composite materials, polymer composite materials, polymer composite materials, such as epoxy resin with filler, ABF, or Other polymers for suitable fillers; other materials with similar insulating and structural properties are also possible. In a preferred embodiment, the secondary dielectric layer 129 is ABF. The dielectric layer 129 functions to protect the conductive layer and to insulate.

In one embodiment, the applied thickness of the dielectric layer 129 is thicker than that of the panel-level conductive layer, and the panel-level conductive layer is exposed through a grinding process; in another embodiment, the applied thickness of the dielectric layer 129 is the same as the panel-level conductive layer. The thickness of the conductive layer is the same, and the panel-level conductive layer is just exposed after the dielectric layer 129 is applied.

In one embodiment, the steps of FIGS. 11 to 13 c are repeated to form a multi-layer panel-level conductive layer on the die active surface 1131 of the die 113 .

Return to the steps of Figures 11 to 13c. In one embodiment, the steps of forming the panel-level conductive layer may be: forming conductive traces 125 on the die active surface 1131 of the die 113; Using lamination, coating, spraying, printing, molding and other suitable methods to form one or more dielectric layers 129 on the surface of the conductive traces 125, the height of the dielectric layer 129 is higher than the height of the conductive traces 125, the conductive traces 125. traces 125 are completely encapsulated in dielectric layer 129; and Openings are formed on the dielectric layer 129 at locations corresponding to pads or connection points of the conductive traces 125, and conductive bumps 127 are formed within the openings.

In yet another embodiment, the conductive bumps 127 may not be formed in the opening, so that the solder pads or connection points of the conductive traces 125 of the completed package are exposed from the opening.

In a preferred embodiment, after the step of applying the dielectric layer 129, the thickness of the outermost panel-level conductive layer is thinned by etching to form grooves 131 on the outer surface of the dielectric layer 129. The packaged chip structure is shown in Figure 15b shown.

Optionally, as shown in FIG. 13c, in one encapsulation process, multiple, especially multiple dies 113a and 113b with different functions, two of which are shown in the figure, or more than two, can be encapsulated. As a multi-chip package module, the pattern design of the conductive structures of the plurality of dies 113a and 113b is designed according to the electrical connection requirements of the actual product. The packaged chip structure is shown in Figure 15d.

As shown in FIG. 14 , the packaged monomers are separated by dicing to form a packaged wafer, which can be diced by machine or laser.

15a , 15b , 15c and 15d are schematic diagrams of a chip package structure obtained by a packaging method provided by an exemplary embodiment of the present disclosure. A chip package structure includes: at least one die 113 , and the die 113 includes The active surface 1131 of the die and the back surface 1132 of the die; the conductive structure is formed on the side of the active surface 1131 of the die; the protective layer 107 is formed on the side of the active surface 1131 of the die; the plastic sealing layer 123 is the plastic sealing layer 123 is used to encapsulate the die 113; the dielectric layer 129.

In some embodiments, the conductive structure includes a wafer conductive layer 106 , a conductively filled via 111 and a panel-level conductive layer 170 ; the conductively filled via 111 is formed in the protective layer 107 .

In some embodiments, the die active surface 1131 includes electrical connection points 103 and an insulating layer 105; a part or all of the wafer conductive layer 106 is electrically connected to a part or all of the electrical connection points 103 for electrical connection Part or all of the electrical connection points 103 are drawn out from the active surface 1131 of the die; the lower surface 111a of the conductively filled via is electrically connected to the wafer conductive layer 106; the upper surface 111b of the conductively filled via is connected to the panel The level conductive layer 170 is electrically connected.

In some embodiments, the panel-level conductive layer 170 includes conductive traces 125 and/or conductive bumps 127; the conductive bumps 127 are formed on pads or connection points of the conductive traces 125; the The dielectric layer 129 covers the panel-level conductive layer 170; the panel-level conductive layer 170 is one layer.

Although not shown in the figures, the panel-level conductive layer may also be multi-layered.

In some embodiments, the Young's modulus of the protective layer 107 is any one of the following numerical ranges or values: 1000-20000 MPa, 1000-10000 MPa, 4000-8000 MPa, 1000-7000 MPa, 4000-7000 MPa, 5500MPa.

In some embodiments, the material of the protective layer 107 is an organic/inorganic composite material.

In some embodiments, the thickness of the protective layer 107 is any one of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, and 50 μm.

In some embodiments, the thermal expansion coefficient of the protective layer 107 is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In some embodiments, the thermal expansion coefficient of the plastic sealing layer 123 is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In some embodiments, the protective layer 107 and the plastic sealing layer 123 have the same or similar thermal expansion coefficients.

In some embodiments, the protective layer 107 includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm.

In some embodiments, the diameter of the inorganic filler particles is 1-2 μm.

In some embodiments, as shown in the enlarged view of FIG. 15a, the conductively filled via 111 has a conductively filled via lower surface 111a and a conductively filled via upper surface 111b, and the area of the conductively filled via lower surface 111a is smaller than the area of the upper surface 111b of the conductive filled via.

In some embodiments, as shown in FIGS. 15 a and 15 b , at least a portion of the wafer conductive layer 106 interconnects and leads out a plurality of the electrical connection points 103 in at least a portion of the active surface 1131 of the die. .

In some embodiments, as shown in FIG. 15c , at least a part of the wafer conductive layer 106 separates at least a part of the electrical connection points 103 on the active surface 1131 of the die.

In some embodiments, as shown in the partial enlarged view in FIG. 15c , the contact area α2 of the single contact area between the wafer conductive layer 106 and the electrical connection point 103 is smaller than the contact area α2 between the wafer conductive layer 106 and the conductive layer 103 . The contact area β2 of the single contact area filling the via hole 111 .

In some embodiments, as shown in FIG. 15b , at least a portion of the conductive traces 125 closest to the die active surface 1131 is formed on the front side 1231 of the molding layer and extends to the edge of the package body.

In some embodiments, as shown in FIG. 15b , the backside 1132 of the die is exposed from the molding layer 123 .

In some embodiments, as shown in FIG. 15b, the surface of the dielectric layer 129 has grooves at locations corresponding to the conductive layers.

In some embodiments, as shown in FIGS. 15 a , 15 b , and 15 c , the package structure includes a plurality of dies 113 .

In some embodiments, as shown in FIG. 15d , the package structure includes a plurality of die 113, and the plurality of die 113 are electrically connected according to product design.

Preferably, the plurality of die 113 are die with different functions to form a multi-chip module.

FIG. 16 shows a schematic diagram of the package wafer in use. During use, the package wafer is connected to a circuit board or substrate 161 by solder 160, and then connected to other circuit elements.

When the surface of the dielectric layer 129 of the package chip has the groove 131, the solder 160 can be connected stably and not easily moved.

The specific embodiments described above are intended to further describe the technical solutions and technical effects of the present disclosure in detail, but those skilled in the art will understand that the specific embodiments described above are not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the inventive idea of the present disclosure should be included within the protection scope of the present disclosure.

100: Wafer 1001: Wafer Active Surface 1002: Wafer backside 103: Electrical connection point 105: Insulation layer 106: Wafer Conductive Layer 107: Protective layer 109: Protective layer opening 109a: Lower surface of protective layer opening 109b: upper surface of protective layer opening 109c: Protective layer opening sidewall 111: Conductive Filled Vias 111a: Conductive filled via lower surface 111b: conductive filled via upper surface 113: Die 113a: grain 113b: grain 1131: Grain Active Surface 1132: Die backside 117: carrier board 1171: front side of carrier board 1172: Back of carrier board 121: Adhesive layer 123: Plastic layer 1231: Front of plastic layer 1232: The back of the plastic layer 125: Conductive traces 127: conductive bump 129: Dielectric layer 131: Groove 150: Panel Module 160: Solder 161: Substrate 170: Panel level conductive layer α1, α2: Contact area β1, β2: Contact area

1 to 14 are flowcharts of a chip packaging method proposed according to an exemplary embodiment of the present disclosure; 1 is a schematic diagram of a wafer in accordance with an exemplary embodiment of the present disclosure; 2a and 2b are schematic views of a wafer after forming a wafer conductive layer according to an exemplary embodiment of the present disclosure; 3 is a schematic diagram of a wafer after a protective layer is applied according to an exemplary embodiment of the present disclosure; 4a and 4b are schematic diagrams of wafers forming protective layer openings in accordance with exemplary embodiments of the present disclosure; 5 is a schematic diagram of a wafer with conductive filled vias formed in accordance with an exemplary embodiment of the present disclosure; 6 is a schematic diagram of dicing a wafer to form a die according to an exemplary embodiment of the present disclosure; 7a and 7b are schematic diagrams of mounting a die on a carrier according to an exemplary embodiment of the present disclosure; FIG. 7c is a schematic diagram of a die assembly attached to a carrier according to an exemplary embodiment of the present disclosure; 8 is a schematic diagram of forming a plastic encapsulation layer on a carrier according to an exemplary embodiment of the present disclosure; FIG. 9a is a schematic diagram of reducing the thickness of the plastic sealing layer according to an exemplary embodiment of the present disclosure; FIG. 9b is a schematic diagram of thinning the plastic encapsulation layer to expose the backside of the die according to an exemplary embodiment of the present disclosure; 10 is a schematic diagram of peeling off the carrier plate and the adhesive layer in accordance with an exemplary embodiment of the present disclosure; 11 is a schematic diagram of forming conductive filled vias and conductive traces on a panel module according to an exemplary embodiment of the present disclosure; 12 is a schematic diagram of forming conductive bumps on a panel module according to an exemplary embodiment of the present disclosure; 13a, 13b and 13c are schematic diagrams of forming a dielectric layer on a panel module according to an exemplary embodiment of the present disclosure; 14 is a schematic diagram of splitting a panel module to form a packaged wafer according to an exemplary embodiment of the present disclosure; 15a, 15b, 15c and 15d are schematic diagrams of a chip package structure obtained by using the above-mentioned packaging method according to an exemplary embodiment of the present disclosure; 16 is a schematic diagram of a packaged wafer in use according to an exemplary embodiment of the present disclosure.

103: Electrical connection point

105: Insulation layer

106: Wafer Conductive Layer

107: Protective layer

111: Conductive Filled Vias

111a: Conductive filled via lower surface

111b: conductive filled via upper surface

113: Die

1131: Grain Active Surface

1132: Die backside

123: Plastic layer

1231: Front of plastic layer

1232: The back of the plastic layer

125: Conductive traces

127: conductive bump

129: Dielectric layer

170: Panel level conductive layer

Claims (19)

A chip package structure includes: at least one die, the die includes a die active surface and a die back, the die active surface includes an electrical connection point and an insulating layer; a conductive structure is formed on the die On the side of the active surface of the die, the conductive structure includes a wafer conductive layer, a conductive filled via and a panel-level conductive layer; a protective layer is formed on the active surface side of the die and its side is the same as the side of the die flush; a plastic encapsulation layer used to encapsulate the chip; and a dielectric layer encapsulated on the panel-level conductive layer. The chip package structure according to claim 1, wherein the conductive filled via is formed in the protective layer. The chip package structure according to claim 2, wherein: at least a part of the conductive layer of the wafer is electrically connected to the electrical connection point, so as to lead the electrical connection point from the active surface of the die; at least a part of the conductive layer is filled under the through hole The surface is electrically connected to the wafer conductive layer; and at least a portion of the upper surface of the conductive filled via is electrically connected to the panel-level conductive layer. According to the chip package structure of claim 3, at least a part of the conductive layer of the wafer interconnects and leads out a plurality of the electrical connection points to each other. According to the chip package structure of claim 3, at least a part of the conductive layer of the wafer leads out the electrical connection point independently. According to the chip package structure of claim 5, the contact area between the wafer conductive layer and the single contact area of the electrical connection point is smaller than the contact area between the wafer conductive layer and the single contact area of the conductive filled via. The chip package structure of claim 3, wherein the panel-level conductive layer includes a conductive trace and/or a conductive bump; and the panel-level conductive layer is one or more layers. The chip package structure as claimed in claim 7, at least a part of the conductive trace closest to the active surface of the die is formed on the front side of a plastic packaging layer and extends to an edge of a package body. The chip package structure according to claim 3, wherein the backside of the die is exposed from the plastic sealing layer. The chip package structure according to claim 3, wherein the surface of the dielectric layer has a groove corresponding to the position of the panel-level conductive layer. The chip package structure according to any one of claims 1 to 10, wherein the at least one die is a plurality of die, and the plurality of die is electrically connected according to product design. The chip package structure according to any one of claims 1 to 10, wherein the material of the protective layer is an organic/inorganic composite material. According to the chip package structure of claim 12, the Young's modulus of the protective layer is in the range of 1000-20000 MPa. According to the chip package structure of claim 12, the thickness of the protective layer is in the range of 15-50 μm. According to the chip package structure of claim 12, the thermal expansion coefficient of the protective layer is in the range of 3-10 ppm/K. According to the chip package structure of claim 12, the thermal expansion coefficient of the plastic sealing layer is in the range of 3-10 ppm/K. The chip package structure according to claim 12, wherein the protective layer and the plastic sealing layer have the same or similar thermal expansion coefficients. The chip package structure according to claim 12, wherein the protective layer includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm. The chip package structure of claim 12, wherein the conductively filled via has a lower surface of the conductively filled via and an upper surface of the conductively filled via, and the area of the lower surface of the conductively filled via is smaller than the upper surface of the conductively filled via area.

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