JP2010118534A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has high reliability and good productivity by enhancing bonding strength between a carrier substrate and a semiconductor element, and a method of manufacturing the same. <P>SOLUTION: The semiconductor device 13 includes the carrier substrate 1, a flip-chip pad electrode 4 formed on the carrier substrate 1, a gold bump 15 bonded on an upper surface and a side surface of the flip-chip pad electrode 4, and the semiconductor element 5 electrically connected to the flip-chip pad electrode 4 through the gold bump 15. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a pad electrode and a bump bonded to each other and a manufacturing method thereof.

  As high-speed and large-capacity communication means in the computer and broadband communication fields, wired communication devices using optical fibers and the like, and wireless communication devices using microwaves and millimeter waves are particularly widespread. These communication devices incorporate high-performance high-frequency transistors and semiconductor elements such as MMIC (Monolithic Microwave Integrated Circuit). Since this type of equipment operates in a high-frequency region exceeding GHz, it is not a silicon that is widely used as a material for semiconductor elements, but a compound semiconductor, particularly a gallium arsenide (GaAs) semiconductor, which has excellent high-frequency characteristics. Is often chosen.

  In order to complete the electronic circuit by combining the semiconductor elements, it is necessary to provide wiring for connection in order to electrically connect a plurality of pad electrodes formed on the surface of the semiconductor element to an external circuit. There is. In general, in a semiconductor element, the semiconductor element is fixed with a conductive adhesive or the like with the circuit surface facing upward, and a gold wire or an aluminum wire is connected between the pad electrode and the corresponding external electrode. Such metal wires are subjected to ultrasonic bonding (wire bonding), whereby loop-shaped wiring is performed.

  However, especially in the case of electronic circuits that operate in the high-frequency region, if the pad electrode of the semiconductor element and the external electrode are connected by a looped metal wire, the parasitic inductance and parasitic capacitance caused by the wire itself increase. As a result, impedance mismatch occurs at the connection. As a result, transmission loss of high-frequency signals occurs and transmission efficiency deteriorates. As one means for solving this problem, a flip chip mounting method, which is a method for connecting semiconductor elements without using metal wires, has been developed.

  On the other hand, in a semiconductor device in which a high-frequency compatible semiconductor element is accommodated, a hermetically sealed hollow ceramic or metal package is employed from the viewpoint of low loss and high reliability. The carrier substrate used in such a package has the disadvantages that it is heavy and expensive because performance and reliability are most important. However, a package using a ceramic carrier substrate is used because of the advantage of low electrical loss. In the era when the performance and reliability of semiconductor devices were the top priority, the above drawbacks were not regarded as a problem. In the era when the system price is high, the cost of such a package is small in the total system cost. Therefore, the cost reduction is not so important. However, in a social environment where high-quality and high-performance systems need to be provided at low prices recently, cost is an important factor that cannot be ignored and must be reduced as much as possible.

  For this reason, there has been proposed a semiconductor device of a type in which a semiconductor element is flip-chip bonded to a carrier substrate (printed substrate) using a resin that is advantageous in cost, although the performance is slightly inferior to that of a ceramic material.

  By the way, as a system for connecting the pad electrode of the semiconductor element and the pad electrode of the carrier substrate by flip chip, several methods have been proposed as shown below. In either method, a protruding electrode called a stud bump or simply a bump is provided in advance on a pad electrode of a semiconductor element or a pad electrode of a carrier substrate. The bump electrode is used to connect the pad electrode of the semiconductor element and the pad electrode of the carrier substrate.

  First, there is a method using solder. In this method, solder bumps provided on one or both of the pad electrodes to be connected, or pad electrodes having a solder layer that has been supplied in advance by a screen printing method or a plating method, that is, subjected to a pre-coating treatment, are aligned with each other. Connected by being heated and pressurized.

  This method has a problem when the distance between adjacent pad electrodes is small. In the heating / pressurizing step, the molten solder is pushed out and protrudes from the pad electrode, whereby the solders of the pad electrodes adjacent to each other come into contact with each other. As a result, a short circuit occurs between adjacent pad electrodes, and normal connection cannot be made.

  The limit value of the distance between adjacent pads is considered to be around 120 μm, although it depends on the size of the solder bump.

  In general, compound semiconductors such as GaAs and InP (indium phosphide), which are known as high-frequency compatible semiconductor elements, are expensive in material cost, so that an element with as small an area as possible is manufactured. For this reason, the electrode pitch of the element also tends to be narrowed, and there are cases in which the distance between adjacent pads is 100 μm or less. Therefore, it is difficult to deal with recent narrow pitch semiconductor elements by the method using solder.

  Secondly, a method has been proposed in which a conductive paste mixed with silver or the like is applied to the tip end portion of a stud bump formed of gold or the like and pressed against a pad electrode of a carrier substrate to be bonded. However, in consideration of problems such as the adhesive supply method and the wetting and spreading of the paste when the bump and the pad electrode are in contact, there is a problem similar to the method using the above-mentioned solder. Have difficulty.

  Third, there is a method using ACF (anisotropic conductive film). ACF is an abbreviation for Anisotropic Conductive Film, in which conductive particles having a diameter of several μm are dispersed in a semi-cured insulating adhesive film formed into a film shape. In this method, the ACF is heated and pressed in a state of being interposed between the bump formed on the pad electrode of the semiconductor element and the pad electrode of the carrier substrate, thereby performing flip chip connection. Conductivity is imparted between the upper and lower pad electrodes that are in contact via the conductive particles sandwiched between the pad electrodes. On the other hand, the pad electrodes adjacent to each other that are not in contact with each other through the conductive particles are given insulation. This method can also be applied to a semiconductor device having a narrow pitch pad electrode. However, an organic polymer material is usually used for the insulating adhesive film forming the ACF, and the polymer material generally has a large dielectric loss and is not suitable for connection of a high frequency device.

  Finally, there is a method using metal bumps. This method is a method called solid phase diffusion bonding in which metal bumps are heated and pressurized or bonded by applying ultrasonic vibration. Solid phase diffusion bonding means diffusion of atoms that occur between metals when solid metal that does not melt (solid state) is in close contact and heated and pressurized in a vacuum, reducing gas atmosphere, inert gas atmosphere, etc. It is the method of joining using. Usually, it is often carried out at a high temperature of several hundred degrees Celsius. Fundamentally, in gold-gold bonding where an oxide layer is not formed, bonding is possible even in a relatively low temperature region of about 300 ° C. or lower. If ultrasonic vibration is used in the same manner as the wire bonding described above, bonding at a lower temperature (200 ° C. or lower) is possible. When this method is applied to flip chip bonding, a system that normally uses a heating environment of about 100 to 200 ° C. and ultrasonic bonding is used. This method is the only bonding method applicable to narrow pitch semiconductor devices.

  The flip chip mounting method is roughly classified into the methods described above. When a semiconductor element is flip-chip bonded to a resin carrier substrate, the following problem arises due to the difference in physical properties with the ceramic carrier substrate. In the case of a resin carrier substrate, there is a problem that the resin material is softened in a high temperature environment, and therefore the bonding temperature cannot be increased. For example, in the case of a widely used FR-4 substrate, the Tg (Glass transition temperature), which is a measure of the softening temperature, is around 125 ° C, so the temperature range that can be used avoiding softening is around 100 ° C. Up to. Even in a substrate using a high Tg material that can withstand high temperatures, the temperature range in which it can be used while avoiding softening is about 150 ° C. at most. That is, in the case of a resin carrier substrate, flip chip bonding needs to be performed in an environment of about 100 to 150 ° C. unless a special material is used.

  On the other hand, a resin carrier substrate has a larger coefficient of linear expansion than a semiconductor element. For example, the linear expansion coefficient in the plane (horizontal) direction of an FR-4 substrate that is widely used is approximately 16 ppm / ° C. On the other hand, the linear expansion coefficient of the Si (silicon) semiconductor element is about 3 ppm / ° C. The linear expansion coefficient of the GaAs semiconductor is about 5 ppm / ° C. For this reason, when the resin carrier substrate and the semiconductor element are connected in a high temperature environment, the flip is caused by a thermal expansion mismatch generated between the pad electrode between the resin carrier substrate and the semiconductor element in the process of cooling to room temperature. An excessive mechanical stress is generated at the chip joint, which may cause a problem in connection reliability.

  In general, flip chip bonding of a semiconductor element to a resin carrier substrate is desirably performed at a temperature as low as possible for the reasons described above. For this reason, a gold-gold bonding method using both heat and ultrasonic waves is usually employed.

  Furthermore, even if the gold-gold bonding method using both heat and ultrasonic waves is adopted, the resin carrier substrate is more flexible and has lower rigidity than the ceramic carrier substrate, so that high strength bonding is possible. The high load and high ultrasonic power necessary for realizing the above cannot be applied. Therefore, it is not possible to use a method for obtaining a high bonding force by increasing the load or the ultrasonic power.

  For this reason, a structure that realizes high-strength bonding by providing a device for improving the strength at a portion to be bump-connected has been proposed. This structure is resistant to thermal stress caused by changes in environmental temperature immediately after bonding or after bonding.

  For example, Japanese Patent Application Laid-Open No. 2002-222832 discloses a semiconductor device that realizes high-strength bonding by providing a device for improving strength in a bump-connected portion.

In the semiconductor device disclosed in this publication, a mounting pad formed on a substrate and a bump formed on a semiconductor element are electrically joined. A plurality of needle-like or dendritic protrusions are formed as anchors on the mounting pad or bump. The needle-shaped or dendritic protrusion bites into the bump or pad, whereby the mounting pad and the bump are anchored. Further, gold plating is formed on the surface of the anchor portion. This improves the bonding strength between the semiconductor element and the substrate.
Japanese Patent Laid-Open No. 2002-222832

However, the above-described semiconductor device has the following problems regarding the anchor structure.
First, in order to form the anchor structure at the joint or its equivalent part, a dedicated process for forming the anchor structure is required. This dedicated process is a separate process other than the normal substrate manufacturing process. Therefore, manufacturing equipment and chemicals specialized for this dedicated process are required. This increases the manufacturing cost. Further, when a large number of carrier substrates that require such another process are required at one time, it is not easy to absorb the process load.

  Also, gold plating or the like is applied to the surface of the anchor structure. However, it is difficult to apply stable plating to the surface after the anchor structure is formed because of its complex physical shape. For example, defects in plating due to defoaming in the plating process, and residual chemicals due to the flow of chemicals occur. In such a case, the desired bonding strength cannot be obtained. Rather, there is a risk that the bonding strength will be significantly reduced due to poor bonding.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a highly reliable and highly productive semiconductor device and a method for manufacturing the same by improving the bonding strength between the carrier substrate and the semiconductor element. Is to provide.

  A semiconductor device of the present invention includes a carrier substrate, a pad electrode formed on the carrier substrate, a bump bonded on the upper surface and side surface of the pad electrode, and a semiconductor element electrically connected to the pad electrode through the bump. It has.

The method for manufacturing a semiconductor device of the present invention includes the following steps.
A carrier substrate on which pad electrodes are formed is prepared. By pressing the bump against the pad electrode, the bump holds the side surface of the pad electrode, and the bump and the upper surface of the pad electrode are solid-phase diffusion bonded.

  According to the semiconductor device of the present invention, since the bump is connected to both the upper surface and the side surface of the pad electrode, the bonding strength between the semiconductor element and the carrier substrate can be improved. Therefore, even if a temperature change occurs due to a change in the surrounding environment or heat generation of the semiconductor device itself, and a thermal stress based on a difference in linear expansion coefficient between the semiconductor element and the carrier substrate occurs, Connection reliability is maintained.

  In addition, according to the method for manufacturing a semiconductor device of the present invention, the bumps are bonded to the upper surface and side surfaces of the pad electrode to improve the bonding strength, so that a dedicated process other than the normal substrate manufacturing process is unnecessary. Therefore, the semiconductor device manufacturing method of the present invention can improve the bonding strength without increasing the manufacturing cost because the conventional carrier substrate material and manufacturing process are not significantly changed. Further, when a large amount of the semiconductor device of the present invention is needed at one time, it is easy to absorb the process load. Thereby, productivity can be improved.

  That is, according to the present invention, an inexpensive semiconductor device excellent in mass productivity can be provided.

Hereinafter, the present embodiment will be described with reference to the drawings.
(Embodiment 1)
First, the configuration of the semiconductor device according to the first embodiment of the present invention will be described.

  FIG. 1 is a schematic cross-sectional view showing a state in which the semiconductor device of the first embodiment is mounted on a circuit board. FIG. 2 is a schematic perspective view of the semiconductor device according to the first embodiment. FIG. 3 is an enlarged cross-sectional view showing a P portion of FIG.

  1 to 3, a semiconductor device 13 according to the first embodiment includes a carrier substrate 1, an electronic component 2, a component pad electrode 3, a flip chip pad electrode (pad electrode) 4, and a semiconductor element. 5, sealing pad electrode 6, solder fillet 7, lid 8, BGA (Ball Grid Array) pad electrode 9, solder ball 12, gold bump (bump) 15, and semiconductor element pad electrode 16. Has mainly.

  A flip chip pad electrode 4 is formed on the carrier substrate 1. A semiconductor element pad electrode 16 is formed on the semiconductor element 5. The semiconductor element pad electrode 16 of the semiconductor element 5 is electrically connected to the flip chip pad electrode 4 through the gold bump 15.

  The gold bump 15 is joined to the flip chip pad electrode 4 on the upper surface and side surfaces of the flip chip pad electrode 4. The upper surface of the flip chip pad electrode 4 and the gold bump 15 are solid phase diffusion bonded. The side surface of the flip chip pad electrode 4 and the gold bump 15 are joined so that the gold bump 15 holds the flip chip pad electrode 4.

  The carrier substrate 1 is a commercially available copper-clad multilayer printed circuit board mainly composed of, for example, BT resin (bismaleimide / triazine resin). The external dimensions are, for example, length 30 mm × width 30 mm × thickness 1 mm. In the carrier substrate 1, for example, the surface of a copper foil having a thickness of 18 μm to 35 μm serving as a common base is formed on the surfaces of all wirings and electrodes so that the oxidation of the copper foil and the solid phase diffusion bonding of gold can be efficiently performed. Ni plating with a thickness of 3 to 5 μm is applied thereto, and a slightly thick Au plating with a thickness of 0.1 to 0.3 μm is applied thereon. The carrier substrate 1 includes a large number of wirings such as inner layer conductors and via holes used for the connection inside the carrier substrate 1, but is omitted from illustration because it is not directly related to the present embodiment.

  The flip chip pad electrode 4 is a discontinuous wiring formed on the carrier substrate 1. The tip has a pointed shape toward the tip. The gold bumps 15 of the semiconductor element 5 are joined so as to overlap the tip portion. The width of the tip is smaller than the diameter of the gold bump 15. The flip chip pad electrode 4 is formed so as to slightly protrude in the thickness direction with respect to the main surface of the carrier substrate 1 (the surface of the resin portion of the carrier substrate 1). In the first embodiment, a carrier substrate manufactured by a subtractive method in which a copper-clad multilayer printed circuit board is patterned by etching is used, and the protrusion amount is, for example, 40 μm in height including the plating thickness. is there.

  The gold bumps 15 are formed corresponding to the number of semiconductor element pad electrodes 16 of the semiconductor element 5. The semiconductor element 5 and the external circuit are connected through the gold bump 15.

  The semiconductor element 5 is a bare semiconductor element cut out from a wafer, for example. The semiconductor element 5 is flip-chip mounted on the surface (upper surface) of the carrier substrate 1. The material forming the semiconductor element 5 is, for example, gallium arsenide (GaAs). The external dimensions are, for example, length 0.6 mm × width 0.4 mm × thickness 0.2 mm.

  The semiconductor element pad electrode 16 is formed on the semiconductor element 5 and is a connection electrode with an external circuit. Signals are exchanged with external circuits through these electrodes. The semiconductor element pad electrode 16 is formed by, for example, Au plating. The external dimension is, for example, a square having a side of 0.1 mm.

  Various pad electrodes are formed on the carrier substrate 1 as shown in FIG. That is, in addition to the flip chip pad electrode 4, a component pad electrode 3, a sealing pad electrode 6, and a BGA pad electrode 9 are formed. These pad electrodes only have different names depending on the application to be used, and the constituent material is copper, and the basic configuration such as plating is the same. These pad electrodes may be manufactured by any of the normal printed circuit board manufacturing processes such as a subtractive method, an additive method, and a semi-additive method. In addition, the subtractive construction method manufactured by etching the copper foil of the copper clad multilayer printed board is advantageous in terms of cost.

  The electronic component 2 is attached to the component pad electrode 3 formed on the surface (upper surface) of the carrier substrate 1 using solder. The electronic component 2 is, for example, a resistor or a capacitor.

  A lid 8 is soldered to a sealing pad electrode 6 formed on the surface of the carrier substrate 1 via a solder fillet 7. The lid 8 is formed so as to cover the semiconductor element 5 and the electronic component 2 on the carrier substrate 1. The lid 8 is for protecting the semiconductor element 5 and the electronic component 2 on the carrier substrate 1 and also serves as an electromagnetic shield.

  The semiconductor device 13 of the first embodiment is mounted on a resin circuit board 10 such as FR-4 via solder balls 12. BGA pad electrodes 9 for attaching solder balls 12 are arranged on the back side of the carrier substrate 1 in the semiconductor device 13. The semiconductor device 13 is electrically connected to the circuit board 10 by soldering the BGA pad electrode 9 to the circuit board pad electrode 11 provided on the circuit board 10 side via the solder balls 12. A signal circuit wiring or ground electrode 14 made of the same material as the flip chip pad electrode 4 is formed on the back side of the circuit board 10.

  Next, how the semiconductor element 5 is flip-chip bonded to the carrier substrate 1 will be described in order.

  4, 5, and 6 are respectively a schematic perspective view, a schematic plan view, and a schematic side view for explaining the semiconductor element after the semiconductor element is cut from the wafer and before being flip-chip bonded. It is. 4 to 6, first, a semiconductor element 5 having a plurality of semiconductor element pad electrodes 16 formed on the surface is prepared. Gold bumps 15 are formed on each of the plurality of semiconductor element pad electrodes 16 by, for example, a wire bonder or a similar device.

  The gold bump 15 is formed by using a dedicated device for forming a gold bump such as a stud bump bonder. In this apparatus, a gold ball made by discharging and melting the tip of a gold wire is ultrasonically bonded to a predetermined semiconductor element pad electrode 16 through a hollow nozzle-like jig called a capillary, and then the capillary is pulled up. The gold bump 15 having the appearance shown in FIG. 4 is formed by tearing the gold wire in the vertical direction. In general, the bonding strength of the gold bump 15 is more advantageous as the heating temperature is higher. A strong bonding force can be obtained even when the load is low by heating. Applied. For this purpose, the gold bump 15 is formed by raising the temperature of the semiconductor element 5 to around 230 ° C. and simultaneously applying ultrasonic vibration energy of 100 to 200 mW while applying a static load of about 0.5 N. For example, a commercially available gold wire for bump formation having a diameter of 25 μm is used for the gold bump 15. The formed gold bump has a maximum diameter of 100 μm, for example, and the gold bump has a height of 100 μm.

  FIG. 7 is a schematic side view showing an alignment state before flip chip bonding. FIG. 8 is a schematic perspective view in which the vicinity of one gold bump shown in FIG. 7 is enlarged. Referring to FIG. 7, the semiconductor element 5 to which the gold bump 15 is attached is turned upside down. Then, the gold bump 15 and the flip chip pad electrode 4 are faced to align the gold bump 15 with the flip chip pad electrode 4. This alignment is performed so that the tip of the gold bump 15 (the lower end in the figure) matches the tip of the flip chip pad electrode 4 as shown in FIG.

  Although not shown in the drawing, such alignment and flip chip bonding described later are usually performed using a dedicated device called a flip chip bonder. The flip chip bonder can handle semiconductor chips and carrier substrates. In addition, an image processing function using an optical camera for recognizing bumps, pad electrodes, wiring patterns, and the like, and a fine alignment function based thereon are provided. In addition, a heating and pressing mechanism necessary for flip chip mounting, an ultrasonic horn for ultrasonic bonding, and the like are also provided. Thereby, the flip chip bonder can easily perform gold-gold bonding.

  After completion of the above alignment, the gold bump 15 is bonded to the flip chip pad electrode 4 and the semiconductor element 5 is flip chip mounted on the carrier substrate 1. Thus, the gold bump 15 and the gold plating on the upper surface of the flip chip pad electrode 4 are gold-gold bonded (solid phase diffusion bonding), and the flip chip pad electrode is held so that the gold bump 15 holds the side portion of the flip chip pad electrode 4. It is physically joined to the four side surfaces.

  FIG. 9 is a schematic plan view showing a state after the semiconductor element is flip-chip bonded to the carrier substrate. In FIG. 9, in order to make the drawing easier to see, a perspective view from the upper surface is shown. FIG. 10 is a schematic plan view showing the pattern layout of the flip chip pad electrode 4 extracted from FIG. Referring to FIGS. 9 and 10, gold bumps 15 are pressed against and bonded to flip chip pad electrode 4 so as to surround the tip of flip chip pad electrode 4. The tip portion of the flip chip pad electrode 4 is narrower than the tip portion and has a sharp shape toward the tip. FIG. 3 is a sectional view taken along line III-III in this state.

  Next, the shape of the gold bump 15 after flip chip bonding will be described. Further, the state where the tip of the flip chip pad electrode 4 is bonded to the gold bump 15 will be described.

  FIG. 11 is a schematic plan view showing indentations formed by the flip chip pad electrodes of the carrier substrate biting into the gold bumps. That is, this figure is a plan view showing a state in which the semiconductor element 5 after flip-chip bonding is peeled off from the carrier substrate 1. This figure is a plan view seen from the surface on which the semiconductor element pad electrode 16 is formed.

  FIG. 12 is a schematic perspective view in which a part of FIG. 11 is enlarged. That is, it is a schematic perspective view in which only one bump is taken out and enlarged.

  Referring to FIGS. 11 and 12, in gold bump 15 after flip-chip bonding, indentation 17 is formed at the portion where the flip chip pad electrode 4 contacts the upper surface and the side surface of flip chip pad electrode 4 by biting into gold bump 15. Is formed. As a result, the tip of the flip chip pad electrode 4 is joined so as to be held in the gold bump 15.

  Next, a method for manufacturing the semiconductor device according to the first embodiment of the present invention including the above-described flip chip bonding will be described.

Referring to FIG. 1, first, the carrier substrate 1 is prepared.
Next, flux is supplied to the BGA pad electrode 9 on the back surface of the carrier substrate 1, and the solder balls 12 are attached. In general, a ball mounter, which is a dedicated device, is used for supplying flux necessary for mounting the solder balls 12 and mounting the solder balls 12. With the back surface (lower side) of the carrier substrate 1 facing upward, the transfer method (flux adhered to the protruding jig is transferred to the BGA pad electrode 9) or printing method (screen printing) on the surface of the BGA pad electrode 9 Flux is supplied to the BGA pad electrode 9 by this method. Solder balls 12 are temporarily mounted on the BGA pad electrodes 9 of the carrier substrate 1 to which the flux has been supplied. The size of the solder ball 12 used is, for example, 0.6 mm in diameter. Solder balls 12 corresponding to the number and pitch of the BGA pad electrodes 9 are collectively sucked by a vacuum suction jig and mounted on the BGA pad electrodes 9 to which the flux has been supplied. Since the flux has an adhesive force, the solder ball 12 is not removed by subsequent operations.

  Next, melting and fixing of the solder balls 12 are performed by a reflow method. The carrier substrate 1 on which the solder balls 12 temporarily fixed with flux are mounted is passed through a reflow furnace. Thereby, the solder of the solder ball 12 is melted and solidified, and the solder ball 12 is attached to the BGA pad electrode 9. The flux component that has finished its role when the solder ball 12 is completely attached becomes a flux residue and adheres to the surface of the solder ball 12 and the carrier substrate 1.

  Next, the flux residue is washed and removed. The flux residue may cause dust and foreign matter, and may cause circuit contact failure and product quality degradation. For this reason, the flux residue which is an unnecessary component is washed and removed from the carrier substrate 1 to which the solder ball 12 has been attached. For this purpose, the carrier substrate is put into a cleaning apparatus using a dedicated solvent, and the flux residue is removed.

  Next, solder paste printing is performed. That is, a solder paste is supplied by screen printing on the solder bonding pad electrodes on the surface (upper surface) of the carrier substrate 1 for solder pre-coating for component mounting and lid attachment. The solder bonding pad electrode is a sealing pad electrode 6 for providing a precoat solder layer required when the component pad electrode 3 for mounting electronic components and the lid 8 are solder-bonded. The component pad electrode 3 and the sealing pad electrode 6 have different names, but the supplied solder paste is the same. The screen printing mask used in the screen printing method is provided with an opening that matches the size and position of the solder bonding pad electrode. When the squeegee moves on the upper surface of the screen printing mask set on the carrier substrate 1, printing of the solder paste on the carrier substrate 1 is completed. When the solder paste printing is finished, the screen printing mask is removed. Solder paste having a thickness of about 0.2 mm and approximately the same area as the solder bonding pad electrode is supplied.

  Next, the electronic component 2 is mounted on the component pad electrode 3 of the carrier substrate 1 printed with solder paste by a mounter (electronic component mounting machine). The mounted electronic component 2 is temporarily fixed on the component pad electrode 3 by the adhesive force of the solder paste. The electronic component 2 is soldered onto the component pad electrode 3 through a reflow process described below. At this time, since the lid 8 is not mounted, the sealing pad electrode 6 remains in a state where the solder paste is printed.

  Next, solder joining of the electronic component 2 and formation of a precoat solder layer on the sealing pad electrode 6 are performed by a reflow method. The carrier substrate 1 on which the electronic component 2 temporarily fixed with the solder paste is mounted is passed through a reflow furnace, whereby the solder is melted and solidified, and the electronic component 2 is soldered to the component pad electrode 3. At the same time, the solder is melted and solidified on the sealing pad electrode 6 to which only the solder paste is supplied, thereby forming a pre-coated solder layer having a thickness of about 0.2 mm and a short side cross-section having a kamaboko shape. Is done. The flux component in the solder paste that has finished its role at the time when the mounting of the electronic component 2 and the formation of the precoat solder layer is completed becomes a flux residue and adheres to the surface of the electronic component 2 and the carrier substrate 1.

  Next, the flux residue is washed and removed. The flux residue which is an unnecessary component is washed and removed from the carrier substrate 1 on which the electronic component 2 is attached and the precoat solder layer is formed. As in the previous solder ball attachment process, the carrier substrate 1 is put into a cleaning apparatus using a dedicated solvent for removing flux, and the residual components are removed.

Next, the semiconductor element 5 is flip-chip mounted on the flip chip pad electrode 4.
As described above, the flip chip pad electrode 4 of the carrier substrate 1 and the gold bump 15 provided on the semiconductor element pad electrode 16 are joined and aligned using the image processing function of the flip chip bonder. In general, by combining and calculating the images of both patterns captured by a television camera, they are aligned so that the deviation between them becomes the minimum value.

  The carrier substrate 1 vacuum-adsorbed on the heating stage of the flip chip bonder is maintained at a surface temperature of 150 ° C. near the flip chip pad electrode 4. Then, the back surface of the semiconductor element 5 held at room temperature is vacuum-sucked to the ultrasonic application nozzle of the flip chip bonder, and ultrasonic vibration energy of 200 mW is simultaneously applied while applying a static load of 0.6 N per bump. As a result, the gold bump 15 of the semiconductor element 5 is connected to a predetermined portion of the flip chip pad electrode 4 of the carrier substrate 1. The bonding conditions when the semiconductor element 5 is bonded to the carrier substrate 1 are different from the case where the gold bump 15 is formed on the semiconductor element 5 because the carrier substrate 1 is an organic material that softens in a high temperature environment. Because the temperature cannot be increased too much, the bonding strength is obtained by setting the load slightly higher.

  In the present embodiment, since the gold bumps 15 formed on the semiconductor element 5 are pressed against the gold-plated flip chip pad electrode 4 of the carrier substrate 1 and are joined by applying ultrasonic vibration at the same time. The gold in both the gold bump 15 and the gold-plated flip chip pad electrode 4 causes solid phase diffusion, and bonding is achieved (solid phase diffusion bonding). Thereby, good electrical connection and mechanical connection (in the shear strength measurement, a good value of 50 g / bump or more) can be obtained.

  In addition, it is possible to join by applying solid phase diffusion bonding using a method by thermocompression bonding without using the ultrasonic waves described here, but as described above, this method requires a high temperature environment, Application to resin substrates is difficult.

  Next, lid attachment is performed. A metal lid 8 is solder-sealed on the sealing pad electrode 6 to protect the semiconductor element 5 and the electronic component 2 mounted on the carrier substrate 1 and to perform electromagnetic shielding of the circuit as necessary. The The lid 8 is adsorbed by a heating tool and positioned by a positioning device, a jig or the like. Then, positioning is performed so that the bottom surface of the lid 8 is in contact with the apex portion of the kamaboko shape of the precoat solder portion of the carrier substrate 1. Subsequently, the positioned lid 8 is heated by the heating tool and raised to the melting temperature of the solder. Then, the lid 8 is pushed into the molten solder. At this time, N2 gas or the like is used, and the precoat solder is melted and solidified while the surrounding atmosphere is maintained in a low oxygen environment (approximately 100 ppm or less), so that the lid 8 and the sealing pad electrode 6 of the carrier substrate 1 are used. Are soldered together.

  This process is characterized in that the lid 8 is soldered by melting only the precoat solder in a low oxygen environment. By adopting this method, it is not necessary to supply a new solder paste or flux. For this reason, the flux residue does not remain on the surface of the carrier substrate 1 or the lid 8. Therefore, a process for cleaning and removing the residual component is not necessary, and highly reliable solder bonding is possible.

  In the vicinity of the lid 8 and the sealing pad electrode, the molten solder is supplied from the contact portion between the precoat solder and the bottom surface of the lid 8 and spreads out, so that the solder fillet 7 as shown in FIG. 1 is formed.

  As the material of the lid 8, for example, a copper material having substantially the same linear expansion coefficient as that of the resin substrate is used so as not to give mechanical stress to the resin substrate. The outer shape of the lid 8 is, for example, a square and 20 mm × 20 mm × 1.5 mm. The thickness of the lid 8 is, for example, about 0.5 mm. The lid 8 can be manufactured by machining by pressing or cutting or processing by etching.

  For example, Ni-Au plating (approx. 5 μm thick nickel plating and about 0.01 μm thick gold plating is superimposed) on the surface of the lid 8 so that soldering can be easily performed to prevent oxidation. Is given.

  By adopting the manufacturing method as described above, it is possible to provide a semiconductor device in which the mechanical strength of the joint portion is improved without significant changes in the conventional flip chip joining process.

Next, the function and effect of the semiconductor device according to the first embodiment will be described.
In the semiconductor device according to the first embodiment, the tip of the flip chip pad electrode 4 of the carrier substrate 1 is formed with a dimension that is smaller than the diameter of the gold bump in the state after the flip chip bonding. After bonding, the gold bump 15 is structured to hold the tip of the flip chip pad electrode 4.

  Further, on the upper surface of the tip portion of the flip chip pad electrode 4 of the carrier substrate, the tip of the gold bump 15 is crushed by applying a static load and ultrasonic vibration at a high temperature, and is pushed into the upper surface of the flip chip pad electrode 4. At the same time, a new surface appears on the surface of the gold bump 15 by ultrasonic vibration, and gold-gold solid phase diffusion bonding is performed.

  On the other hand, a part of gold of the gold bump 15 is deformed by the load and ultrasonic vibration at the time of bonding at the side surface portion of the tip portion of the flip chip pad electrode 4 of the carrier substrate 1, and the tip portion of the flip chip pad electrode 4 is deformed. As a result of following the shape, the gold bump 15 changes to a shape that holds the tip of the flip chip pad electrode 4, thereby generating a new restraining force. That is, a physical restraint force is newly generated by the gold bump 15 biting into the side surface portion of the tip portion of the flip chip pad electrode 4.

  That is, when the semiconductor element 5 is flip-chip bonded to the flip chip pad electrode 4 of the carrier substrate 1, the upper surface of the flip chip pad electrode 4 is fixed based on gold-gold solid phase diffusion bonding, that is, metal bonding, and flipped. The side surface of the chip pad electrode 4 is physically restricted by the biting of the gold bump 15, that is, fixed by the biting. As a result, the bonding strength is further improved.

  According to the present embodiment, the flip chip pad of a normal printed wiring board having a flat surface without providing a special anchor structure such as a needle or dendrite on the flip chip pad electrode 4 in the manufacturing process. The bonding strength can be improved by using the electrode 4.

(Embodiment 2)
FIG. 13 is an enlarged schematic cross-sectional view of a part of the semiconductor device according to the second embodiment of the present invention. Referring to FIG. 13, the semiconductor device 13 of the present embodiment is mainly different from the configuration of the first embodiment in that the upper side surface of the flip chip pad electrode 4 protrudes from the lower side. Yes. That is, the flip chip pad electrode 4 has an overhang shape.

  In the manufacturing method of the semiconductor device 13 of the present embodiment, the carrier substrate 1 manufactured by the subtractive method in which the copper-clad multilayer printed circuit board is patterned by etching is used as in the first embodiment. The pad electrode 4 is formed by etching so that the upper side of the side surface protrudes from the lower side.

  In addition, since the structure and manufacturing method other than this of this Embodiment are the same as that of Embodiment 1 mentioned above, the same code | symbol is attached | subjected about the same element and the description is abbreviate | omitted.

  According to the present embodiment, the shape and area of the upper surface of the flip chip pad electrode 4 of the carrier substrate 1 to which solid phase diffusion bonding is performed are not changed. However, since the side surface of the flip chip pad electrode 4 has an overhang shape, this embodiment has an anchor effect that the flip chip pad electrode 4 has a wedge shape. As a result, the biting force increases, so that the bonding strength increases.

(Embodiment 3)
14 (A) to 14 (C) are plan views of flip chip pad electrodes of the semiconductor device according to the third embodiment of the present invention. 14A to 14C, in the semiconductor device 13 of the present embodiment, the tip of the flip chip pad electrode 4 is branched in a plan view as compared with the configuration of the first embodiment. It differs mainly in that it has a shape. That is, the tip of the flip chip pad electrode 4 is branched and divided. Specifically, the tip shape of the flip-chip pad electrode 4 is a shape that spreads on both sides at a bifurcated branch (FIG. 14A), a shape that has the same width at a bifurcated branch (FIG. 14B), and a bifurcated branch This is the shape (FIG. 14C).

  In the manufacturing method of the semiconductor device 13 of the present embodiment, the carrier substrate 1 manufactured by the subtractive method in which the copper-clad multilayer printed circuit board is patterned by etching is used as in the first embodiment. The pad electrode 4 is formed by etching so that the tip of the pad electrode 4 has a branched shape in plan view.

  In addition, since the structure and manufacturing method other than this of this Embodiment are the same as that of Embodiment 1 mentioned above, the same code | symbol is attached | subjected about the same element and the description is abbreviate | omitted.

  According to the present embodiment, the area of the upper surface of the flip chip pad electrode 4 that contributes to flip chip bonding is increased, and the length of the biting portion on the side surface of the flip chip pad electrode 4 is increased so that the gold bump 15 is flipped. Increasing the portion that bites into the side surface of the chip pad electrode 4 can increase the bonding strength.

  Note that the shapes shown in FIGS. 14A to 14C are only examples and are not limited thereto. Of course, these shapes may be combined with the overhang shape of the second embodiment.

(Embodiment 4)
FIG. 15 is a schematic side view showing an alignment state before flip chip bonding in the fourth embodiment. 16 is an enlarged perspective view of a part of FIG. FIG. 17 is a partially enlarged view of a schematic cross-sectional view showing a state in which the semiconductor element in the semiconductor device of the fourth embodiment is bonded to the carrier substrate.

  Referring to FIGS. 15 to 17, in the semiconductor device 13 of the present embodiment, the entire upper surface and side surfaces of the tip portion of the flip chip pad electrode 4 are bonded to the gold bump 15.

  The semiconductor device 13 of the present embodiment is mainly different from the configuration of the first embodiment in that gold bumps 15 are attached upside down. This is due to a difference in the manufacturing method of the semiconductor device 13 described below.

  Compared with the manufacturing method of the first embodiment, the manufacturing method of the semiconductor device 13 of the present embodiment joins the semiconductor element 5 to the gold bump 15 after the gold bump 15 is pressed against the flip chip pad electrode 4. It is mainly different in that it further includes a process.

  In the method for manufacturing a semiconductor device according to the present embodiment, gold bumps 15 are formed on flip chip pad electrodes 4 of carrier substrate 1. In the step of forming the gold bumps 15 on the flip chip pad electrode 4 of the carrier substrate 1, first, the carrier substrate 1 is vacuum-sucked on the heating stage of the stud bump bonder. Next, the surface temperature in the vicinity of the flip chip pad electrode 4 is maintained at 150 ° C., while applying a static load of 0.6 N per bump, while simultaneously applying ultrasonic vibration energy of 250 mW, the gold bump 15 is attached to the carrier substrate 1. The flip chip pad electrode 4 is connected to a preset portion. The static load is set high to improve the biting on the flip chip pad electrode 4.

  In addition, since the structure and manufacturing method other than this of this Embodiment are the same as that of Embodiment 1 mentioned above, the same code | symbol is attached | subjected about the same element and the description is abbreviate | omitted.

  According to the present embodiment, the gold bumps 15 are formed on the flip chip pad electrode 4 of the carrier substrate 1 as is clear when FIGS. 7, 8 and 3 are compared with FIGS. 15, 16 and 17. Since the formed gold bumps 15 having a larger bottom area and can be formed one by one can be individually formed on the flip chip pad electrode 4, the flip chip pad electrode can be formed rather than a case where a plurality of gold bumps 15 are bonded simultaneously. The bonding strength of the gold bumps 15 on 4 increases.

  Furthermore, since the gold bumps 15 can be formed directly on the individual flip chip pad electrodes 4 as compared with the case where the gold bumps 15 formed on the semiconductor element pad electrode 16 are joined together, positional displacement during mounting is less likely to occur. It becomes possible to join more reliably. That is, in this method, as is apparent from FIG. 16, even if a slight misalignment occurs, the pointed portion of the gold bump 15 can be accommodated in the area of the semiconductor element pad electrode 16. Disappears.

  In addition, although gold bump was described, it is not limited to this, It can apply to the bump of the material solid-phase diffusion-bonded.

  Each embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be particularly advantageously applied to a semiconductor device having a pad electrode and a bump bonded to each other and a method for manufacturing the same.

It is a schematic sectional drawing which shows the state by which the semiconductor device in Embodiment 1 of this invention was mounted in the circuit board. 1 is a schematic perspective view of a semiconductor device according to a first embodiment of the present invention. It is an expanded sectional view which expands and shows the P section of FIG. 1 in Embodiment 1 of this invention. It is a schematic perspective view for demonstrating the semiconductor element before flip-chip joining in Embodiment 1 of this invention. FIG. 5 is a schematic plan view of the semiconductor element of FIG. 4 in the first embodiment of the present invention. FIG. 5 is a schematic side view of the semiconductor element of FIG. 4 in the first embodiment of the present invention. It is a schematic side view which shows the alignment state before flip-chip joining in Embodiment 1 of this invention. FIG. 8 is a schematic perspective view in which the vicinity of one gold bump shown in FIG. 7 in Embodiment 1 of the present invention is enlarged. It is a schematic plan view which shows the state after carrying out the flip chip joining of the semiconductor element to the carrier substrate in Embodiment 1 of this invention. FIG. 10 is a schematic plan view showing a pattern layout of flip chip pad electrodes extracted from FIG. 9 in the first embodiment of the present invention. It is a schematic plan view which shows the impression formed when the flip chip pad electrode of the carrier substrate in Embodiment 1 of this invention bites into a gold bump. It is the schematic perspective view to which a part of FIG. 11 in Embodiment 1 of this invention was expanded. It is the schematic sectional drawing to which a part of semiconductor device in Embodiment 2 of this invention was expanded. It is a schematic plan view of the flip chip pad electrode of the semiconductor device in Embodiment 3 of this invention. It is a schematic side view which shows the alignment state before flip-chip joining in this Embodiment 4. FIG. 16 is a schematic perspective view in which a part of FIG. 15 in the fourth embodiment is enlarged. FIG. 10 is a partially enlarged view of a schematic cross-sectional view showing a state where a semiconductor element in a semiconductor device according to a fourth embodiment is bonded to a carrier substrate.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Carrier substrate, 2 Electronic component, 3 Component pad electrode, 4 Flip chip pad electrode, 5 Semiconductor element, 6 Sealing pad electrode, 7 Solder fillet, 8 Lid, 9 BGA pad electrode, 10 Circuit board, 11 Circuit board pad electrode , 12 solder ball, 13 semiconductor device, 14 copper plating, 15 gold bump, 16 semiconductor element pad electrode, 17 indentation.

Claims (10)

A carrier substrate;
A pad electrode formed on the carrier substrate;
Bumps bonded on the upper and side surfaces of the pad electrode;
A semiconductor device comprising: a semiconductor element electrically connected to the pad electrode through the bump.   The semiconductor device according to claim 1, wherein the upper surface of the pad electrode and the bump are bonded by solid phase diffusion bonding.   The semiconductor device according to claim 1, wherein a width of a tip portion of the pad electrode is smaller than a diameter of the bump.   The semiconductor device according to claim 1, wherein an upper side surface of the pad electrode protrudes from a lower side.   The semiconductor device according to claim 1, wherein a tip end of the pad electrode has a shape branched in a plan view.   The semiconductor device according to claim 1, wherein the entire upper surface and side surfaces of the front end portion of the pad electrode are bonded to the pad.   The semiconductor device according to claim 1, wherein the carrier substrate is a printed circuit board using a resin material. Preparing a carrier substrate on which a pad electrode is formed;
A method of manufacturing a semiconductor device, comprising: a step of pressing a bump against the pad electrode, the bump holding a side surface of the pad electrode, and a solid phase diffusion bonding of the bump and the upper surface of the pad electrode. . Further comprising a step of forming the bump on the semiconductor element;
The method for manufacturing a semiconductor device according to claim 8, wherein the bump is pressed against the pad electrode after the bump is formed on the semiconductor element.   The method for manufacturing a semiconductor device according to claim 8, further comprising a step of bonding a semiconductor element to the bump after the bump is pressed against the pad electrode.

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