JP2001332583A - Method of mounting semiconductor chip - Google Patents
Method of mounting semiconductor chipInfo
- Publication number
- JP2001332583A JP2001332583A JP2000149783A JP2000149783A JP2001332583A JP 2001332583 A JP2001332583 A JP 2001332583A JP 2000149783 A JP2000149783 A JP 2000149783A JP 2000149783 A JP2000149783 A JP 2000149783A JP 2001332583 A JP2001332583 A JP 2001332583A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- mounting
- mounting substrate
- adhesive
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81905—Combinations of bonding methods provided for in at least two different groups from H01L2224/818 - H01L2224/81904
- H01L2224/81907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はフリップチップ法に
よってプリント基板等の実装基板に半導体チップを実装
する方法に関する。The present invention relates to a method for mounting a semiconductor chip on a mounting substrate such as a printed circuit board by a flip chip method.
【０００２】[0002]
【従来の技術】フリップチップ接続によって半導体チッ
プを実装する方法は、電子機器の小型化、軽量化、多ピ
ン化に好適に対応できる実装方法として利用されてい
る。フリップチップ接続によって半導体チップを実装す
る方法には、大別して半田バンプ接合による方法と金バ
ンプ接合による方法がある。図１０は、半田バンプ接合
によって半導体チップを搭載する従来方法を示す。実装
基板を乾燥した後、接続パッド１２に半田ペースト１４
を印刷し（図１０(a)）、ウエットバックにより接続パ
ッド１２の表面に半田１６を盛り上げ（図１０(b)）、
コイニングにより半田１６の表面を平坦化する（図１０
(c)）。次いで、実装基板１０の表面にフラックス１８
を塗布し（図１０(d)）、接続パッド１２と半田バンプ
２２とを位置合わせして半導体チップ２０を搭載する
（図１０(e))。2. Description of the Related Art A method of mounting a semiconductor chip by flip-chip connection is used as a mounting method suitable for miniaturization, weight reduction, and increase in the number of pins of electronic equipment. The method of mounting a semiconductor chip by flip-chip connection is roughly classified into a method using solder bump bonding and a method using gold bump bonding. FIG. 10 shows a conventional method for mounting a semiconductor chip by solder bump bonding. After the mounting board is dried, the solder paste 14 is applied to the connection pads 12.
(FIG. 10A), and the solder 16 is raised on the surface of the connection pad 12 by wet back (FIG. 10B).
The surface of the solder 16 is flattened by coining (FIG. 10).
(c)). Next, the flux 18 is applied to the surface of the mounting substrate 10.
Is applied (FIG. 10 (d)), and the semiconductor chip 20 is mounted by aligning the connection pads 12 with the solder bumps 22 (FIG. 10 (e)).
【０００３】図１０(f)は、リフローにより半田１６を
溶融させ半田バンプ２２を接続パッド１２に半田付けし
た状態である。実装基板１０の表面に付着しているフラ
ックス１８は、半田付け後、洗浄工程によって除去され
る（図１０(g)）。図１０(h)は、半導体チップ２０と実
装基板１０との間の隙間部分に封止用の樹脂２４を充填
し、加熱して樹脂２４を硬化させ、半田バンプ２２と接
続パッド１２との接合部を封止した状態である。これに
よって、半導体チップ２０は実装基板１０に確実に電気
的接続され接合部が封止されて実装される。FIG. 10F shows a state in which the solder 16 is melted by reflow and the solder bumps 22 are soldered to the connection pads 12. The flux 18 adhering to the surface of the mounting substrate 10 is removed by a washing step after soldering (FIG. 10 (g)). FIG. 10 (h) shows that a gap between the semiconductor chip 20 and the mounting substrate 10 is filled with a sealing resin 24, and the resin 24 is cured by heating. This is a state where the portion is sealed. As a result, the semiconductor chip 20 is reliably electrically connected to the mounting substrate 10 and the joint is sealed and mounted.
【０００４】図１１は、金バンプ接合によって半導体チ
ップを搭載する従来方法を示す。図１１(a)は、半導体
チップ２０を実装する実装基板１０である。１２が接続
パッド１２である。図１１(b)は、実装基板１０に搭載
する半導体チップ２０であり、電極に金バンプ２６が形
成されている。図１１(c)は、金バンプ２６に導電性接
着剤２８を転写して付着させた状態を示す。金バンプ接
合では導電性接着剤２８を介して金バンプ２６を実装基
板１０の接続パッド１２に接合する。図１１(d)は、金
バンプ２６と接続パッド１２とを位置合わせして、半導
体チップ２０を実装基板１０に仮接続した状態である。
図１１(e)は、半導体チップ２０と実装基板１０との間
に電気的絶縁性を有する封止用の樹脂２９を充填した状
態で、この状態で半導体チップ２０を実装基板１０に加
圧・加熱して樹脂２９を硬化させることにより、半導体
チップ２０の金バンプ２６と接続パッド１２とが互いに
当接し、半導体チップ２０と実装基板１０とが電気的に
接続され接合部が封止されて実装される。FIG. 11 shows a conventional method for mounting a semiconductor chip by gold bump bonding. FIG. 11A shows a mounting substrate 10 on which the semiconductor chip 20 is mounted. 12 is a connection pad 12. FIG. 11B shows a semiconductor chip 20 mounted on the mounting substrate 10, in which gold bumps 26 are formed on electrodes. FIG. 11C shows a state in which the conductive adhesive 28 is transferred and attached to the gold bump 26. In the gold bump bonding, the gold bump 26 is bonded to the connection pad 12 of the mounting board 10 via the conductive adhesive 28. FIG. 11D shows a state where the gold bumps 26 and the connection pads 12 are aligned and the semiconductor chip 20 is temporarily connected to the mounting substrate 10.
FIG. 11E shows a state in which a sealing resin 29 having electrical insulation properties is filled between the semiconductor chip 20 and the mounting substrate 10. In this state, the semiconductor chip 20 is pressed onto the mounting substrate 10. By heating and curing the resin 29, the gold bumps 26 of the semiconductor chip 20 and the connection pads 12 come into contact with each other, the semiconductor chip 20 and the mounting substrate 10 are electrically connected, and the joint is sealed and mounted. Is done.
【０００５】[0005]
【発明が解決しようとする課題】ところで、上述した半
田バンプ接合によって半導体チップを実装する方法で
は、半導体チップの半田バンプを接続パッドに接合する
工程と、半田バンプを接続パッドに接合した後、半導体
チップと実装基板との間の隙間部分を樹脂によって封止
する工程とは別工程になっている。したがって、各々専
用設備が必要であり、また各々の処理工程を経ることか
ら処理工程時間が長くなる。また、半田接合するために
半田付け用のフラックスを使用するから、半田バンプを
接続パッドに接合した後、フラックスを洗浄する必要が
ある。この洗浄工程では、半導体チップと実装基板との
間の狭い隙間部分を洗浄するため、特殊な洗浄剤を使用
したり特殊な設備を使用したりすることが必要であり、
製造コストが上がる原因となる。また、洗浄時に実装基
板を損傷させるといったことがあることから、洗浄を行
うことは製品の信頼性を高める上で好ましくないという
問題がある。In the above-described method of mounting a semiconductor chip by solder bump bonding, the method of bonding the solder bumps of the semiconductor chip to the connection pads, and the steps of bonding the solder bumps to the connection pads, This is a separate step from the step of sealing the gap between the chip and the mounting board with resin. Therefore, a dedicated facility is required for each, and each processing step requires a long processing time. In addition, since a soldering flux is used for soldering, it is necessary to wash the flux after joining the solder bumps to the connection pads. In this cleaning process, it is necessary to use a special cleaning agent or special equipment to clean the narrow gap between the semiconductor chip and the mounting board,
This causes an increase in manufacturing cost. In addition, since the mounting substrate may be damaged during cleaning, there is a problem that cleaning is not preferable in terms of improving the reliability of the product.
【０００６】また、半田バンプ接合及び金バンプ接合
で、半導体チップと実装基板との間の隙間部分に充填し
た樹脂を硬化させる場合、通常の工程では１〜２時間程
度加熱する必要がある。したがって、インラインによる
大量生産には不適でバッチ処理によらざるを得ず、生産
性が上がらない。また、半導体チップと実装基板との間
の隙間部分に樹脂材を充填する場合も１分程度の時間が
かかったりし、製造工程全体として処理工程時間が長く
かかるという問題がある。また、金バンプ接合による場
合では、常温で半導体チップを実装すると、封止用の樹
脂材が硬いことから、バンプ先端の不必要な潰れ等によ
ってバンプと接続パッドとの電気的接続が不安定になる
といった問題もあった。In the case of curing the resin filled in the gap between the semiconductor chip and the mounting board by solder bump bonding and gold bump bonding, it is necessary to heat for about 1 to 2 hours in a usual process. Therefore, it is not suitable for in-line mass production, and must be performed by batch processing, and productivity cannot be improved. In addition, it takes about one minute to fill the gap between the semiconductor chip and the mounting board with the resin material, and there is a problem that it takes a long processing time as a whole manufacturing process. Also, in the case of gold bump bonding, when the semiconductor chip is mounted at room temperature, the sealing resin material is hard, and the electrical connection between the bump and the connection pad becomes unstable due to unnecessary collapse of the tip of the bump. There was also the problem of becoming.
【０００７】本発明は、これらの問題点を解消すべくな
されたものであり、その目的とするところは、フリップ
チップ接続によって半導体チップを実装する工程を簡易
化して生産性を向上させ、これによって半導体チップを
実装するコストを引き下げることができるとともに、半
導体チップの実装信頼性を高めることができる半導体チ
ップの実装方法を提供するにある。The present invention has been made to solve these problems, and an object of the present invention is to improve the productivity by simplifying a process of mounting a semiconductor chip by flip chip connection. It is an object of the present invention to provide a semiconductor chip mounting method capable of reducing the cost of mounting a semiconductor chip and improving the mounting reliability of the semiconductor chip.
【０００８】[0008]
【課題を解決するための手段】本発明は、上記目的を達
成するため、次の構成を備える。すなわち、半導体チッ
プをフリップチップ接続により実装基板に実装する半導
体チップの実装方法において、実装基板の前記半導体チ
ップの実装面に、半導体チップを実装基板に接着した際
に半導体チップバンプと実装基板の接続パッドとの接合
部を封止する接着剤を被着し、該実装基板の接着剤が被
着された面に、前記バンプと前記接続パッドとを位置合
わせして半導体チップを加圧して搭載し、リフローによ
り前記接着剤を硬化させて前記半導体チップと実装基板
との間を封止して接合するとともに、前記バンプと前記
接続パッドとを接続することを特徴とする。The present invention has the following configuration to achieve the above object. That is, in a semiconductor chip mounting method of mounting a semiconductor chip on a mounting board by flip-chip connection, when the semiconductor chip is bonded to the mounting board on the mounting surface of the semiconductor chip of the mounting board, the connection between the semiconductor chip bump and the mounting board is performed. An adhesive for sealing a bonding portion with the pad is applied, and the semiconductor chip is mounted by pressing the semiconductor chip by aligning the bump and the connection pad on the surface of the mounting substrate on which the adhesive is applied. Curing the adhesive by reflow to seal and join the semiconductor chip and the mounting substrate, and connect the bump and the connection pad.
【０００９】また、前記実装基板に半導体チップを加圧
して前記実装基板に半導体チップを搭載する際に、前記
実装基板に被着された接着剤を加熱して接着剤の粘度を
低下させ、半導体チップの搭載領域から接着剤を押し出
して、前記バンプと接続パッドとを直接接触させること
を特徴とする。接着剤の粘度を下げることによって半導
体チップを加圧した際に余分の接着剤が半導体チップの
搭載領域の外に押し出されて、半導体チップと実装基板
との確実な電気的接続と、確実な封止がなされる。ま
た、接着剤を半導体チップの搭載領域から押し出した際
に、半導体チップの側面と実装基板との間にフィレット
を形成することを特徴とする。接着剤を加熱して流動性
を高めることによって、半導体チップの側面と実装基板
との間にフィレットた形成される。フィレットを形成す
ることによって接着剤の濡れ力が半導体チップを実装基
板に引き込むように作用し、半導体チップの位置ずれを
防止して半導体チップと実装基板との接続を確実にする
ことができる。また、前記実装基板に被着する樹脂剤と
して、ロジン等の固形分を含まず、活性剤及び硬化促進
剤として、アミンまたはカルボン酸等の酸無水物を含む
樹脂剤を使用することによって、接続パッドの酸化膜が
還元され、バンプと接続パッドとの電気的接続を確実に
することができる。Further, when the semiconductor chip is mounted on the mounting substrate by pressing the semiconductor chip on the mounting substrate, the adhesive applied to the mounting substrate is heated to lower the viscosity of the adhesive. An adhesive is extruded from a chip mounting area to bring the bumps and the connection pads into direct contact. When the pressure of the semiconductor chip is reduced by lowering the viscosity of the adhesive, the excess adhesive is pushed out of the mounting area of the semiconductor chip, thereby ensuring a reliable electrical connection between the semiconductor chip and the mounting board and a reliable sealing. A stop is made. Further, when the adhesive is extruded from the mounting area of the semiconductor chip, a fillet is formed between the side surface of the semiconductor chip and the mounting substrate. By heating the adhesive to increase the fluidity, a fillet is formed between the side surface of the semiconductor chip and the mounting substrate. By forming the fillet, the wetting force of the adhesive acts to draw the semiconductor chip into the mounting substrate, preventing the semiconductor chip from being displaced and ensuring the connection between the semiconductor chip and the mounting substrate. In addition, as a resin agent to be adhered to the mounting substrate, a solid agent such as rosin is not included, and a resin agent including an acid anhydride such as an amine or a carboxylic acid is used as an activator and a curing accelerator, thereby making connection. The oxide film of the pad is reduced, and electrical connection between the bump and the connection pad can be ensured.
【００１０】また、前記半導体チップが、錫−鉛の共晶
半田もしくは該共晶半田よりも低温の融点を有する半田
合金によりバンプが形成され、前記樹脂剤が、エポキシ
系樹脂を主成分とするものであることを特徴とする。共
晶半田によってバンプを形成し、エポキシ系樹脂を主成
分とする接着剤を用いて実装することによって、リフロ
ー工程での昇温速度を制御することにより半田を溶融さ
せた後、半田の溶融温度以下に降温させ、半田を固化さ
せた後、接着剤を硬化させることができる。また、半導
体チップを実装基板に加圧して搭載した状態で、半田融
点温度以下に加熱することによりバンプと接続パッドと
の間に合金層を形成してバンプと接続パッドとを仮接続
した後、リフローすることにより、半田バンプと接続パ
ッドとの電気的接続を確実にして実装することができ
る。また、半導体チップを実装基板に加圧して搭載する
際に、半導体チップの加圧力によってバンプをつぶして
若干扁平に形成し、リフローの際にバンプが球形に戻る
作用を利用してバンプと接続パッドとを接合することに
より、リフローの際に半田バンプと接続パッドとの接続
を確実にすることができる。Further, the semiconductor chip has bumps formed of a eutectic solder of tin-lead or a solder alloy having a melting point lower than that of the eutectic solder, and the resin agent is mainly composed of an epoxy resin. Characterized in that: After forming a bump with eutectic solder and mounting it with an adhesive mainly composed of epoxy resin, the solder is melted by controlling the rate of temperature rise in the reflow process and then the melting temperature of the solder After lowering the temperature and solidifying the solder, the adhesive can be cured. Also, after the semiconductor chip is mounted on the mounting substrate under pressure, the alloy layer is formed between the bump and the connection pad by heating the solder chip below the melting point, and the bump and the connection pad are temporarily connected. By performing the reflow, the electrical connection between the solder bumps and the connection pads can be reliably performed and the mounting can be performed. Also, when the semiconductor chip is mounted on the mounting substrate by pressing, the bumps are crushed by the pressure of the semiconductor chip to form a slightly flat shape, and the bumps and the connection pads are used by utilizing the effect that the bumps return to a spherical shape during reflow. Is bonded, the connection between the solder bumps and the connection pads can be ensured during reflow.
【００１１】また、前記半導体チップが、金バンプによ
りバンプが形成されたものであることを特徴とする。半
導体チップのバンプが金バンプの場合も、上述したと同
様の方法によって、金バンプと接続パッドとの接続およ
び半導体チップと実装基板との接合部を封止して実装す
ることができる。また、前記実装基板の接続パッドの表
面にあらかじめ金めっきを施し、半導体チップを実装基
板に加圧して搭載した際に、金−金結合によりバンプと
接続パッドとを仮接続した後、リフローすることによ
り、金バンプと接続パッドとの接続をより確実に行うこ
とが可能になる。Further, the semiconductor chip is characterized in that bumps are formed by gold bumps. Also in the case where the bump of the semiconductor chip is a gold bump, the connection between the gold bump and the connection pad and the joint between the semiconductor chip and the mounting substrate can be sealed and mounted by the same method as described above. In addition, the surface of the connection pad of the mounting board is subjected to gold plating in advance, and when the semiconductor chip is mounted on the mounting board by pressing, the bump and the connection pad are temporarily connected by gold-gold bonding and then reflowed. Accordingly, the connection between the gold bump and the connection pad can be more reliably performed.
【００１２】[0012]
【発明の実施の形態】以下、本発明の好適な実施形態に
ついて、添付図面と共に詳細に説明する。図１(a)は、
半田バンプ接合により半導体チップを実装基板にフリッ
プチップ接続する本発明方法による処理工程図である。
図１(b)は比較例として従来の半田バンプ接合により半
導体チップを実装基板にフリップチップ接続する処理工
程図を示す。本発明に係る半導体チップの実装方法は、
基板に接着剤を塗布し、半導体チップを基板に搭載し、
リフローにより半導体チップを基板に接合するという主
要な３工程によって実装することを特徴とする。以下
で、この処理工程によって半導体チップを実装する実施
形態について説明する。Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 (a)
FIG. 4 is a process diagram according to the method of the present invention for flip-chip connecting a semiconductor chip to a mounting board by solder bump bonding.
FIG. 1B shows a process of flip chip connecting a semiconductor chip to a mounting substrate by conventional solder bump bonding as a comparative example. The method for mounting a semiconductor chip according to the present invention includes:
Apply adhesive to the board, mount the semiconductor chip on the board,
It is characterized in that it is mounted by three main steps of joining a semiconductor chip to a substrate by reflow. Hereinafter, an embodiment in which a semiconductor chip is mounted by this processing step will be described.
【００１３】図２は、ビルドアップ法によって形成した
実装基板１０に、電極に半田バンプ２２を形成した半導
体チップ２０を搭載する実施形態を示す説明図である。
半田バンプ２２は共晶合金半田（融点１８３℃）によっ
て形成している。図２(a)は、半導体チップ２０を実装
する実装基板１０である。実装基板１０の表面には半導
体チップ２０の半田バンプ２２と一致する配置で、銅め
っきにより所定パターンに形成された接続パッド１２が
形成されている。なお、半導体チップ２０を実装する基
板にはビルドアップ法に限らず種々の製法、材質による
基板が使用できる。実装基板１０は、半導体チップ２０
を実装基板１０に接合して樹脂封止する部位にボイドが
生じる原因となる吸着水分を除去するため、あらかじめ
加熱して乾燥処理が施される。FIG. 2 is an explanatory view showing an embodiment in which a semiconductor chip 20 having solder bumps 22 formed on electrodes is mounted on a mounting substrate 10 formed by a build-up method.
The solder bumps 22 are formed by eutectic alloy solder (melting point: 183 ° C.). FIG. 2A shows a mounting substrate 10 on which the semiconductor chip 20 is mounted. Connection pads 12 formed in a predetermined pattern by copper plating are formed on the surface of the mounting substrate 10 in an arrangement corresponding to the solder bumps 22 of the semiconductor chip 20. The substrate on which the semiconductor chip 20 is mounted is not limited to the build-up method, but may be a substrate made of various manufacturing methods and materials. The mounting substrate 10 includes a semiconductor chip 20
Is heated and dried in advance in order to remove the adsorbed moisture that causes voids in a portion to be bonded to the mounting substrate 10 and sealed with a resin.
【００１４】図２(b)は、実装基板１０の半導体チップ
２０を搭載する面を接着剤３０によって被着した状態で
ある。接着剤３０は、半導体チップ２０を実装基板１０
に接着して固定するとともに半導体チップ２０を実装基
板１０に搭載した領域を封止する作用を有し、半導体チ
ップ２０を実装基板１０に確実に接合固定することによ
って半導体チップ２０の半田バンプ２２と実装基板１０
の接続パッド１２とを確実に電気的に接続する。FIG. 2B shows a state in which the surface of the mounting substrate 10 on which the semiconductor chip 20 is mounted is adhered by the adhesive 30. The adhesive 30 attaches the semiconductor chip 20 to the mounting substrate 10.
And has a function of sealing a region where the semiconductor chip 20 is mounted on the mounting substrate 10, and securely joins and fixes the semiconductor chip 20 to the mounting substrate 10, so that the solder bumps 22 of the semiconductor chip 20 Mounting board 10
Is reliably electrically connected to the connection pad 12.
【００１５】接着剤３０によって実装基板１０の実装面
を被着する場合は、実装基板１０を加熱して接着剤３０
が最軟化する直前の温度に加熱して行う。最軟化する直
前の温度とは、接着剤３０が流動化する直前の温度の意
味である。本発明方法では、実装基板１０の実装面を接
着剤３０によって被覆した状態で半導体チップ２０を実
装基板１０に加圧して搭載する。したがって、接着剤３
０は半導体チップ２０を実装基板１０に対して加圧した
際に、余分の接着剤３０が半導体チップ２０と実装基板
１０との間から外に押し出されるようにする必要があ
る。半導体チップ２０を実装基板１０に加圧して搭載す
る際には、接着剤３０がある程度流動性をもった状態で
行うが、実装基板１０の実装面を接着剤３０によって被
着する際には、事前に実装基板１０を加熱して接着剤３
０を軟化させる状態で行う。When the mounting surface of the mounting substrate 10 is adhered by the adhesive 30, the mounting substrate 10 is heated to
Is heated to a temperature immediately before the softening of the resin. The temperature immediately before softening means the temperature immediately before the adhesive 30 fluidizes. In the method of the present invention, the semiconductor chip 20 is mounted on the mounting substrate 10 by applying pressure while the mounting surface of the mounting substrate 10 is covered with the adhesive 30. Therefore, the adhesive 3
It is necessary that when the semiconductor chip 20 is pressed against the mounting substrate 10, the extra adhesive 30 is pushed out from between the semiconductor chip 20 and the mounting substrate 10. When the semiconductor chip 20 is mounted on the mounting substrate 10 by pressing, the adhesive 30 is carried out with a certain degree of fluidity, but when the mounting surface of the mounting substrate 10 is applied with the adhesive 30, The mounting substrate 10 is heated in advance and the adhesive 3
This is performed in a state where 0 is softened.
【００１６】接着剤３０の特性にもよるが、エポキシ系
接着剤を使用する場合は、実装基板１０を８０℃程度に
加熱しておくことによって接着剤３０は軟化する。接着
剤３０は半導体チップ２０を実装基板１０に接着した際
に、半導体チップ２０と実装基板１０との間を封止する
から、封止に必要な厚さに被着する。接着剤３０を実装
基板１０に被着するには、接着剤３０を実装基板１０の
表面にコーティングしてもよいし、シート状の接着剤３
０で実装基板１０の表面を被着してもよい。シート状の
接着剤３０であっても実装基板１０を加熱しておくこと
によって十分に軟化させることができる。シート状の接
着剤３０の場合は、接着剤３０を所要の厚さに確実にコ
ントロールできるという利点がある。Although it depends on the characteristics of the adhesive 30, when the epoxy adhesive is used, the adhesive 30 is softened by heating the mounting substrate 10 to about 80.degree. The adhesive 30 seals the gap between the semiconductor chip 20 and the mounting substrate 10 when the semiconductor chip 20 is bonded to the mounting substrate 10, so that the adhesive 30 is applied to a thickness necessary for sealing. In order to apply the adhesive 30 to the mounting substrate 10, the adhesive 30 may be coated on the surface of the mounting substrate 10, or the sheet-like adhesive 3
0 may be applied to the surface of the mounting substrate 10. Even the sheet-like adhesive 30 can be sufficiently softened by heating the mounting substrate 10. In the case of the sheet-like adhesive 30, there is an advantage that the adhesive 30 can be reliably controlled to a required thickness.
【００１７】図２(c)は、半導体チップ２０を実装基板
１０に加圧している状態を示す。接着剤３０は加熱され
て軟化しているから、半導体チップ２０を実装基板１０
に押圧すると接着剤３０が流動して余分の接着剤３０が
半導体チップ２０の下側から外側に押し出される。接着
剤３０の粘度が固いと接着剤３０を押し出す圧力が高く
なり、押し出された接着剤３０が安定するまでに時間が
かかり、場合によっては半田バンプ２２と接続パッド１
２との間に接着剤３０が残ってしまったり、半田バンプ
２２と接続パッド１２との間から押し出された接着剤３
０が反力によって再度半田バンプ２２と接続パッド１２
との間に戻ってしまったりする。FIG. 2C shows a state in which the semiconductor chip 20 is pressed against the mounting substrate 10. Since the adhesive 30 is heated and softened, the semiconductor chip 20 is mounted on the mounting substrate 10.
, The adhesive 30 flows and the excess adhesive 30 is pushed outward from the lower side of the semiconductor chip 20. If the viscosity of the adhesive 30 is high, the pressure for pushing out the adhesive 30 increases, and it takes time for the extruded adhesive 30 to stabilize, and in some cases, the solder bumps 22 and the connection pads 1
2 or the adhesive 3 extruded from between the solder bumps 22 and the connection pads 12.
0 is the solder bump 22 and the connection pad 12 again due to the reaction force.
Or return between.
【００１８】したがって、半導体チップ２０を実装基板
１０に加圧して搭載する際には、さらに加熱して接着剤
３０に流動性をもたせた状態で行うようにする。接着剤
３０に流動性をもたせると、半導体チップ２０の側面に
押し出された接着剤３０は、半導体チップ２０の側面と
実装基板１０との間でフィレットを形成するようにな
る。図３(a)は、半導体チップ２０と実装基板１０との
間にフィレットＡが形成された状態を示す。一方、図３
(b)は、接着剤３０の流動性が不十分のため、半導体チ
ップ２０の側面に押し出された接着剤３０が、半導体チ
ップ２０の側面で盛り上がったままフィレットが形成さ
れていない状態を示す。図３(a)に示すように、半導体
チップ２０の側面と実装基板１０との間にフィレットが
形成されると、図の矢印のように接着剤３０は半導体チ
ップ２０を実装基板１０に向けて引き込むように作用
し、半導体チップ２０が実装基板１０に押しつけられる
ようになる。これに対して、フィレットが形成されない
と、図３(b)に示すように、接着剤３０は半導体チップ
２０を押し上げるように作用し、半導体チップ２０が実
装基板１０に押しつける力が作用しなくなる。Therefore, when the semiconductor chip 20 is mounted on the mounting substrate 10 by applying pressure, the semiconductor chip 20 is heated further so that the adhesive 30 has fluidity. When the adhesive 30 has fluidity, the adhesive 30 extruded on the side surface of the semiconductor chip 20 forms a fillet between the side surface of the semiconductor chip 20 and the mounting substrate 10. FIG. 3A shows a state in which a fillet A is formed between the semiconductor chip 20 and the mounting substrate 10. On the other hand, FIG.
FIG. 3B shows a state in which the fillet is not formed while the adhesive 30 extruded on the side surface of the semiconductor chip 20 is raised on the side surface of the semiconductor chip 20 because the fluidity of the adhesive 30 is insufficient. As shown in FIG. 3A, when a fillet is formed between the side surface of the semiconductor chip 20 and the mounting substrate 10, the adhesive 30 directs the semiconductor chip 20 toward the mounting substrate 10 as shown by the arrow in the figure. The semiconductor chip 20 acts so as to be pulled in, and the semiconductor chip 20 is pressed against the mounting substrate 10. On the other hand, if the fillet is not formed, as shown in FIG. 3B, the adhesive 30 acts to push up the semiconductor chip 20, and the force for pressing the semiconductor chip 20 against the mounting substrate 10 does not act.
【００１９】エポキシ系の接着剤の場合は９０℃程度に
加熱すると流動性が得られるから、この状態で半導体チ
ップ２０を実装基板１０に加圧して実装基板１０に半導
体チップ２０を搭載する。半導体チップ２０を加圧して
５秒間程度保持することで、半導体チップ２０の側面か
ら押し出された接着剤３０が半導体チップ２０と実装基
板１０との間でフィレットが形成され、半導体チップ２
０は接着剤３０の濡れ力によって実装基板１０に押さえ
つけられた状態となる（図２(d)）。なお、半導体チッ
プ２０を実装基板１０に加圧すると、その際の荷重によ
って実装基板１０がたわみ、半田バンプ２２が若干つぶ
れて扁平になる。図４(a)は、実装基板１０がたわみ、
半田バンプ２２がつぶれた状態を説明的に示す。Ｐが接
続パッド１２のたわみ量、Ｂが半田バンプ２２の潰れ量
である。この状態で半導体チップ２０に加えた荷重を解
放すると、弾性変形分が復元し、反力によって半導体チ
ップ２０の半田バンプ２２と接続パッド１２とが僅かに
離間する。図４(b)は、半導体チップ２０の加圧を解除
して半田バンプ２２と接続パッド１２とが離間した状態
を示す。In the case of an epoxy adhesive, fluidity can be obtained by heating to about 90 ° C. In this state, the semiconductor chip 20 is pressed onto the mounting substrate 10 and the semiconductor chip 20 is mounted on the mounting substrate 10. By pressing and holding the semiconductor chip 20 for about 5 seconds, the adhesive 30 extruded from the side surface of the semiconductor chip 20 forms a fillet between the semiconductor chip 20 and the mounting substrate 10, and the semiconductor chip 2
Reference numeral 0 indicates a state in which the adhesive 30 is pressed against the mounting substrate 10 by the wetting force of the adhesive 30 (FIG. 2D). When the semiconductor chip 20 is pressed against the mounting substrate 10, the mounting substrate 10 is bent by the load at that time, and the solder bumps 22 are slightly crushed and flattened. FIG. 4A shows that the mounting substrate 10 is bent,
A state in which the solder bumps 22 are crushed is illustratively shown. P is the amount of deflection of the connection pad 12, and B is the amount of collapse of the solder bump 22. When the load applied to the semiconductor chip 20 is released in this state, the elastic deformation is restored, and the solder bumps 22 of the semiconductor chip 20 and the connection pads 12 are slightly separated by the reaction force. FIG. 4B shows a state in which the pressure on the semiconductor chip 20 is released and the solder bumps 22 and the connection pads 12 are separated.
【００２０】半田バンプ２２と接続パッド１２との離間
量は数μｍ程度であるが、半田バンプ２２と接続パッド
１２との離間間隔は、半田バンプ２２の大きさのばらつ
きによっても変動する。半導体チップ２０を実装基板１
０に搭載する際に、加圧して半田バンプ２２をつぶすよ
うにしているのは、半田バンプ２２を扁平にすることで
半田バンプ２２の高さのばらつきを小さくすることと、
次工程で半田バンプ２２を溶融して半田バンプ２２を接
続パッド１２に接合する際に、半田バンプ２２を確実に
接続パッド１２に接触させるようにする意味がある。The distance between the solder bumps 22 and the connection pads 12 is on the order of a few μm, but the distance between the solder bumps 22 and the connection pads 12 also varies due to variations in the size of the solder bumps 22. Mounting the semiconductor chip 20 on the mounting substrate 1
The reason why the solder bumps 22 are crushed by applying pressure when mounted on the solder bumps 0 is to reduce the variation in height of the solder bumps 22 by flattening the solder bumps 22.
When the solder bumps 22 are melted in the next step to join the solder bumps 22 to the connection pads 12, it is important to ensure that the solder bumps 22 come into contact with the connection pads 12.
【００２１】すなわち、扁平につぶされた半田バンプ２
２が溶融されると、表面張力の作用により半田バンプ２
２は球形に戻ろうとする。その結果、図５に示すよう
に、半田バンプ２２が扁平状態で接続パッド１２から浮
き量Ｃで離間していたとしても、半田バンプ２２が球形
になることによって半田バンプ２２の高さが高くなり接
続パッド１２に接するようになる。半田バンプ２２が接
続パッド１２に接触すれば、半田バンプ２２の濡れ性に
よって半田バンプ２２と接続パッド１２は相互に引き合
って半田バンプ２２と接続パッド１２とは確実に半田接
合される。That is, the flattened solder bumps 2
When the solder bump 2 is melted, the solder bump 2
2 tries to return to a spherical shape. As a result, as shown in FIG. 5, even if the solder bump 22 is separated from the connection pad 12 by a floating amount C in a flat state, the height of the solder bump 22 increases due to the spherical shape of the solder bump 22. It comes into contact with the connection pad 12. When the solder bump 22 contacts the connection pad 12, the solder bump 22 and the connection pad 12 attract each other due to the wettability of the solder bump 22, and the solder bump 22 and the connection pad 12 are securely soldered.
【００２２】なお、半導体チップ２０を実装基板１０に
搭載する際の加圧操作で半田バンプ２２をつぶすことが
難しい場合には、半導体チップ２０に半田バンプ２２を
形成した際に、あらかじめ半田バンプ２２を扁平につぶ
しておいても良い。なお、半田バンプ２２をつぶして扁
平に形成するのは、半田バンプ２２を溶融した際に半田
バンプ２２を接続パッド１２に接合させやすくするため
であり、実際にはさほど大きくつぶす必要はない。If it is difficult to crush the solder bumps 22 by a pressing operation when the semiconductor chip 20 is mounted on the mounting substrate 10, when the solder bumps 22 are formed on the semiconductor chip 20, May be crushed flat. The reason why the solder bumps 22 are flattened by being crushed is to make it easier to bond the solder bumps 22 to the connection pads 12 when the solder bumps 22 are melted, and it is not actually necessary to crush the solder bumps 22 so much.
【００２３】半導体チップ２０を実装基板１０に加圧し
て搭載した際に、上記のように半田バンプ２２と接続パ
ッド１２とが離間する可能性があることを防止する方法
としては、半導体チップ２０を実装基板１０に加圧して
接着剤３０を介して搭載した際に、半田バンプ２２を接
続パッド１２に仮接続し、その後に半田バンプ２２を溶
融して本接続する方法がある。仮接続は、半導体チップ
２０を実装基板１０に加圧して搭載した状態で半田バン
プ２２が溶融する直前の温度程度まで昇温させることに
より、半田バンプ２２と接続パッド１２の界面で半田と
銅が一部拡散して合金層を形成し、半田バンプ２２と接
続パッド１２とを接続させる操作である。共晶半田を用
いた半田バンプ２２の溶融温度は１８３℃であり、この
場合は１７５℃程度に昇温させることによって仮接続す
ることができる。As a method for preventing the possibility that the solder bumps 22 and the connection pads 12 are separated from each other when the semiconductor chip 20 is mounted on the mounting board 10 by pressing as described above, the semiconductor chip 20 is There is a method of temporarily connecting the solder bumps 22 to the connection pads 12 when the semiconductor device is mounted on the mounting substrate 10 by applying pressure and via the adhesive 30, and then melting the solder bumps 22 to make the actual connection. The temporary connection is performed by heating the semiconductor chip 20 to a temperature immediately before the solder bump 22 is melted in a state where the semiconductor chip 20 is mounted on the mounting substrate 10 by pressing, so that solder and copper are formed at the interface between the solder bump 22 and the connection pad 12. This is an operation of partially diffusing to form an alloy layer and connecting the solder bumps 22 and the connection pads 12. The melting temperature of the solder bumps 22 using the eutectic solder is 183 ° C. In this case, the solder bumps 22 can be temporarily connected by raising the temperature to about 175 ° C.
【００２４】半田バンプ２２と接続パッド１２とを仮接
続する方法による場合は、半導体チップ２０を実装基板
１０に搭載した後、本接続する際に半田バンプ２２と接
続パッド１２との間に接着剤３０が流れ込んで未接続に
なることを防止することができる。もちろん、この仮接
続の場合には、接着剤３０が硬化しない条件が必要であ
る。逆にいえば、接着剤３０はこのような温度条件では
硬化しないものを選択することになる。In the case where the method of temporarily connecting the solder bumps 22 and the connection pads 12 is employed, after the semiconductor chip 20 is mounted on the mounting board 10, an adhesive is provided between the solder bumps 22 and the connection pads 12 when the actual connection is made. 30 can be prevented from flowing and becoming unconnected. Of course, in the case of the temporary connection, a condition that the adhesive 30 is not cured is necessary. Conversely, the adhesive 30 that does not cure under such temperature conditions is selected.
【００２５】上記のようにして半導体チップ２０を接着
剤３０を介して実装基板１０に搭載した後、リフローに
より半田バンプ２２を溶融することにより半田バンプ２
２と接続パッド１２とを半田接合し、次いで、接着剤３
０を硬化させて半導体チップ２０を実装基板１０に実装
する。リフロー工程では、半田バンプ２２を先に溶融
し、次いで接着剤３０を硬化させるようにする。このた
め、なるべく短時間のうちに半田が溶融する温度まで上
昇させ、接着剤３０が硬化開始する前に半田の溶融を終
わらせるようにする。昇温速度を速くすると、接着剤３
０は硬化が開始する前に液状の状態で半田を溶融させる
ことができる。After the semiconductor chip 20 is mounted on the mounting board 10 via the adhesive 30 as described above, the solder bumps 22 are melted by reflow to form the solder bumps 2.
2 and the connection pads 12 are soldered, and then the adhesive 3
Then, the semiconductor chip 20 is mounted on the mounting substrate 10 by curing 0. In the reflow step, the solder bumps 22 are melted first, and then the adhesive 30 is cured. For this reason, the temperature is raised to a temperature at which the solder melts in as short a time as possible, and the melting of the solder is completed before the adhesive 30 starts to harden. When the heating rate is increased, the adhesive 3
0 means that the solder can be melted in a liquid state before curing starts.
【００２６】図６は、リフロー工程における温度設定条
件のプロファイルを示したものである。リフロー工程で
は、まず、急速に半田の溶融温度以上にまで昇温させ
る。実施形態では、２℃／秒程度の昇温速度で、２１０
℃程度まで一気に昇温して半田バンプ２２を溶融させ、
半田バンプ２２が溶融した後、１６０℃まで降温させて
半田を固化させるとともに、加熱を保持することによっ
て接着剤３０を硬化させた。半田バンプ２２を溶融させ
た後は、半田の溶融温度以下で接着剤３０が硬化する温
度を継続させて接着剤３０を完全に硬化させるためであ
る。実施形態では、接着剤３０に硬化促進剤を加えるこ
とによって約３００秒の加熱時間で接着剤３０を硬化さ
せることができた。FIG. 6 shows a profile of a temperature setting condition in the reflow process. In the reflow process, first, the temperature is rapidly raised to a temperature equal to or higher than the melting temperature of the solder. In the embodiment, at a heating rate of about 2 ° C./sec.
The temperature is raised to about ℃ at a stretch to melt the solder bumps 22,
After the solder bumps 22 were melted, the temperature was lowered to 160 ° C. to solidify the solder, and the adhesive 30 was cured by holding the heating. This is because, after the solder bumps 22 are melted, the temperature at which the adhesive 30 cures below the melting temperature of the solder is continued to completely cure the adhesive 30. In the embodiment, the adhesive 30 can be cured in a heating time of about 300 seconds by adding the curing accelerator to the adhesive 30.
【００２７】リフロー工程では、半田を先に溶融させる
ことによって半田バンプ２２と接続パッド１２とが半田
接合され、半導体チップ２０と実装基板１０との電気的
接続が確実になされる。図２(e)は、半導体チップ２０
が実装基板１０に実装された状態である。半田がメニス
カス状となって接続パッド１２と半導体チップ２０の電
極とを接合している。球状の半田が接続パッド１２に濡
れることで半導体チップ２０と接続パッド１２との間で
半田が引き合って確実に半田接合される。また、接着剤
３０が次いで完全硬化することによって半導体チップ２
０を実装基板１０に確実に接合する。接着剤３０は硬化
の際に収縮して半導体チップ２０と実装基板１０が引き
合い、この点からも半導体チップ２０と実装基板１０と
の電気的接続が確実になされることになる。In the reflow step, the solder bumps 22 and the connection pads 12 are soldered by melting the solder first, and the electrical connection between the semiconductor chip 20 and the mounting board 10 is ensured. FIG. 2E shows the semiconductor chip 20.
Are mounted on the mounting board 10. The solder has a meniscus shape and joins the connection pad 12 and the electrode of the semiconductor chip 20. When the spherical solder wets the connection pad 12, the solder is attracted between the semiconductor chip 20 and the connection pad 12, and the solder is surely joined. Further, the semiconductor chip 2 is completely cured after the adhesive 30 is completely cured.
0 is securely bonded to the mounting substrate 10. The adhesive 30 shrinks during curing, and the semiconductor chip 20 and the mounting substrate 10 are attracted to each other. This also ensures that the semiconductor chip 20 and the mounting substrate 10 are electrically connected.
【００２８】本実施形態の半導体チップの実装方法で
は、リフロー工程によって半田バンプ２２と実装基板１
０の接続パッド１２とが一括して半田接合され、続け
て、加熱することによって接着剤３０が硬化して半導体
チップ２０が実装基板１０に固定され、半導体チップ２
０と実装基板１０との接合部が封止されて実装される。
本実施形態では、リフロー後に半田フラックスを洗浄す
る必要がなく、封止用の樹脂をアンダーフィルすること
も必要ない。これによって、きわめて効率的に半導体チ
ップをフリップチップ接続することが可能になる。図１
(a)、(b)を比較対照すれば、本実施形態の半導体チップ
の実装方法が従来方法にくらべてはるかに簡易な製造工
程によっていることがわかる。In the semiconductor chip mounting method according to the present embodiment, the solder bumps 22 and the mounting
0 and the connection pads 12 are collectively solder-bonded, and subsequently, the adhesive 30 is cured by heating and the semiconductor chip 20 is fixed to the mounting substrate 10.
The joint between the mounting board 10 and the mounting board 10 is sealed and mounted.
In this embodiment, there is no need to clean the solder flux after reflow, and it is not necessary to underfill the sealing resin. This makes it possible to flip chip connect the semiconductor chips very efficiently. FIG.
Comparing (a) and (b), it can be seen that the semiconductor chip mounting method of the present embodiment uses a much simpler manufacturing process than the conventional method.
【００２９】なお、本実施形態では、半導体チップ２０
を接着剤３０を介して実装基板１０に搭載し、半田接合
用のフラックスを使用せず、半導体チップ２０を実装基
板１０に実装した後は、アンダーフィルを行わない。こ
のような操作を可能にするためには、接着剤３０とし
て、エポキシ系樹脂等の樹脂の主要部に、アミン（R-NH
3）または、カルボン酸(R-COOH）等の酸無水物を加えた
ものを使用し、通常の半田フラックスに使用されている
ロジン等の固形分を添加しないようにする。アミンまた
はカルボン酸等の酸無水物は、硬化反応前の状態では酸
化銅を還元する作用があり、硬化反応の際には硬化剤と
して作用する。たとえば、カルボン酸による酸化銅の還
元反応は以下のとおりである。 Ｘ・ＣＯＯＨ＋Ｃｕ2Ｏ → Ｘ・ＣＯＯＣｕ＋Ｈ2ＯIn this embodiment, the semiconductor chip 20
Is mounted on the mounting substrate 10 via the adhesive 30 and soldered.
The semiconductor chip 20 is mounted without using the flux for mounting.
After mounting on the board 10, no underfill is performed. This
In order to enable such operations, the adhesive 30
The main part of the resin such as epoxy resin, amine (R-NH
Three) Or acid anhydride such as carboxylic acid (R-COOH)
Used for normal soldering flux
Avoid adding solids such as rosin. Amine or
Is an acid anhydride such as carboxylic acid before curing reaction.
It has the effect of reducing copper oxide, and at the time of the curing reaction,
Act. For example, reduction of copper oxide by carboxylic acid
The original reaction is as follows. X COOH + CuTwoO → X ・ COOCu + HTwoO
【００３０】上記実施形態では接続パッド１２は銅によ
って形成されているから、半田バンプ２２と接続パッド
１２とを半田接合する際に、接着剤３０に含まれている
酸無水物の作用によって接続パッド１２の表面の酸化銅
が還元されることにより、半田バンプ２２と接続パッド
１２とが確実に半田接合される。また、接着剤３０を硬
化させる際には、酸無水物は硬化促進剤として作用する
から、適宜分量を増量することによって接着剤３０の硬
化時間を短縮して、作業工程を効率化することが可能で
ある。本実施形態では接着剤３０が短時間で硬化するよ
うにしているが、これは酸無水物の分量を通常よりも増
量させて硬化時間を短縮するようにしたものである。In the above embodiment, since the connection pad 12 is formed of copper, when the solder bump 22 and the connection pad 12 are solder-bonded, the connection pad 12 is formed by the action of the acid anhydride contained in the adhesive 30. By reducing the copper oxide on the surface of the substrate 12, the solder bumps 22 and the connection pads 12 are securely soldered. When the adhesive 30 is cured, the acid anhydride acts as a curing accelerator. Therefore, by appropriately increasing the amount, the curing time of the adhesive 30 can be shortened, and the work process can be made more efficient. It is possible. In the present embodiment, the adhesive 30 is cured in a short time, but this is to shorten the curing time by increasing the amount of the acid anhydride more than usual.
【００３１】なお、上記実施形態では半導体チップ２０
に形成する半田バンプ２２は錫−鉛の共晶半田である
が、融点が１８３℃以下の他の半田合金、たとえば、錫
−銀−ビスマス等の半田合金を使用することもできる。
半田バンプ接合による実装方法では、接着剤の硬化温度
よりも溶融温度が高い半田であれば使用することが可能
である。ただし、本実施形態のようにエポキシ系の樹脂
材を接着剤に使用する場合は、融点が１８３℃近傍の半
田合金が温度条件の関係で好適に使用できる。In the above embodiment, the semiconductor chip 20
The solder bumps 22 to be formed are tin-lead eutectic solders, but other solder alloys having a melting point of 183 ° C. or less, for example, solder alloys such as tin-silver-bismuth can also be used.
In the mounting method by solder bump bonding, any solder having a melting temperature higher than the curing temperature of the adhesive can be used. However, when an epoxy resin material is used for the adhesive as in the present embodiment, a solder alloy having a melting point of around 183 ° C. can be suitably used in relation to the temperature conditions.
【００３２】上記実施形態は、電極に半田バンプ２２を
形成した半導体チップ２０を実装基板１０にフリップチ
ップ接続によって実装する方法である。本発明に係る半
導体チップの実装方法は、電極として金バンプを形成し
た半導体チップ２０を実装基板１０にフリップチップ接
続によって実装する場合にも適用することができる。図
７(a)は、金バンプを形成した半導体チップ２０を実装
基板１０に実装する場合の製造工程を示している。図７
(b)は、金バンプを形成した半導体チップ２０を実装す
る従来の製造工程を示す。The above embodiment is a method of mounting the semiconductor chip 20 having the solder bumps 22 formed on the electrodes on the mounting substrate 10 by flip-chip connection. The method for mounting a semiconductor chip according to the present invention can also be applied to a case where the semiconductor chip 20 on which gold bumps are formed as electrodes is mounted on the mounting substrate 10 by flip-chip connection. FIG. 7A shows a manufacturing process when the semiconductor chip 20 on which the gold bumps are formed is mounted on the mounting substrate 10. FIG.
(b) shows a conventional manufacturing process for mounting the semiconductor chip 20 having the gold bump formed thereon.
【００３３】金バンプを形成した半導体チップ２０を実
装する場合の実施形態も、基本的な方法において上記実
施形態の方法と変わるものではない。すなわち、実装基
板１０を乾燥させた後、実装基板１０の実装面に接着剤
３０を被着し、金バンプ２６と実装基板１０の接続パッ
ド１２とを位置合わせして半導体チップ２０を実装基板
１０に加圧して搭載し、リフロー工程にて金バンプ２６
と接続パッド１２とを一括して電気的に接続するととも
に、接着剤３０を硬化させて実装基板１０に半導体チッ
プ２０を固定し、半導体チップ２０と実装基板１０との
接合部を接着剤３０によって封止する。The embodiment in which the semiconductor chip 20 on which the gold bumps are formed is mounted is not different from the above embodiment in a basic method. That is, after the mounting substrate 10 is dried, the adhesive 30 is applied to the mounting surface of the mounting substrate 10, the gold bumps 26 and the connection pads 12 of the mounting substrate 10 are aligned, and the semiconductor chip 20 is mounted on the mounting substrate 10. To the bumps 26 in the reflow process.
And the connection pads 12 are collectively electrically connected, and the adhesive 30 is cured to fix the semiconductor chip 20 to the mounting substrate 10, and the joint between the semiconductor chip 20 and the mounting substrate 10 is bonded by the adhesive 30. Seal.
【００３４】なお、金バンプ接合による場合は、金バン
プ２６と接続パッド１２とを確実に接続できるようにす
るため、接続パッド１２の表面にあらかじめ金めっき４
０を施しておき、金バンプ２６と接続パッド１２とを金
−金結合によって接続するようにするとよい。図８は、
実装基板１０の接続パッド１２の表面に金めっき４０を
施し、半導体チップ２０の金バンプ２６を加圧すること
によって、金バンプ２６と金めっき４０との当接部を金
−金結合する状態を示す。実装基板１０を加熱した状態
で実装基板１０の表面に接着剤３０を被着させ、半導体
チップ２０を加圧して実装基板１０に搭載することによ
って、金バンプ２６と接続パッド１２の金めっき４０と
の間で金−金結合がなされ、仮接続された状態となる。
実装基板２０を加熱しておくことにより数秒程度で金−
金結合がなされる。In the case of gold bump bonding, the surface of the connection pad 12 is preliminarily plated with gold plating 4 so that the gold bump 26 and the connection pad 12 can be securely connected.
0, the gold bump 26 and the connection pad 12 may be connected by gold-gold bonding. FIG.
A state in which gold plating 40 is applied to the surface of the connection pad 12 of the mounting substrate 10 and the gold bump 26 of the semiconductor chip 20 is pressed, so that the contact portion between the gold bump 26 and the gold plating 40 is gold-gold bonded. . The adhesive 30 is applied to the surface of the mounting substrate 10 while the mounting substrate 10 is heated, and the semiconductor chip 20 is pressed and mounted on the mounting substrate 10, so that the gold bumps 26 and the gold plating 40 of the connection pads 12 are removed. Are gold-gold bonded between them, and are in a temporarily connected state.
By heating the mounting substrate 20, the gold
A gold bond is made.
【００３５】金バンプ２６と接続パッド１２の金めっき
４０との間の金−金結合は、弱い接続であるから、リフ
ロー工程によって接着剤３０を硬化させる温度に加熱し
て保持することにより、接着剤３０を完全に硬化させ半
導体チップ２０を実装基板１０に確実に接合する。ま
た、このリフロー工程の加熱によって、金バンプ２６と
接続パッド１２との金拡散が促進され、金バンプ２６と
接続パッド１２との電気的接続が確実になされるように
なる。接着剤３０は硬化時に収縮し、これによって金バ
ンプ２６と接続パッド１０とが強固に接合され、金バン
プ２６と接続パッド１０との電気的接続が確実に保持さ
れるようになる。Since the gold-gold bond between the gold bump 26 and the gold plating 40 of the connection pad 12 is a weak connection, the bonding is performed by heating and holding the adhesive 30 at a temperature at which the adhesive 30 is cured by a reflow process. The agent 30 is completely cured, and the semiconductor chip 20 is securely bonded to the mounting substrate 10. Further, by the heating in this reflow step, gold diffusion between the gold bumps 26 and the connection pads 12 is promoted, and electrical connection between the gold bumps 26 and the connection pads 12 is ensured. The adhesive 30 shrinks upon curing, whereby the gold bump 26 and the connection pad 10 are firmly joined, and the electrical connection between the gold bump 26 and the connection pad 10 is reliably maintained.
【００３６】本実施形態の半導体チップの実装方法によ
れば、接着剤３０を硬化させて半導体チップ２０を実装
した時点で、樹脂による封止も完了する。従来例と比較
すると、本実施形態の半導体チップの実装方法によれ
ば、金バンプに導電性接着剤２８を塗布する必要がな
く、また、半導体チップを実装基板に搭載した後、アン
ダーフィルする必要がない。これによって、半導体チッ
プをフリップチップ接続によって容易にかつ効率的に実
装することが可能になり、製造コストの低減を図ること
が可能になる。なお、半導体チップを実装基板に加圧し
て搭載する工程と実装基板に半導体チップを搭載した
後、接着剤を加熱して硬化させるリフロー工程は、同一
の設備で行うことも可能である。設備を共用することに
よって、さらに生産性を向上させることが可能になる。According to the semiconductor chip mounting method of this embodiment, the sealing with the resin is completed when the adhesive 30 is cured and the semiconductor chip 20 is mounted. Compared to the conventional example, according to the semiconductor chip mounting method of the present embodiment, it is not necessary to apply the conductive adhesive 28 to the gold bumps, and it is necessary to underfill after mounting the semiconductor chip on the mounting board. There is no. As a result, the semiconductor chip can be easily and efficiently mounted by flip-chip connection, and the manufacturing cost can be reduced. Note that the step of mounting the semiconductor chip on the mounting substrate by pressing and the step of mounting the semiconductor chip on the mounting substrate and then heating and curing the adhesive can be performed by the same equipment. By sharing the equipment, the productivity can be further improved.
【００３７】[0037]
【発明の効果】本発明に係る半導体チップの実装方法で
は、実装基板に接着剤を塗布し、半導体チップを実装基
板に加圧して搭載し、リフローにより半導体チップを実
装基板に接合する工程によって実装するから、実装工程
がきわめて簡略化され、処理工程が短縮されてフリップ
チップ接続によって半導体チップを実装する作業効率を
大幅に向上させることが可能になる。これにより、半導
体チップをフリップチップ実装して得られる半導体装置
の製造コストを効果的に削減することができる。According to the method of mounting a semiconductor chip of the present invention, an adhesive is applied to a mounting substrate, the semiconductor chip is mounted on the mounting substrate by pressing, and the semiconductor chip is bonded to the mounting substrate by reflow. Therefore, the mounting process is greatly simplified, the processing process is shortened, and the operation efficiency of mounting the semiconductor chip by flip-chip connection can be greatly improved. Thereby, the manufacturing cost of the semiconductor device obtained by flip-chip mounting the semiconductor chip can be effectively reduced.
【図１】半田バンプ接合によって半導体チップをフリッ
プチップ接続する製造工程の実施形態及び従来例を示す
説明図。FIG. 1 is an explanatory view showing an embodiment and a conventional example of a manufacturing process for flip-chip connecting a semiconductor chip by solder bump bonding.
【図２】実装基板に半導体チップを実装する方法を示す
説明図。FIG. 2 is an explanatory view showing a method of mounting a semiconductor chip on a mounting board.
【図３】実装基板に半導体チップを加圧して搭載した状
態の断面図。FIG. 3 is a cross-sectional view showing a state where a semiconductor chip is mounted on a mounting substrate by pressing.
【図４】半導体チップを加圧して実装基板に搭載する状
態を示す説明図。FIG. 4 is an explanatory view showing a state in which a semiconductor chip is pressed and mounted on a mounting substrate.
【図５】扁平につぶされた半田バンプが接続パッドから
離間した様子を示す説明図。FIG. 5 is an explanatory view showing a state in which a flattened solder bump is separated from a connection pad.
【図６】リフロー工程での加熱方法を示すグラフ。FIG. 6 is a graph showing a heating method in a reflow step.
【図７】金バンプ接合によって半導体チップをフリップ
チップ接続する製造工程の実施形態及び従来例を示す説
明図。FIG. 7 is an explanatory view showing an embodiment and a conventional example of a manufacturing process for flip-chip connecting a semiconductor chip by gold bump bonding.
【図８】金−金結合によって半導体チップを実装基板に
仮接続する状態を示す説明図。FIG. 8 is an explanatory view showing a state in which a semiconductor chip is temporarily connected to a mounting board by gold-gold bonding.
【図９】金バンプ接合によって半導体チップを実装基板
に実装した状態の断面図。FIG. 9 is a cross-sectional view showing a state where a semiconductor chip is mounted on a mounting board by gold bump bonding.
【図１０】半田バンプ接合によって半導体チップを実装
する従来方法を示す説明図。FIG. 10 is an explanatory view showing a conventional method for mounting a semiconductor chip by solder bump bonding.
【図１１】金バンプ接合によって半導体チップを実装す
る従来方法を示す説明図。FIG. 11 is an explanatory view showing a conventional method for mounting a semiconductor chip by gold bump bonding.
１０ 実装基板 １２ 接続パッド ２０ 半導体チップ ２２ 半田バンプ ２４ 樹脂 ２６ 金バンプ ２８ 導電性接着剤 ３０ 接着剤 ４０ 金めっき DESCRIPTION OF SYMBOLS 10 Mounting board 12 Connection pad 20 Semiconductor chip 22 Solder bump 24 Resin 26 Gold bump 28 Conductive adhesive 30 Adhesive 40 Gold plating
───────────────────────────────────────────────────── フロントページの続き (72)発明者 石川 直樹 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 (72)発明者 松沼 繁男 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 (72)発明者 竹内 周一 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 Ｆターム(参考） 5F044 KK01 LL11 QQ03 RR17 RR18 5F061 AA01 BA03 CA04 CB03 CB12 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Naoki Ishikawa 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Shigeo Matsunuma 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 Fujitsu Co., Ltd. (72) Inventor Shuichi Takeuchi 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture F-term in Fujitsu Co., Ltd. 5F044 KK01 LL11 QQ03 RR17 RR18 5F061 AA01 BA03 CA04 CB03 CB12
Claims (9)
り実装基板に実装する半導体チップの実装方法におい
て、 実装基板の前記半導体チップの実装面に、半導体チップ
を実装基板に接着した際に半導体チップバンプと実装基
板の接続パッドとの接合部を封止する接着剤を被着し、 該実装基板の接着剤が被着された面に、前記バンプと前
記接続パッドとを位置合わせして半導体チップを加圧し
て搭載し、 リフローにより前記接着剤を硬化させて前記半導体チッ
プと実装基板との間を封止して接合するとともに、前記
バンプと前記接続パッドとを接続することを特徴とする
半導体チップの実装方法。1. A method of mounting a semiconductor chip on a mounting substrate by flip-chip connection, wherein the semiconductor chip is mounted on a mounting surface of the semiconductor chip of the mounting substrate when the semiconductor chip is bonded to the mounting substrate. An adhesive for sealing a joint portion between the substrate and the connection pad is applied, and the semiconductor chip is pressed by aligning the bump and the connection pad on the surface of the mounting substrate on which the adhesive is applied. Mounting the semiconductor chip and curing the adhesive by reflow to seal and bond between the semiconductor chip and the mounting substrate, and connecting the bump and the connection pad. Method.
前記実装基板に半導体チップを搭載する際に、 前記実装基板に被着された接着剤を加熱して接着剤の粘
度を低下させ、半導体チップの搭載領域から接着剤を押
し出して、前記バンプと接続パッドとを直接接触させる
ことを特徴とする請求項１記載の半導体チップの実装方
法。2. When the semiconductor chip is mounted on the mounting substrate by pressing the semiconductor chip on the mounting substrate, the adhesive applied to the mounting substrate is heated to reduce the viscosity of the adhesive. 2. The method for mounting a semiconductor chip according to claim 1, wherein an adhesive is extruded from a mounting area of the chip to directly contact the bump and the connection pad.
し出した際に、半導体チップの側面と実装基板との間に
フィレットを形成することを特徴とする請求項２記載の
半導体チップの実装方法。3. The method for mounting a semiconductor chip according to claim 2, wherein a fillet is formed between a side surface of the semiconductor chip and the mounting substrate when the adhesive is extruded from a mounting area of the semiconductor chip.
ロジン等の固形分を含まず、活性剤及び硬化促進剤とし
て、アミンまたはカルボン酸等の酸無水物を含む樹脂剤
を使用することを特徴とする請求項１、２または３記載
の半導体チップの実装方法。4. The resin material to be adhered to the mounting board,
The semiconductor chip according to claim 1, wherein a resin agent containing an acid anhydride such as an amine or a carboxylic acid is used as an activator and a curing accelerator without containing a solid content such as rosin. Implementation method.
もしくは該共晶半田よりも低温の融点を有する半田合金
によりバンプが形成され、 前記樹脂剤が、エポキシ系樹脂を主成分とするものであ
ることを特徴とする請求項１、２、３または４記載の半
導体チップの実装方法。5. The semiconductor chip has bumps formed of a tin-lead eutectic solder or a solder alloy having a lower melting point than the eutectic solder, and the resin agent is mainly composed of an epoxy resin. The method for mounting a semiconductor chip according to claim 1, wherein the semiconductor chip is mounted.
した状態で、半田融点温度以下に加熱することによりバ
ンプと接続パッドとの間に合金層を形成してバンプと接
続パッドとを仮接続した後、リフローすることを特徴と
する請求項５記載の半導体チップの実装方法。6. In a state where the semiconductor chip is mounted on the mounting substrate by pressing, a solder layer is heated to a temperature equal to or lower than the melting point of the solder to form an alloy layer between the bump and the connection pad, thereby temporarily connecting the bump and the connection pad. 6. The method for mounting a semiconductor chip according to claim 5, wherein reflow is performed after said step.
する際に、半導体チップの加圧力によってバンプをつぶ
して若干扁平に形成し、リフローの際にバンプが球形に
戻る作用を利用してバンプと接続パッドとを接合するこ
とを特徴とする請求項５または６記載の半導体チップの
製造方法。7. When the semiconductor chip is mounted on the mounting substrate by pressing, the bump is crushed by the pressure of the semiconductor chip to form a slightly flat shape, and the bump is returned to a spherical shape during reflow by utilizing the bump. 7. The method for manufacturing a semiconductor chip according to claim 5, wherein the semiconductor chip and the connection pad are joined.
ンプが形成されたものであることを特徴とする請求項
１、２、３または４記載の半導体チップの実装方法。8. The method for mounting a semiconductor chip according to claim 1, wherein the semiconductor chip has a bump formed by a gold bump.
かじめ金めっきを施し、半導体チップを実装基板に加圧
して搭載した際に、金−金結合によりバンプと接続パッ
ドとを仮接続した後、リフローすることを特徴とする請
求項８記載の半導体チップの実装方法。9. A method in which gold plating is applied to the surfaces of the connection pads of the mounting substrate in advance, and when the semiconductor chip is mounted on the mounting substrate by pressing, the bumps and the connection pads are temporarily connected by gold-gold bonding. 9. The method for mounting a semiconductor chip according to claim 8, wherein reflow is performed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000149783A JP2001332583A (en) | 2000-05-22 | 2000-05-22 | Method of mounting semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000149783A JP2001332583A (en) | 2000-05-22 | 2000-05-22 | Method of mounting semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001332583A true JP2001332583A (en) | 2001-11-30 |
Family
ID=18655586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000149783A Pending JP2001332583A (en) | 2000-05-22 | 2000-05-22 | Method of mounting semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001332583A (en) |
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