JP2002343829A - Method of packaging semiconductor device - Google Patents
Method of packaging semiconductor deviceInfo
- Publication number
- JP2002343829A JP2002343829A JP2001150645A JP2001150645A JP2002343829A JP 2002343829 A JP2002343829 A JP 2002343829A JP 2001150645 A JP2001150645 A JP 2001150645A JP 2001150645 A JP2001150645 A JP 2001150645A JP 2002343829 A JP2002343829 A JP 2002343829A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- thermosetting resin
- temperature
- wiring board
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置の実装
方法に関し、特に、半導体装置と配線基板との間の熱硬
化性樹脂におけるボイドの発生を抑制し、高い接続信頼
性が得られる半導体層装置の実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor device, and more particularly, to a semiconductor layer capable of suppressing generation of voids in a thermosetting resin between a semiconductor device and a wiring board and obtaining high connection reliability. The present invention relates to an apparatus mounting method.
【０００２】[0002]
【従来の技術】従来のはんだバンプを用いたフリップチ
ップ実装方法を図７に示す。図７に示すように、従来
は、バンプ２形成後のＬＳＩチップ等の半導体装置１の
バンプ先端または配線基板３にフラックス１０を付着さ
せた後、配線基板３に位置合わせして半導体装置１を搭
載した後、リフローを行い、その後、フラックス１０を
洗浄した後、毛細管現象により半導体装置１と配線基板
３のギャップにアンダーフィル樹脂（熱硬化性樹脂６）
の充填を行い、最後に熱硬化性樹脂６を硬化させる方法
が行われている。2. Description of the Related Art A conventional flip chip mounting method using solder bumps is shown in FIG. Conventionally, as shown in FIG. 7, a flux 10 is adhered to a bump tip of a semiconductor device 1 such as an LSI chip or the like after a bump 2 is formed or a wiring substrate 3, and then the semiconductor device 1 is aligned with the wiring substrate 3. After mounting, reflow is performed, and after the flux 10 is washed, an underfill resin (thermosetting resin 6) is formed in the gap between the semiconductor device 1 and the wiring board 3 by capillary action.
And finally, the thermosetting resin 6 is cured.
【０００３】また、はんだを有するフリップチップ実装
方法のうち、あらかじめ配線基板３上に封止樹脂６を塗
布しておき、半導体装置１をマウント後、加熱すること
ではんだ接続および樹脂硬化を行なう実装方法として、
例えば、特開平１１−２３３５５８号公報に開示されて
いる方法がある。この方法による実装プロセスを図８に
示す。[0003] In a flip chip mounting method having solder, a sealing resin 6 is applied on the wiring substrate 3 in advance, and after mounting the semiconductor device 1, the mounting is performed by heating and performing solder connection and resin curing. As a method,
For example, there is a method disclosed in JP-A-11-233558. FIG. 8 shows a mounting process according to this method.
【０００４】まず、半導体装置１を配線基板３上に搭載
する前工程として、半導体装置１の端子電極にバンプ２
を形成し（ステップ１）、パッド４にはんだ５を形成す
る（ステップ２）。次に、予め配線基板３の半導体装置
１が搭載される部分に、半導体装置１と配線基板３の間
を充分に介在させる量の樹脂６を塗布する（ステップ
３）。次に、この樹脂６を塗布したパッド４上のはんだ
５にバンプ２が位置するように半導体装置１を配線基板
３に位置決め搭載する。その後、半導体装置１を吸着し
たボンディングツ−ル７に備えられたヒ−タ−等の加熱
手段により、位置決め搭載した半導体装置１を加熱する
と同時に、配線基板３を載せた基板ステ−ジ８に備えら
れたヒ−タ−等の加熱手段で加熱を行なう（ステップ
４）。この加熱工程では、最初、はんだ融点以上の温度
に加熱してバンプ２とはんだ５との接合部を金属結合さ
せた後、はんだ融点以下に加熱温度を下げて樹脂６を硬
化させて実装が完了する。First, as a pre-process for mounting the semiconductor device 1 on the wiring board 3, bumps 2 are applied to terminal electrodes of the semiconductor device 1.
Is formed (Step 1), and a solder 5 is formed on the pad 4 (Step 2). Next, an amount of the resin 6 that sufficiently interposes between the semiconductor device 1 and the wiring board 3 is applied to a portion of the wiring board 3 on which the semiconductor device 1 is mounted (Step 3). Next, the semiconductor device 1 is positioned and mounted on the wiring board 3 such that the bumps 2 are positioned on the solders 5 on the pads 4 to which the resin 6 has been applied. Thereafter, the positioning and mounting semiconductor device 1 is heated by a heating means such as a heater provided on the bonding tool 7 to which the semiconductor device 1 is sucked, and at the same time, the substrate stage 8 on which the wiring board 3 is mounted is placed. Heating is performed by a heating means such as a heater provided (step 4). In this heating step, first, the bonding portion between the bump 2 and the solder 5 is metal-bonded by heating to a temperature equal to or higher than the solder melting point, and then the heating temperature is lowered to a temperature lower than the solder melting point to cure the resin 6 to complete the mounting. I do.
【０００５】他の従来例として、バンプ２がはんだバン
プであり、樹脂６に酸化膜除去作用を含んだ樹脂を用い
る場合がある。これらの方法により、半導体装置と基板
のギャップにアンダーフィル樹脂充填する工程を削除
し、生産性を向上させている。As another conventional example, there is a case where the bump 2 is a solder bump and the resin 6 has a function of removing an oxide film. With these methods, the step of filling the gap between the semiconductor device and the substrate with an underfill resin is eliminated, and the productivity is improved.
【０００６】[0006]
【発明が解決しようとする課題】図７に示すフラックス
を用いてはんだバンプを接続する従来のフリップチップ
実装方法では、以下の問題点がある。The conventional flip-chip mounting method of connecting solder bumps using the flux shown in FIG. 7 has the following problems.
【０００７】まず、第１の問題点は、ＬＳＩの高密度化
による狭ピッチ化が進むにつれ、バンプ２が微細化し、
半導体装置１と配線基板３間の隙間が狭くなる傾向があ
り、フラックス洗浄が益々困難な状況となってきてい
る。フラックス残渣が引き起こす問題点としては、活性
剤がＬＳＩ等の電子部品に残留し、この残留した活性剤
が吸湿すると、そのイオン成分が電気的絶縁性を低下さ
せ、マイグレーション等により製造された電子部品の信
頼性を低下させるといった問題を引き起こす。また、ア
ンダーフィル充填をも阻害することとなり、樹脂封止層
にボイドが発生するなど実装信頼性を低下させるという
問題がある。First, the first problem is that as the pitch of LSIs becomes smaller due to higher density, the bumps 2 become finer,
The gap between the semiconductor device 1 and the wiring board 3 tends to be narrower, and it has become increasingly difficult to perform flux cleaning. The problem caused by the flux residue is that an activator remains in an electronic component such as an LSI, and when the remaining activator absorbs moisture, the ionic component lowers the electrical insulation and the electronic component manufactured by migration or the like. Causes a problem of lowering the reliability of the device. In addition, it also hinders underfill filling, which causes a problem of lowering mounting reliability such as generation of voids in the resin sealing layer.
【０００８】第２の問題点は、フラックス洗浄工程やア
ンダ−フィル充填工程などのプロセスを必要とする為、
フラックス洗浄に必要な設備を必要としたり、アンダ−
フィル充填に時間がかかる等、生産コストが高くなるこ
とである。[0008] The second problem is that a process such as a flux cleaning step and an underfill filling step is required.
Equipment required for flux cleaning is required,
The production cost increases, for example, it takes time to fill the fill.
【０００９】このような問題に関して、図８に示すよう
なあらかじめ配線基板３上に熱硬化性樹脂６を塗布して
おき、半導体装置１を搭載後、熱硬化性樹脂６を硬化さ
せる一括プロセスが提案されている。しかしながら、こ
の方法では、半導体装置１を熱硬化性樹脂６が塗布され
た配線基板３上に搭載する際に、半導体装置１側の突起
電極間凹部の外気が抜けきれずに残ったり、樹脂６を外
側に強制的に押し出すこととなるため、バンプ２や配線
基板３の凹凸があると樹脂６が乱流になって外気を巻き
込む等の影響でボイドが発生しやすい。As for such a problem, as shown in FIG. 8, a batch process of applying a thermosetting resin 6 on the wiring board 3 in advance, mounting the semiconductor device 1, and then curing the thermosetting resin 6 is performed. Proposed. However, in this method, when the semiconductor device 1 is mounted on the wiring board 3 coated with the thermosetting resin 6, the outside air in the recess between the protruding electrodes on the semiconductor device 1 side remains without being completely removed, or the resin 6 Is forcibly pushed outward, and if there are irregularities on the bumps 2 and the wiring board 3, the resin 6 becomes turbulent, and voids are likely to be generated due to the influence of, for example, entraining outside air.
【００１０】この現象は、半導体装置１と配線基板３を
接続する電極が半導体装置１表面全体に配置しているエ
リア配置の場合に特に顕著に発生する。電極間にボイド
がある状態では、ボイド部のバンプ２に応力が集中して
接続破壊を起こすことがあるだけでなく、装置動作時に
発生する熱応力で電極金属を塑性変形させ、場合によっ
てはボイドを介して隣り合った電極が連結してしまうシ
ョ−トを引き起こす等、接続信頼性に対して重大な問題
となる。This phenomenon occurs particularly remarkably in an area arrangement in which the electrodes connecting the semiconductor device 1 and the wiring board 3 are arranged on the entire surface of the semiconductor device 1. When there is a void between the electrodes, not only the stress concentrates on the bump 2 in the void portion, but also the connection may be broken. In addition, the electrode metal may be plastically deformed by thermal stress generated during operation of the device, and in some cases, the void may be formed. This causes a serious problem with respect to connection reliability, such as causing a short circuit in which adjacent electrodes are connected via the connection.
【００１１】また、はんだ酸化膜除去作用を含む樹脂を
使用し、はんだ接続を行なう場合、ボイドがあると酸化
膜除去作用が弱くなり、はんだ表面の酸化膜を除去しに
くくなる為、ボイド部分のバンプは接続不良を起こしや
すくなる。In the case of using a resin having a function of removing a solder oxide film and performing solder connection, if a void is present, the effect of removing the oxide film is weakened, and it becomes difficult to remove the oxide film on the solder surface. Bumps tend to cause poor connections.
【００１２】前記のようなボイドが引き起こす問題は、
接続信頼性を向上させるために熱硬化性樹脂の熱膨張係
数を調整する手段として樹脂中にシリカ等のフィラ−を
添加すると、樹脂粘度が相対的に上昇する為、樹脂がな
めらかに流れず半導体装置や配線基板に濡れにくくなる
ためさらに顕著になることから、信頼性の高い実装品を
得ることは困難である。The problem caused by the above-mentioned void is as follows.
When a filler such as silica is added to the resin as a means for adjusting the thermal expansion coefficient of the thermosetting resin to improve connection reliability, the resin viscosity relatively increases, so that the resin does not flow smoothly. It becomes difficult to get wet with the device and the wiring board, so that it becomes more remarkable, and it is difficult to obtain a highly reliable mounted product.
【００１３】本発明の目的は、はんだバンプが形成され
たベアチップまたはチップサイズパッケージ等の半導体
装置において、接続信頼性を確保するとともに生産性に
優れた実装方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a mounting method which secures connection reliability and is excellent in productivity in a semiconductor device such as a bare chip or a chip size package on which solder bumps are formed.
【００１４】[0014]
【課題を解決するための手段】本発明の半導体装置の実
装方法は、半導体装置の電極と配線基板の電極とがバン
プを介して電気的に接続され、前記半導体装置と前記配
線基板との間を熱硬化性樹脂により封止してなる半導体
装置の実装方法において、前記配線基板上に熱硬化性樹
脂を塗布する工程と、前記半導体装置を前記配線基板上
に搭載するに際し、前記半導体装置と前記熱硬化性樹脂
とが接触する前に、前記半導体装置を少なくとも前記配
線基板より高い温度で加熱する予備加熱工程と、前記半
導体装置の電極と前記配線基板の電極とが前記バンプを
介して接触した状態で、前記半導体装置を前記予備加熱
工程以上の温度に加熱して前記半導体装置の電極と前記
配線基板間の電極とを電気的に接続するバンプ接続工程
と、前記半導体装置の搭載が完了した前記配線基板を、
前記バンプ接続工程以下の温度雰囲気中に保持し、前記
熱硬化性樹脂を硬化させる樹脂硬化工程と、を含むもの
である。According to a method of mounting a semiconductor device of the present invention, an electrode of a semiconductor device and an electrode of a wiring board are electrically connected via bumps, and the semiconductor device and the wiring board are electrically connected to each other. In a method of mounting a semiconductor device in which the semiconductor device is sealed with a thermosetting resin, a step of applying a thermosetting resin on the wiring substrate, and when mounting the semiconductor device on the wiring substrate, the semiconductor device and Before the thermosetting resin comes into contact, a preheating step of heating the semiconductor device at least at a temperature higher than that of the wiring board, and an electrode of the semiconductor device and an electrode of the wiring board come into contact with each other via the bump. A bump connection step of heating the semiconductor device to a temperature equal to or higher than the preheating step to electrically connect an electrode of the semiconductor device and an electrode between the wiring boards; It said wiring board mounting is complete,
A resin curing step of keeping the thermosetting resin in a temperature atmosphere equal to or lower than the bump connection step and curing the thermosetting resin.
【００１５】本発明においては、前記半導体装置を前記
配線基板上に搭載するに際し、前記半導体装置と前記配
線基板上に塗布された前記熱硬化性樹脂とが接触する直
前に、前記半導体装置を載置するツールの移動速度を減
速、又は、一旦停止させる構成とすることができる。In the present invention, when the semiconductor device is mounted on the wiring substrate, the semiconductor device is mounted immediately before the semiconductor device comes into contact with the thermosetting resin applied on the wiring substrate. The moving speed of the tool to be placed may be reduced or temporarily stopped.
【００１６】また、本発明においては、前記予備加熱工
程において、前記配線基板の温度を前記熱硬化性樹脂の
濡れ性を改善可能な第１の温度に設定し、前記半導体装
置の温度を前記第１の温度以上、前記バンプの溶融温度
以下の第２の温度に設定する構成とすることができ、前
記第１の温度が、略６０乃至１００℃、前記第２の温度
が、略１５０℃以上に設定されることが好ましい。In the present invention, in the preheating step, the temperature of the wiring substrate is set to a first temperature capable of improving the wettability of the thermosetting resin, and the temperature of the semiconductor device is set to the first temperature. The temperature may be set to a second temperature equal to or higher than 1 and equal to or lower than the melting temperature of the bump, wherein the first temperature is approximately 60 to 100 ° C, and the second temperature is approximately 150 ° C or higher. Is preferably set to.
【００１７】また、本発明の半導体装置の実装方法は、
半導体装置の電極と配線基板の電極とがバンプを介して
電気的に接続され、前記半導体装置と前記配線基板との
間を熱硬化性樹脂により封止してなる半導体装置の実装
方法において、前記配線基板上に熱硬化性樹脂を塗布す
る工程と、前記半導体装置を前記配線基板上に搭載する
に際し、前記半導体装置と前記熱硬化性樹脂とが接触す
る前に、前記半導体装置を載置するツールの移動速度を
減速又は一旦停止させる工程と、前記半導体装置の電極
と前記配線基板の電極とが前記バンプを介して接触した
状態で、前記半導体装置を加熱して前記半導体装置の電
極と前記配線基板間の電極とを電気的に接続するバンプ
接続工程と、前記半導体装置の搭載が完了した前記配線
基板を、前記バンプ接続工程以下の温度雰囲気中に保持
し、前記熱硬化性樹脂を硬化させる樹脂硬化工程と、を
含むものである。Further, a method of mounting a semiconductor device according to the present invention comprises:
An electrode of a semiconductor device and an electrode of a wiring board are electrically connected via bumps, and the semiconductor device and the wiring board are sealed with a thermosetting resin. A step of applying a thermosetting resin on a wiring board, and, when mounting the semiconductor device on the wiring board, before placing the semiconductor device and the thermosetting resin, placing the semiconductor device. A step of reducing or temporarily stopping the moving speed of the tool, and heating the semiconductor device while the electrodes of the semiconductor device and the electrodes of the wiring substrate are in contact with each other via the bumps, and A bump connection step of electrically connecting electrodes between the wiring boards, and holding the wiring board on which the semiconductor device is mounted in an atmosphere at a temperature equal to or lower than that of the bump connection step; A resin curing step of curing the lipid is intended to include.
【００１８】本発明においては、前記半導体装置と前記
熱硬化性樹脂とが接触する前における前記ツールの移動
速度が、略１０ｍｍ／ｓ以下に設定される構成とするこ
とができる。In the present invention, a configuration may be adopted in which a moving speed of the tool before the semiconductor device and the thermosetting resin come into contact with each other is set to about 10 mm / s or less.
【００１９】また、本発明においては、前記熱硬化性樹
脂を前記配線基板上に塗布する際に、前記配線基板を加
熱しながら塗布する構成とすることもできる。In the present invention, when the thermosetting resin is applied on the wiring board, the thermosetting resin may be applied while heating the wiring board.
【００２０】また、本発明においては、前記半導体装置
は、バンプが形成されたベアチップまたはチップサイズ
パッケージであることが好ましい。Further, in the present invention, it is preferable that the semiconductor device is a bare chip or a chip size package on which bumps are formed.
【００２１】また、本発明においては、前記バンプはは
んだからなり、前記熱硬化性樹脂ははんだ酸化膜除去作
用を有することが好ましい。Further, in the present invention, it is preferable that the bumps are made of solder, and the thermosetting resin has a function of removing a solder oxide film.
【００２２】本発明の実装方法の場合、半導体装置の搭
載に際し、半導体装置と熱硬化性樹脂とが接触する前に
半導体装置を少なくとも前記配線基板より高い温度で加
熱することで、配線基板側に塗布した熱硬化性樹脂が半
導体装置と接触すると、瞬時に樹脂粘度が低下して半導
体装置側に濡れやすくなる。このため、半導体装置側の
突起電極間の凹部にも樹脂が入り込みやすくなる。ま
た、中央部の樹脂が押し出されることにより、樹脂充填
される半導体装置外周については樹脂が濡れやすくなる
ことで押し出される樹脂速度に対して樹脂の濡れが追従
可能となる。このため、搭載時に発生するボイドを防止
することが可能となる。In the mounting method of the present invention, when mounting the semiconductor device, the semiconductor device is heated at least at a temperature higher than that of the wiring board before the semiconductor device comes into contact with the thermosetting resin, so that When the applied thermosetting resin comes into contact with the semiconductor device, the viscosity of the resin is instantaneously reduced and the semiconductor device is easily wetted. For this reason, the resin easily enters the recesses between the protruding electrodes on the semiconductor device side. In addition, since the resin in the central portion is extruded, the resin is easily wetted around the semiconductor device to be filled with the resin, so that the resin can follow the speed of the extruded resin. For this reason, it is possible to prevent voids generated during mounting.
【００２３】また、フィラ−添加した時など粘度が高い
樹脂の場合、樹脂の濡れ性や流動性が不足するが、加熱
に加えて半導体装置と熱硬化性樹脂が接触する直前に半
導体装置の搭載速度を減速させることにより、突起電極
間の凹部へ樹脂が入り込みやすくなり、樹脂の濡れが樹
脂押し出し速度に追従可能となるため、搭載時に発生す
るボイドを防止することが可能となる。Further, in the case of a resin having a high viscosity such as when a filler is added, the wettability and fluidity of the resin are insufficient. However, in addition to heating, the mounting of the semiconductor device immediately before the semiconductor device comes into contact with the thermosetting resin. Decreasing the speed makes it easier for the resin to enter the concave portions between the protruding electrodes, and enables the wetting of the resin to follow the resin extrusion speed, thereby preventing voids generated during mounting.
【００２４】また、使用する樹脂によっては、高温で長
時間加熱すると樹脂自体からボイドが発生するものがあ
るが、短時間の高温加熱で接続を行い、低い温度で樹脂
硬化させる方法にすれば、ボイドを防止できる。In addition, depending on the resin used, voids may be generated from the resin itself when heated at a high temperature for a long time. However, if a method is used in which connection is performed by heating at a high temperature for a short time and the resin is cured at a low temperature, Voids can be prevented.
【００２５】従って、本実装方法を行なえば、熱硬化性
樹脂の熱膨張係数を調整する為にシリカ等のフィラ−を
添加した場合であっても、搭載時のボイドや接続不良を
生じることがない為、信頼性の高い実装品を得ることが
出来る。Therefore, if this mounting method is carried out, voids and poor connection may occur at the time of mounting, even when a filler such as silica is added to adjust the thermal expansion coefficient of the thermosetting resin. Therefore, a highly reliable mounted product can be obtained.
【００２６】[0026]
【発明の実施の形態】次に、本発明の一実施の形態につ
いて図面を参照して詳細に説明する。図２を参照して、
エリアに配列されたＣｕパッド９上に高融点バンプ２が
形成されたＬＳＩを、同一配列位置にＣｕパッド４を形
成し、且つパッド４上に共晶はんだ５が予備はんだとし
て形成されたプリント配線基板３上に実装する時の一例
について説明する。Next, an embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIG.
An LSI in which the high melting point bumps 2 are formed on the Cu pads 9 arranged in the area, and a printed wiring in which the Cu pads 4 are formed in the same arrangement position and the eutectic solder 5 is formed on the pads 4 as preliminary solder An example of mounting on the substrate 3 will be described.
【００２７】まず、図２（ａ）に示すように、予備はん
だ５が形成されたプリント配線基板３を加熱されたステ
−ジ８上に置き、昇温する。昇温の目的は、熱硬化性樹
脂６を塗布する際にプリント配線基板３表面の樹脂の濡
れ性を向上させ、樹脂塗布時に配線基板３表面の凹凸の
影響で空気を巻き込みにくくする為である。この時の温
度は熱硬化性樹脂６の硬化反応があまり進まないことが
望ましく、６０℃〜１００℃程度が良い。プリント配線
基板３は、濡れ性改善のためにステ−ジ８に置く前にプ
ラズマ等の表面処理により、表面改質することも有効で
ある。First, as shown in FIG. 2 (a), the printed wiring board 3 on which the preliminary solder 5 is formed is placed on a heated stage 8, and the temperature is raised. The purpose of the temperature rise is to improve the wettability of the resin on the surface of the printed wiring board 3 when the thermosetting resin 6 is applied, and to prevent air from being entrained by the influence of the unevenness on the surface of the wiring board 3 during the application of the resin. . The temperature at this time is desirably such that the curing reaction of the thermosetting resin 6 does not proceed so much, and is preferably about 60 ° C to 100 ° C. It is also effective to modify the surface of the printed wiring board 3 by surface treatment such as plasma before placing it on the stage 8 to improve wettability.
【００２８】次に、図２（ｂ）に示すように、プリント
配線基板３上の半導体装置１搭載位置に熱硬化性樹脂６
をディスペンサ−等により塗布する。塗布形状は、中央
部分に１点塗布する方法が一般的であるが、半導体装置
１搭載位置の対角線上に「×」を描くように塗布する方
法、数点に分けて塗布する方法等がある。Next, as shown in FIG. 2B, the thermosetting resin 6 is placed on the printed wiring board 3 at the mounting position of the semiconductor device 1.
Is applied with a dispenser or the like. The application shape is generally a method of applying a single point to the center portion, but there are a method of applying an “x” on a diagonal line of the mounting position of the semiconductor device 1 and a method of applying the application in several points. .
【００２９】次に、図２（ｃ）に示すように、ツ−ル７
に吸着された半導体装置１をプリント配線基板３上に位
置合わせした後、ツ−ル７に内蔵された加熱ヒ−タによ
り、半導体装置１を加熱する。加熱の目的は、半導体装
置１のバンプ２と熱硬化性樹脂６とが接触した際に、接
触した熱硬化性樹脂６の粘度を瞬時に低下させ、バンプ
２へ濡れやすくさせる為であり、この作用により半導体
装置１搭載時にバンプ２間の凹部の空気が取り残されて
ボイドになることを未然に防いでいる。この時のツ−ル
７の加熱温度は１５０℃以上であることが望ましい。ま
た半導体装置１は、ツ−ル７に吸着する前にプラズマ等
の表面処理により、表面改質することも有効である。Next, as shown in FIG.
After the semiconductor device 1 adsorbed on the substrate is positioned on the printed wiring board 3, the semiconductor device 1 is heated by a heating heater built in the tool 7. The purpose of the heating is to, when the bump 2 of the semiconductor device 1 comes into contact with the thermosetting resin 6, to instantaneously reduce the viscosity of the thermosetting resin 6 in contact with the thermosetting resin 6 so that the bump 2 can be easily wetted. This prevents the air in the recess between the bumps 2 from being left behind when the semiconductor device 1 is mounted, thereby preventing a void. The heating temperature of the tool 7 at this time is desirably 150 ° C. or higher. It is also effective to modify the surface of the semiconductor device 1 by a surface treatment such as plasma before it is adsorbed on the tool 7.
【００３０】また、使用する熱硬化性樹脂６にフィラ−
を添加する場合、その添加量が５０％以上になると加熱
時の樹脂粘度が低下しにくくなり、半導体装置１の加熱
によるボイド防止効果が薄れる為、半導体装置１の加熱
と同時に半導体装置１と熱硬化性樹脂６とが接触する直
前に、半導体装置１の搭載速度を減速させると効果があ
る。この場合の搭載速度は１０ｍｍ／ｓ以下が効果的で
ある。ツ−ル７の搭載速度を制御する方法として、半導
体装置１と熱硬化性樹脂６とが接触する直前に一度停止
させてもよい。The thermosetting resin 6 used is filled with a filler.
When the addition amount is 50% or more, the resin viscosity during heating is less likely to decrease, and the effect of preventing voids due to heating of the semiconductor device 1 is weakened. It is effective to reduce the mounting speed of the semiconductor device 1 immediately before the curable resin 6 comes into contact with the resin. It is effective that the mounting speed in this case is 10 mm / s or less. As a method of controlling the mounting speed of the tool 7, the tool 7 may be stopped once immediately before the semiconductor device 1 comes into contact with the thermosetting resin 6.
【００３１】次に、図２（ｄ）に示すように、半導体装
置１に対して所定の荷重をかけ、はんだ融点以上に昇温
する事で電極部のはんだ接続を行なう。この際、熱硬化
性樹脂６に付与されているはんだ酸化膜除去作用も加わ
り、短時間で確実なはんだ結合が行なわれる。このと
き、熱硬化性樹脂６は硬化反応がほとんど進んでいない
状態であるため、樹脂粘度は十分に低くはんだ接続を阻
害することはない。なお、半導体装置１に加える荷重は
半導体装置１のサイズやバンプ２のピッチ、サイズ、数
などにより異なるが、目安として１バンプあたり０．１
〜５ｇ程度が望ましく、加熱温度ははんだ融点温度より
２０〜５０℃高いことが望ましく、この条件にてはんだ
接続を行なう時間は、３〜１０秒程度が望ましい。Next, as shown in FIG. 2 (d), a predetermined load is applied to the semiconductor device 1, and the temperature is raised to a temperature equal to or higher than the melting point of the solder, so that the electrodes are connected by soldering. At this time, the effect of removing the solder oxide film applied to the thermosetting resin 6 is also added, so that a reliable solder connection can be performed in a short time. At this time, the thermosetting resin 6 is in a state in which the curing reaction has hardly progressed, so that the resin viscosity is sufficiently low and does not hinder the solder connection. The load applied to the semiconductor device 1 varies depending on the size of the semiconductor device 1 and the pitch, size, and number of the bumps 2.
The heating temperature is desirably 20 to 50 ° C. higher than the melting point of the solder, and the solder connection time under these conditions is desirably about 3 to 10 seconds.
【００３２】また、半導体装置１をプリント配線基板３
に搭載する際に、振動を加えながら加熱して搭載し、電
気的接続を行う方法を用いれば、熱硬化性樹脂６にはん
だ酸化膜除去作用を添加する必要が無くなる。The semiconductor device 1 is connected to a printed circuit board 3
When a method is used in which the thermosetting resin 6 is heated and mounted while applying vibration to make an electrical connection, it is not necessary to add a function of removing a solder oxide film to the thermosetting resin 6.
【００３３】次に、はんだ接続が完了した上記実装品の
熱硬化性樹脂６を硬化させるが、樹脂を完全に硬化させ
る手段としては、はんだ接続を行った後の実装品を複数
個まとめて樹脂硬化可能な温度雰囲気に保たれた恒温槽
等に移して行なうと良い。これにより、個々の搭載サイ
クルタイムははんだ接続に必要な時間のみで良いため、
時間の短縮が可能となり、かつ一定の樹脂硬化時間で複
数個の半導体装置１の樹脂硬化が可能となるため、生産
性が向上する。Next, the thermosetting resin 6 of the above-mentioned mounted product, to which the solder connection is completed, is cured. As means for completely curing the resin, a plurality of mounted products after the solder connection has been made are put together. It is preferable to transfer to a constant temperature bath or the like which is kept in a temperature atmosphere capable of curing. As a result, each mounting cycle time only needs to be the time required for solder connection,
Since the time can be reduced and the resin of the plurality of semiconductor devices 1 can be cured in a fixed resin curing time, the productivity is improved.
【００３４】図１に、実装が完了した本実施の形態の一
例として、バンプ２にはんだバンプを用いて製作した場
合のフリップチップ実装構造体の断面図を示す。図１に
おいて、配線基板３のパッド４上にプリコ−トされたは
んだ５と半導体装置１の突起電極であるバンプ２とがそ
れぞれ対応する位置にて金属接合されることで、半導体
装置１と配線基板３の電気的接続が行われている。半導
体装置１と配線基板３の間の封止樹脂は、熱硬化性樹脂
６で構成されている。FIG. 1 shows a cross-sectional view of a flip-chip mounting structure manufactured by using solder bumps for the bumps 2 as an example of the present embodiment in which mounting is completed. In FIG. 1, a solder 5 pre-coated on a pad 4 of a wiring board 3 and a bump 2 which is a protruding electrode of the semiconductor device 1 are metal-bonded at corresponding positions, thereby connecting the semiconductor device 1 to the wiring. The electrical connection of the substrate 3 is made. The sealing resin between the semiconductor device 1 and the wiring board 3 is made of a thermosetting resin 6.
【００３５】はんだ５の材質の例としてはＳｎ／Ｐｂ共
晶はんだがあるが、Ｓｎ／Ｐｂ共晶はんだに限定され
ず、たとえばＳｎ／Ｐｂ（共晶を除く）、Ｓｎ／Ａｇ、
Ｓｎ／Ｃｕ、Ｓｎ／Ｓｂ、Ｓｎ／Ｚｎ、Ｓｎ／Ｂｉおよ
びこれら前記した材料に特定の添加元素をさらに加えた
材料を挙げることができ、これらが適宜用いられる。ま
た、バンプ２ははんだ５と同じでも異なる材質であって
もよく、融点の異なるはんだであっても良い。よく用い
られる材料はＰｂリッチなＳｎ／Ｐｂがあげられる。異
なる材質の一例としてはＡｕバンプがあげられる。Examples of the material of the solder 5 include Sn / Pb eutectic solder, but are not limited to Sn / Pb eutectic solder. For example, Sn / Pb (excluding eutectic), Sn / Ag,
Examples thereof include Sn / Cu, Sn / Sb, Sn / Zn, Sn / Bi, and materials obtained by further adding a specific additive element to these materials, and these are appropriately used. Further, the bump 2 may be the same or a different material from the solder 5, or may be a solder having a different melting point. A frequently used material is Pb-rich Sn / Pb. An example of a different material is an Au bump.
【００３６】また、電気的接続部を除く半導体装置１と
配線基板３の間は、電気的接続部を保護すると共に、半
導体装置１と配線基板３の熱膨張係数の違いにより生じ
る熱応力が電気的接続部に集中することを緩和し、接続
信頼性を向上させる目的で熱硬化性樹脂６により樹脂封
止されている。In addition, between the semiconductor device 1 and the wiring board 3 excluding the electrical connection portion, the electrical connection portion is protected, and the thermal stress generated due to the difference in the thermal expansion coefficient between the semiconductor device 1 and the wiring board 3 is changed. The resin is sealed with a thermosetting resin 6 for the purpose of relieving concentration on the connection part and improving connection reliability.
【００３７】熱硬化性樹脂６は、はんだ接続を行なう場
合、活性樹脂（はんだ酸化膜を除去する効果がある熱硬
化性樹脂）を用いることが望ましい。例えば、基材とな
る熱硬化性樹脂６にフラックス効果を有する剤を添加し
た構成であり、はんだおよび被はんだ接続面の酸化膜を
除去する作用を持つ。すなわち、はんだ接続での硬化前
の加熱状態において、フラックス作用を有する剤が作用
し、はんだおよび被はんだ接続面の酸化膜が除去され
る。活性樹脂は、硬化後は基材樹脂と結合することによ
り化学的に安定となり、十分な電気的絶縁性を有する。As for the thermosetting resin 6, it is desirable to use an active resin (a thermosetting resin having an effect of removing a solder oxide film) when performing solder connection. For example, it has a configuration in which an agent having a flux effect is added to the thermosetting resin 6 serving as a base material, and has a function of removing an oxide film on a solder and a connection surface to be soldered. That is, in the heating state before curing in the solder connection, the agent having the flux action acts, and the solder and the oxide film on the connection surface to be soldered are removed. After being cured, the active resin becomes chemically stable by bonding to the base resin, and has sufficient electrical insulation.
【００３８】また、熱硬化性樹脂６にフラックス作用を
与えるには、（メタ）アクリル酸、マレイン酸などの不
飽和酸、蓚酸、マロン酸などの有機二酸、クエン酸など
の有機酸をはじめ、炭化水素の側鎖に、ハロゲン基、水
酸基、ニトリル基、ベンジル基、カルボキシル基等を少
なくとも１つ以上を添加することにより可能である。ま
た、(メタ)アクリルアルコールなどの不飽和アルコー
ル、トリメリット酸、テトラメリット酸および一般的に
知られているキレート剤を用いることもできる。このよ
うな前記フラックス作用を有する剤は、二種以上組合せ
て用いることができる。なお、フラックスには、公知の
ゲル化剤を含むこともできる。In order to impart a flux effect to the thermosetting resin 6, an unsaturated acid such as (meth) acrylic acid and maleic acid, an organic diacid such as oxalic acid and malonic acid, and an organic acid such as citric acid can be used. It is possible by adding at least one or more of a halogen group, a hydroxyl group, a nitrile group, a benzyl group, a carboxyl group and the like to the side chain of the hydrocarbon. Unsaturated alcohols such as (meth) acrylic alcohol, trimellitic acid, tetramellitic acid, and generally known chelating agents can also be used. Such agents having a flux action can be used in combination of two or more. The flux may contain a known gelling agent.
【００３９】また、半導体装置実装工程においては、熱
硬化性樹脂６に活性樹脂を使用することで、フラックス
を使用する必要が無くなるため、フラックス洗浄工程を
省略でき、また、洗浄不良によって生じるフラックス残
渣に起因する信頼性への悪影響を防止することができ
る。In the semiconductor device mounting step, the use of an active resin for the thermosetting resin 6 eliminates the need for using a flux, so that the flux cleaning step can be omitted, and the flux residue generated due to poor cleaning can be eliminated. Can prevent adverse effects on reliability.
【００４０】熱硬化性樹脂の基材としては、エポキシ、
ポリエステル（不飽和ポリエステル、不飽和ポリエステ
ルと活性水素基を有する化合物の組合せなど）、アクリ
レート（（メタ）アクリロキシプロピルポリシロキサン
などのシリコンアクリレート、エポキシアクリレートを
含む）などである。熱硬化時に前記した熱硬化性樹脂と
反応して硬化を促進する促進剤、および／または硬化剤
（加熱によって硬化するためのラジカル等が発生するラ
ジカル開始剤、アニオン開始剤またはカチオン開始剤）
等を有している。なお、αーシアノアクリレートなどの
常温で硬化する接着剤等を用いることもできる。前記熱
硬化性樹脂、促進剤、硬化剤および開始剤等は、２種以
上、組合せて用いることができる。さらに、熱硬化性樹
脂には、熱膨張係数等を調整し接続信頼性を向上させる
目的でシリカ等のフィラ−を添加しても良い。As the base material of the thermosetting resin, epoxy,
Polyesters (such as unsaturated polyesters, combinations of unsaturated polyesters and compounds having active hydrogen groups), acrylates (including silicone acrylates such as (meth) acryloxypropylpolysiloxane, and epoxy acrylates); An accelerator which reacts with the above-mentioned thermosetting resin at the time of heat curing to accelerate the curing, and / or a curing agent (a radical initiator, an anionic initiator or a cationic initiator which generates radicals or the like for curing by heating)
Etc. Note that an adhesive that cures at room temperature, such as α-cyanoacrylate, can also be used. The thermosetting resin, accelerator, curing agent, initiator and the like can be used in combination of two or more. Further, a filler such as silica may be added to the thermosetting resin for the purpose of adjusting the coefficient of thermal expansion and the like and improving the connection reliability.
【００４１】なお、バンプ形成された半導体装置１を短
時間で確実にはんだ接続させる為に、搭載時に加熱とと
もに加圧を行なったり、振動によりはんだ接続させるこ
ともできる。In order to securely connect the semiconductor device 1 on which the bumps are formed in a short time, it is also possible to apply pressure while heating or to connect the solder by vibration during mounting.
【００４２】図３は、プリント配線基板３上に予備はん
だが形成されていない場合のはんだバンプを用いた本発
明の実施の形態を示す図である。実装方法に関しては図
２で示した例と同様であるが、この場合、加熱加圧時に
バンプ２を潰してしまわないように、半導体装置１と配
線基板３との隙間を一定に保つような位置制御を行なう
必要がある。FIG. 3 is a view showing an embodiment of the present invention using solder bumps when no preliminary solder is formed on the printed wiring board 3. The mounting method is the same as the example shown in FIG. 2, but in this case, a position where the gap between the semiconductor device 1 and the wiring board 3 is kept constant so as not to crush the bumps 2 during heating and pressing. Control is needed.
【００４３】[0043]
【実施例】上記した本発明の実施の形他についてさらに
詳細に説明すべく、本発明の実施例について図面を参照
して説明する。本実施例では、上記実装方法により、半
導体装置を熱硬化性樹脂が塗布された配線基板上に搭載
する際に、半導体装置側の突起電極間凹部の外気が抜け
きれずに残り、ボイドとなる不具合が発生しないことを
確認するとともに、その際の接続信頼性を確認するため
以下の実験を行なった。まず、使用機材について説明す
る。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; In this embodiment, when the semiconductor device is mounted on the wiring substrate coated with the thermosetting resin by the above-described mounting method, the outside air in the concave portion between the protruding electrodes on the semiconductor device side remains without being able to escape and becomes a void. The following experiment was conducted to confirm that no failure occurred and to confirm the connection reliability at that time. First, the equipment used will be described.
【００４４】半導体装置１は、サイズ１０ｍｍ□であ
り、はんだバンプが０．２４ｍｍピッチで半導体装置１
表面全面に配置されているフルグリッドエリア配置であ
る。はんだバンプ材質はＰｂ９５％、Ｓｎ５％である。
配線基板３は、半導体装置１に対応した電極が配置され
ており、パッド４上には予備はんだが約２０μｍの高さ
で形成されている。予備はんだ材質は共晶はんだであ
る。なお、実装後の半導体装置１と配線基板３は電気的
接続の確認が行なえる構造となっている。The semiconductor device 1 is 10 mm square in size, and has a solder bump pitch of 0.24 mm.
This is a full grid area arrangement arranged on the entire surface. The solder bump material is Pb 95% and Sn 5%.
Electrodes corresponding to the semiconductor device 1 are arranged on the wiring board 3, and preliminary solder is formed on the pads 4 at a height of about 20 μm. The preliminary solder material is eutectic solder. The semiconductor device 1 and the wiring board 3 after mounting have a structure in which electrical connection can be confirmed.
【００４５】熱硬化性樹脂６はエポキシであり、フェノ
−ル系硬化剤を使用した樹脂Ａと酸無水物系硬化剤を使
用した樹脂Ｂを用い、共にはんだ酸化膜除去作用を有す
る樹脂である。さらにこれらの樹脂にシリカフィラ−を
添加したものについても評価を行なった。ここで、熱硬
化性樹脂６は、エポキシに限られるものではなく、上述
したように、ポリエステルやアクリレートなどでも良
い。The thermosetting resin 6 is an epoxy resin, which is a resin A using a phenol-based curing agent and a resin B using an acid anhydride-based curing agent, both of which have a solder oxide film removing action. . Further, those obtained by adding silica filler to these resins were also evaluated. Here, the thermosetting resin 6 is not limited to epoxy, but may be polyester or acrylate as described above.
【００４６】次に、実装方法について説明する。Next, a mounting method will be described.
【００４７】まず、半導体装置１にＡｒプラズマ処理を
行い、プラズマの表面改質効果による半導体装置１と樹
脂６の濡れ性向上及びはんだバンプ２の接続性向上を図
った。続いて、配線基板３をステ−ジ８上に置き、ディ
スペンサ−により熱硬化性樹脂６を配線基板３上の半導
体装置１が搭載される中央部に約２０ｍｇ塗布した。続
いて、半導体装置１をツ−ル７に吸着し、配線基板３と
の位置合わせを行ない、半導体装置１を配線基板３上に
搭載し、半導体装置１のはんだバンプ２と配線基板３の
予備はんだ５が接触後、半導体装置１を２３０℃に加熱
しながら３ｇ／バンプの加圧を５秒間行ない、電極間の
はんだ接続をした。なお、接続の際、加圧を行なわない
方法も試みたが、この場合、フィラー添加量４０％以上
の樹脂は、ほとんどの接続部ではんだ濡れ不良が発生
し、未接続となった。First, an Ar plasma treatment was performed on the semiconductor device 1 to improve the wettability between the semiconductor device 1 and the resin 6 and the connectivity between the solder bumps 2 by the surface modification effect of the plasma. Subsequently, the wiring board 3 was placed on the stage 8, and about 20 mg of the thermosetting resin 6 was applied to the center of the wiring board 3 on which the semiconductor device 1 was mounted by a dispenser. Subsequently, the semiconductor device 1 is attracted to the tool 7, the alignment with the wiring substrate 3 is performed, the semiconductor device 1 is mounted on the wiring substrate 3, and the solder bumps 2 of the semiconductor device 1 and the spare of the wiring substrate 3 are prepared. After the solder 5 came into contact, 3 g / bump was pressed for 5 seconds while the semiconductor device 1 was heated to 230 ° C. to make a solder connection between the electrodes. Attempts were also made to apply no pressure at the time of connection. In this case, however, the resin with an added amount of filler of 40% or more suffered poor solder wetting at most of the connection portions and was not connected.
【００４８】続いて、はんだ接続の完了した実装品を１
５０℃大気雰囲気中の恒温槽に９０分間入れて、熱硬化
性樹脂６の硬化を行ない実装を完了した。Subsequently, the soldered product having completed the soldering is
The thermosetting resin 6 was placed in a thermostat in an air atmosphere at 50 ° C. for 90 minutes to cure the thermosetting resin 6 to complete the mounting.
【００４９】半導体装置搭載時のボイド評価として、半
導体装置１の搭載速度とステ−ジ８及びツ−ル７の温度
条件を変えて比較評価を行なった。本実施例で使用した
樹脂における温度と樹脂粘度の関係を、表１に示す。２
５℃に比べ５０℃ではかなり樹脂粘度が低下しており、
７０℃近傍から昇温に連れて急に樹脂粘度が低下してい
る事がわかる。As a void evaluation when the semiconductor device was mounted, a comparative evaluation was performed by changing the mounting speed of the semiconductor device 1 and the temperature conditions of the stage 8 and the tool 7. Table 1 shows the relationship between the temperature and the resin viscosity of the resin used in this example. 2
At 50 ° C compared to 5 ° C, the resin viscosity is considerably lower,
It can be seen that the viscosity of the resin suddenly decreases from around 70 ° C. as the temperature rises.
【００５０】評価条件詳細および結果として、表２は常
温で搭載速度が速い従来条件に対して搭載速度を遅く
し、ツ−ル温度及びステ−ジ温度を変化させたときのボ
イド観察結果、表３は表２の条件でボイドが発生しなか
った温度条件に関して、樹脂にフィラ−添加し、搭載速
度を速くしたときのボイド観察結果を示す。ボイドの観
察方法としては、実装が完了したサンプルについて、樹
脂層部分の断面を顕微鏡で観察した。As details of the evaluation conditions and the results, Table 2 shows the void observation results when the mounting speed was reduced and the tool temperature and the stage temperature were changed with respect to the conventional conditions in which the mounting speed was high at room temperature. 3 shows the results of observation of voids when filler was added to the resin and the mounting speed was increased under the temperature conditions in which no voids were generated under the conditions in Table 2. As a method for observing voids, a cross section of the resin layer portion was observed with a microscope for a sample after mounting was completed.
【００５１】また、それぞれの搭載時の加熱及びツ−ル
変位を示すプロファイル図を図４乃至図６に示す。な
お、表２又は表３の搭載プロファイル欄の番号と図４乃
至図６の番号とが対応している。図４乃至図６に示す
は、はんだバンプと熱硬化性樹脂とが接触した時点であ
り、ははんだバンプと基板（基板上のパッド）とが接
触した時点である。また、ツール温度は、以降はんだ
バンプの融点以上の温度に上昇されている。表２および
表３において、ツール温度は、はんだバンプと熱硬化性
樹脂が接触した時点での温度である。FIG. 4 to FIG. 6 are profile diagrams showing heating and tool displacement at the time of mounting, respectively. The numbers in the mounting profile column in Table 2 or Table 3 correspond to the numbers in FIGS. FIGS. 4 to 6 show the time when the solder bumps and the thermosetting resin are in contact, and the time when the solder bumps and the substrate (pads on the substrate) are in contact. The tool temperature has been raised to a temperature equal to or higher than the melting point of the solder bump. In Tables 2 and 3, the tool temperature is the temperature at the time when the solder bump and the thermosetting resin are in contact with each other.
【００５２】[0052]
【表１】 [Table 1]
【００５３】[0053]
【表２】 [Table 2]
【００５４】[0054]
【表３】 [Table 3]
【００５５】表２に関して、ツール及びステージを常温
にて４０ｍｍ／ｓで搭載した従来条件の場合は、封止樹
脂全面に多数発生した。これに対し、半導体装置と樹脂
が接触する直前に搭載速度を０．１ｍｍ／ｓと遅くした
場合、ボイドが減っていることは確認できたが、主に樹
脂塗布した中央部分にはボイドが残っており、完全にボ
イドを無くすまでには至らなかった。さらにツール及び
ステージ温度を変化させていくと、ツール温度１５０
℃、ステージ温度６０℃以下のときボイドが発生しなか
った。Referring to Table 2, in the case of the conventional condition in which the tool and the stage were mounted at room temperature at 40 mm / s, many occurred on the entire surface of the sealing resin. On the other hand, when the mounting speed was reduced to 0.1 mm / s immediately before the resin contacted with the semiconductor device, it was confirmed that the voids were reduced, but the voids remained mainly in the central portion where the resin was applied. And did not lead to complete elimination of voids. When the tool and stage temperatures are further changed, the tool temperature 150
When the temperature was lower than 60 ° C and the stage temperature was lower than 60 ° C, no void was generated.
【００５６】次に、表３に示すように、ボイドが発生し
なかったツール温度１５０℃、ステージ温度６０℃の温
度条件において、再び搭載速度を４０ｍｍ／ｓとし、樹
脂にシリカフィラーを添加したものを含め、ボイド観察
を行なった。結果はフィラー添加量４０％まではボイド
が発生しなかったが、フィラー添加量６０％の場合、ボ
イドが発生した。そこでフィラー添加量６０％について
は、この温度条件のまま搭載速度を１０ｍｍ／ｓとする
とボイドが発生しなかった。Next, as shown in Table 3, under the conditions of a tool temperature of 150 ° C. and a stage temperature of 60 ° C. where no voids were generated, the mounting speed was again set to 40 mm / s, and the resin was filled with silica filler. And void observation was performed. As a result, no void was generated up to the filler addition amount of 40%, but voids were generated at the filler addition amount of 60%. Therefore, for the filler addition amount of 60%, no void was generated when the mounting speed was set to 10 mm / s under these temperature conditions.
【００５７】この結果から、フィラ−添加量が４０％以
下の樹脂に関しては、半導体装置１側を配線基板３側よ
り高い温度で加熱しておき、半導体装置１に熱硬化性樹
脂６が接触した際、半導体装置１側に熱硬化性樹脂６が
濡れやすくなる状況を作り出す本実装方法を行なうこと
で、半導体装置１搭載時のボイドを未然に防げることを
確認した。ここで、ツール温度は、１５０℃としたが、
ツール温度は、基板３よりも高い温度であれば、半導体
装置１の搭載速度と使用する熱硬化性樹脂６の温度によ
る樹脂粘度の変化によって変える事が可能である事はも
ちろんである。From these results, it was found that the semiconductor device 1 was heated at a higher temperature than that of the wiring substrate 3 for the resin having a filler content of 40% or less, and the thermosetting resin 6 was brought into contact with the semiconductor device 1. At this time, it was confirmed that by performing this mounting method that creates a situation in which the thermosetting resin 6 is easily wetted on the semiconductor device 1 side, it is possible to prevent voids when the semiconductor device 1 is mounted. Here, the tool temperature was 150 ° C.,
As long as the temperature of the tool is higher than that of the substrate 3, it is of course possible to change the tool temperature by changing the resin viscosity depending on the mounting speed of the semiconductor device 1 and the temperature of the thermosetting resin 6 to be used.
【００５８】また、フィラ−添加量の割合が多く樹脂粘
度が４０Ｐａ・s（２５℃の時）以上の樹脂は半導体装
置側の加熱と共に搭載速度を減速させることで、半導体
装置搭載時のボイドを未然に防げることを確認した。ま
た、これらのサンプルのうち、フィラー添加量４０％以
上のものについて−４０℃〜１２５℃の温度サイクル試
験を行い接続信頼性を評価した結果、樹脂Ａ，Ｂ共に１
０００サイクル以上接続信頼性が確保できていることを
確認した。この結果から、本発明の実装方法により、樹
脂層にボイドが無く接続信頼性が高い実装品が得られる
ことを確認した。In the case of a resin having a high filler addition ratio and a resin viscosity of 40 Pa · s (at 25 ° C.) or more, the mounting speed is reduced together with the heating of the semiconductor device to reduce the voids when the semiconductor device is mounted. I confirmed that it could be prevented beforehand. Further, among these samples, those having a filler addition amount of 40% or more were subjected to a temperature cycle test at −40 ° C. to 125 ° C. to evaluate the connection reliability.
It was confirmed that connection reliability could be secured for 000 cycles or more. From these results, it was confirmed that the mounting method of the present invention can provide a mounted product having no voids in the resin layer and high connection reliability.
【００５９】[0059]
【発明の効果】以上説明したように、本発明の半導体装
置の実装方法によれば、配線基板上に熱硬化性樹脂を塗
布後、半導体装置を配線基板上に搭載するに際し、半導
体装置と熱硬化性樹脂とが接触する前に、半導体装置を
少なくとも配線基板より高い温度で加熱、又は、半導体
装置の搭載速度を減速又は一旦停止、又はこれらを組み
合わせて、半導体装置側に熱硬化性樹脂を濡れやすくす
ることにより、樹脂層に発生しやすいボイドを未然に防
ぐとともに、シリカフィラ−を添加し、熱膨張係数を調
整した熱硬化性樹脂を用いてもはんだ接続を行うことが
でき、接続信頼性の高い実装品を得る事ができる。As described above, according to the semiconductor device mounting method of the present invention, the thermosetting resin is applied on the wiring substrate, and then, when the semiconductor device is mounted on the wiring substrate, the semiconductor device and the semiconductor device are connected to each other. Before the curable resin comes into contact, the semiconductor device is heated at least at a higher temperature than the wiring board, or the mounting speed of the semiconductor device is reduced or temporarily stopped, or a combination thereof, and the thermosetting resin is provided on the semiconductor device side. By making it easy to wet, voids that are likely to occur in the resin layer are prevented beforehand, and solder connection can be performed even if a thermosetting resin with a thermal expansion coefficient adjusted by adding silica filler is used. It is possible to obtain a high-performance mounted product.
【図１】本発明の実装方法により実装したフリップチッ
プ実装構造体を示す断面図である。FIG. 1 is a cross-sectional view showing a flip-chip mounting structure mounted by a mounting method of the present invention.
【図２】配線基板に予備はんだが形成された場合におけ
る本発明の実装方法を示す工程断面図である。FIG. 2 is a process cross-sectional view showing a mounting method of the present invention when a preliminary solder is formed on a wiring board.
【図３】配線基板に予備はんだが形成されていない場合
における本発明の実装方法を示す工程断面図である。FIG. 3 is a process cross-sectional view showing a mounting method of the present invention when no preliminary solder is formed on a wiring board;
【図４】半導体装置搭載時の加熱及びツ−ル変位を示す
プロファイル図である。FIG. 4 is a profile diagram showing heating and tool displacement when a semiconductor device is mounted.
【図５】半導体装置搭載時の加熱及びツ−ル変位を示す
プロファイル図である。FIG. 5 is a profile diagram showing heating and tool displacement when a semiconductor device is mounted.
【図６】半導体装置搭載時の加熱及びツ−ル変位を示す
プロファイル図である。FIG. 6 is a profile diagram showing heating and tool displacement when a semiconductor device is mounted.
【図７】従来のフラックスによるはんだ接合を行なった
場合の実装方法を示す工程断面図である。FIG. 7 is a process cross-sectional view showing a mounting method when soldering is performed by using a conventional flux.
【図８】従来の配線基板に樹脂塗布して半導体装置を搭
載する実装方法を示す工程断面図である。FIG. 8 is a process cross-sectional view showing a mounting method of mounting a semiconductor device by applying a resin to a conventional wiring board.
１ 半導体装置 ２ バンプ ３ 配線基板 ４ パッド(配線基板) ５ はんだ ６ 熱硬化性樹脂 ７ ツ−ル ８ ステ−ジ ９ パッド（半導体装置） １０ フラックス DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Bump 3 Wiring board 4 Pad (wiring board) 5 Solder 6 Thermosetting resin 7 Tool 8 Stage 9 Pad (semiconductor device) 10 Flux
Claims (9)
ンプを介して電気的に接続され、前記半導体装置と前記
配線基板との間を熱硬化性樹脂により封止してなる半導
体装置の実装方法において、 前記配線基板上に熱硬化性樹脂を塗布する工程と、前記
半導体装置を前記配線基板上に搭載するに際し、前記半
導体装置と前記熱硬化性樹脂とが接触する前に、前記半
導体装置を少なくとも前記配線基板より高い温度で加熱
する予備加熱工程と、前記半導体装置の電極と前記配線
基板の電極とが前記バンプを介して接触した状態で、前
記半導体装置を前記予備加熱工程以上の温度に加熱して
前記半導体装置の電極と前記配線基板間の電極とを電気
的に接続するバンプ接続工程と、前記半導体装置の搭載
が完了した前記配線基板を、前記バンプ接続工程以下の
温度雰囲気中に保持し、前記熱硬化性樹脂を硬化させる
樹脂硬化工程と、を含むこと特徴とする半導体装置の実
装方法。An electrode of a semiconductor device, wherein an electrode of the semiconductor device and an electrode of a wiring substrate are electrically connected via bumps, and the space between the semiconductor device and the wiring substrate is sealed with a thermosetting resin. In the mounting method, a step of applying a thermosetting resin on the wiring board, and when mounting the semiconductor device on the wiring board, before the semiconductor device contacts the thermosetting resin, the semiconductor A preheating step of heating the device at a temperature higher than at least the wiring board; and, in a state where the electrodes of the semiconductor device and the electrodes of the wiring board are in contact with each other via the bumps, the semiconductor device is subjected to the preheating step or more. A bump connection step of electrically connecting the electrodes of the semiconductor device and the electrodes between the wiring boards by heating to a temperature; and connecting the wiring board on which the semiconductor device is mounted to the bump connection. A resin curing step of keeping the thermosetting resin in a temperature atmosphere following the step and curing the thermosetting resin.
るに際し、前記半導体装置と前記配線基板上に塗布され
た前記熱硬化性樹脂とが接触する直前に、前記半導体装
置を載置するツールの移動速度を減速、又は、一旦停止
させることを特徴とする請求項１に記載の半導体装置の
実装方法。2. A tool for mounting the semiconductor device immediately before the semiconductor device comes into contact with the thermosetting resin applied on the wiring substrate when the semiconductor device is mounted on the wiring substrate. 2. The method according to claim 1, wherein the moving speed of the semiconductor device is reduced or temporarily stopped.
の温度を前記熱硬化性樹脂の濡れ性を改善可能な第１の
温度に設定し、前記半導体装置の温度を前記第１の温度
以上、前記バンプの溶融温度以下の第２の温度に設定す
ることを特徴とする請求項１又は２に記載の半導体装置
の実装方法。3. In the preheating step, the temperature of the wiring substrate is set to a first temperature at which the wettability of the thermosetting resin can be improved, and the temperature of the semiconductor device is equal to or higher than the first temperature. 3. The method according to claim 1, wherein the second temperature is set equal to or lower than a melting temperature of the bump. 4.
前記第２の温度が、略１５０℃以上に設定されることを
特徴とする請求項３に記載の半導体装置の実装方法。4. The method according to claim 1, wherein the first temperature is approximately 60 to 100 ° C.
The method according to claim 3, wherein the second temperature is set to approximately 150 ° C. or higher.
ンプを介して電気的に接続され、前記半導体装置と前記
配線基板との間を熱硬化性樹脂により封止してなる半導
体装置の実装方法において、 前記配線基板上に熱硬化性樹脂を塗布する工程と、前記
半導体装置を前記配線基板上に搭載するに際し、前記半
導体装置と前記熱硬化性樹脂とが接触する前に、前記半
導体装置を載置するツールの移動速度を減速又は一旦停
止させる工程と、前記半導体装置の電極と前記配線基板
の電極とが前記バンプを介して接触した状態で、前記半
導体装置を加熱して前記半導体装置の電極と前記配線基
板間の電極とを電気的に接続するバンプ接続工程と、前
記半導体装置の搭載が完了した前記配線基板を、前記バ
ンプ接続工程以下の温度雰囲気中に保持し、前記熱硬化
性樹脂を硬化させる樹脂硬化工程と、を含むこと特徴と
する半導体装置の実装方法。5. The semiconductor device according to claim 1, wherein an electrode of the semiconductor device is electrically connected to an electrode of the wiring substrate via a bump, and the space between the semiconductor device and the wiring substrate is sealed with a thermosetting resin. In the mounting method, a step of applying a thermosetting resin on the wiring board, and when mounting the semiconductor device on the wiring board, before the semiconductor device contacts the thermosetting resin, the semiconductor A step of reducing or temporarily stopping a moving speed of a tool for mounting the device, and heating the semiconductor device while the electrodes of the semiconductor device and the electrodes of the wiring board are in contact with each other via the bumps, thereby heating the semiconductor device. A bump connection step of electrically connecting an electrode of the device and an electrode between the wiring boards, and holding the wiring board on which the mounting of the semiconductor device is completed, in a temperature atmosphere equal to or lower than the bump connection step; A resin curing step of curing the thermosetting resin.
触する前における前記ツールの移動速度が、略１０ｍｍ
／ｓ以下に設定されることを特徴とする請求項５に記載
の半導体装置の実装方法。6. The moving speed of the tool before the semiconductor device and the thermosetting resin come into contact with each other is approximately 10 mm.
6. The method according to claim 5, wherein the value is set to not more than / s.
する際に、前記配線基板を加熱しながら塗布することを
特徴とする請求項１乃至６のいずれか一に記載の半導体
装置の実装方法。7. The semiconductor device according to claim 1, wherein, when the thermosetting resin is applied on the wiring board, the thermosetting resin is applied while heating the wiring board. Implementation method.
アチップまたはチップサイズパッケージであることを特
徴とする請求項１乃至７のいずれか一に記載の半導体装
置の実装方法。8. The method according to claim 1, wherein the semiconductor device is a bare chip or a chip size package on which bumps are formed.
性樹脂ははんだ酸化膜除去作用を有することを特徴とす
る請求項１乃至８のいずれか一に記載の半導体装置の実
装方法。9. The method according to claim 1, wherein the bump is made of solder, and the thermosetting resin has a function of removing a solder oxide film.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001150645A JP4626839B2 (en) | 2001-05-21 | 2001-05-21 | Mounting method of semiconductor device |
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| JP4626839B2 JP4626839B2 (en) | 2011-02-09 |
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