JP2007059638A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a package thin, while securing a connection reliability at mounting of components on a wiring board by flip-chip bonding. <P>SOLUTION: A pad of a semiconductor chip 1, whereon a bump is formed, is a small pad 3 with a narrow area. After mounting the semiconductor chip 1 on a substrate 2 with a large pad 4 having an area larger than the small pad 3, the bump formed on the small pad becomes a shape so as to be wetted and spread on the large pad 4, that is, the pitch in the gradient of the slope face of a circular truncated cone is made to become gentle gradually. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device in which a semiconductor chip or the like is mounted on a wiring board or the like, and a method for manufacturing the same, and more specifically, a semiconductor device mounting structure in which a semiconductor chip or the like is mounted using solder bumps or solder balls. And its implementation method.

As electric devices become smaller, lighter and more functional, flip chip mounting has been performed as a method for mounting semiconductor chips such as LSI chips. Flip chip mounting is a mounting method in which bumps are formed with solder or the like on electrodes connected to a wiring pattern of a semiconductor chip, and these are bonded to electrodes of a wiring board.
FIG. 6 is a cross-sectional view in order of steps showing a conventional method for manufacturing a semiconductor device. The conventional process will be described. A bump 5 is formed on a chip-side pad 9 of a semiconductor chip 1 such as an LSI, and a flux 8 is attached on the bump tip of the semiconductor chip 1 or on the substrate 2 (FIG. 6A). After the semiconductor chip 1 is aligned and mounted on the wiring substrate 2, reflow is performed to connect the chip-side pad 9 of the semiconductor chip 1 and the substrate-side pad 10 of the wiring substrate 2 [FIG. After cleaning [FIG. 6C], the gap between the semiconductor chip 1 and the wiring board 2 is filled with resin by capillary action, and then cured to form an underfill 7 [FIG. 6D].

  FIG. 7 is a partially enlarged view in which the solder joint portion of FIG. 6 is enlarged. As shown in FIG. 7, the diameters of the chip-side pad 9 and the substrate-side pad 10 are designed with substantially the same dimensions, and the shape of the bump 5 after mounting is a beer barrel shape. That is, the maximum diameter of the bump 5 after mounting is equal to or larger than the diameter of the pads 9 and 10. On the other hand, with the spread of portable devices and the like, it is desired to reduce the thickness of semiconductor devices. One of the means is to reduce the bump volume in order to reduce the gap between the semiconductor chip after mounting and the substrate. However, in the case of the conventional connection structure, if the bump volume is reduced, the volume before the mounting is reduced. The bump height becomes low, and there is a problem that a bump that cannot be in contact with the pad on the substrate side is generated in the mounting process due to the warp of the substrate or the bump height variation, and stable connection cannot be secured.

  In recent years, a mounting method in which bumps are formed on the substrate side and the top heights of the bumps are made uniform has been proposed (for example, see Patent Document 1). FIG. 8 is a cross-sectional view of a wiring board with solder bumps for carrying out this mounting method. As shown in FIG. 8, a plurality of solder joint pads 13 are provided on the electronic component mounting portion A of the warped insulating substrate 11, and each region on the solder joint pad 13 that is not covered with the solder resist film 14 is provided. Solder bumps 15 flattened by polishing are fixed so that their upper ends are substantially flush. That is, in this wiring board with solder bumps, the volume of the solder bumps 5 is large in the region where the height of the electronic component mounting portion A is low, and the volume thereof is small in the region where the height of the electronic component mounting portion A is high. Thereby, the contact of the solder bump to the chip side pad is ensured, and the connection stability is improved.

In addition, as a conventional technique related to flip chip mounting using solder bumps, in order to facilitate non-destructive inspection by X-rays, board-side pads (connection contacts) are replaced with chip-side pads (connection contacts). There has been proposed a method of increasing the solder thickness after reflow soldering so that the solder thickness continuously decreases toward the edge (see, for example, Patent Document 2). In this inspection method, the bump size is greatly deformed at the time of solder bonding by, for example, defining the diameter size ratio of the board-side pad and bump, and the degree of deformation using an X-ray image is evaluated. Destructive inspection is made easier.
JP 2004-165328 A (Claims, FIG. 2) JP-T-2002-524854 (Claims, FIGS. 1 to 3)

However, the semiconductor device disclosed in Patent Document 1 has several problems.
The first problem is that polishing is required to flatten the solder bumps 5 and it takes time and effort. When a warped substrate is fixed during polishing, it is difficult to fix the warped state, and when the warped state is changed by fixing, the solder bumps 5 cannot be flattened. In order to polish as intended, measures including fixing the substrate are required.
The second problem is that the quality is deteriorated by polishing scrap generated by polishing. The polishing scraps adhere to the surface of the solder bump or, in some cases, are buried in the solder bump. When this phenomenon occurs, bonding failure occurs. Moreover, the problem of polishing scraps becomes more prominent as the pitch becomes finer.
In addition, with respect to the method disclosed in Patent Document 2, the bump can be greatly deformed by utilizing the relationship between the pad diameter and the bump diameter and the wettability of the solder bump, but the narrow gap cannot be realized. It is necessary to adjust the gap with a spacer holder or the like described at the end of paragraph [0023] of Patent Document 2, and if the spacer holder is not used, the solder may be crushed depending on the case, and the solder short connected to the adjacent electrode May occur.
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems, and an object of the present invention is to achieve both thinning of a package and stable solder connection in mounting of an electronic device such as a flip chip or a chip size package. A semiconductor device and a manufacturing method thereof are provided.

  In order to achieve the above object, according to the present invention, a first pad formed on a first electronic device and a second pad formed on the second electronic device opposite thereto are soldered. In a semiconductor device electrically connected by a fillet, the second pad is larger than the first pad, and the inclination of the side surface of the solder fillet formed in the shape of a truncated cone or a truncated pyramid is formed on the second pad. There is provided a semiconductor device that is gradually loosened toward the end.

  In order to achieve the above object, according to the present invention, a first pad formed on the first electronic device and a second pad formed on the second electronic device opposite to the first pad are provided. Are electrically connected by solder fillets, the second pad is larger than the first pad, and the surface of the second electronic device on the side facing the first electronic device is the second pad. The solder fillet is covered with an insulating film surrounding the pad, and the volume of the solder fillet is larger than the volume of the truncated cone or the truncated pyramid defined by the thickness of the first pad, the second pad, and the insulating film. A semiconductor device characterized by being small is provided.

  In order to achieve the above object, according to the present invention, a first pad formed in the first electronic device and a larger area than the first pad formed in the second electronic device are provided. In the method of manufacturing a semiconductor device in which the second pad is electrically connected to the solder pad by a substantially truncated cone or truncated pyramid shape, the surface of the second electronic device on which the second pad is formed. Alternatively, a resin application step of applying a resin to the surface of the first electronic device on which the first pad is formed, and a solder terminal formed on the first pad of the first electronic device ( Alignment / Mounting (including solder bumps and solder balls) on the second pads of the second electronic device and mounting the first electronic device on the second electronic device And extent, the method of manufacturing a semiconductor device, characterized in that it comprises a soldering step of said solder terminal is melted wet and spread to the second pad, is provided.

  In order to achieve the above object, according to the present invention, the solder terminal on the first pad formed in the first electronic device is surrounded by the insulating film on the surface of the second electronic device. In the manufacturing method of the semiconductor device connected to the formed second pad having a larger area than the first pad, the solder terminal formed on the first pad of the first electronic device is connected to the second pad. Positioning on the second pad of the electronic device and mounting and mounting the first electronic device on the second electronic device, and melting the solder terminal to form the second pad A soldering step for spreading, wherein a height of the solder terminal is larger than a film thickness of the insulating coating, and a volume of the solder terminal is determined by the first pad, the second pad, and after completion. Between both pads Method of manufacturing a semiconductor device, characterized in that less than a truncated cone or truncated pyramid volume defined by the distance, is provided.

  For example, when an LSI having solder bumps is mounted on a wiring board, according to the present invention, the height of solder bumps (including solder balls) formed on the small pad side before mounting is formed on the board. Solder bumps formed on small pads are secured by making the solder resist film thicker and ensuring that the bumps and large-area pads such as the substrate contact each other during mounting. As a result of wet spreading on the large-area pad, the surface tension of the solder bumps causes a pulling force between the LSI surface and the solder resist film surface of the substrate, and the gap between the LSI and the wiring substrate is reduced until almost in contact. In other words, by reflowing columnar or spherical bumps into a truncated cone shape in which the slope gradually loosens downward, stable connection is possible and the gap between the LSI and the substrate is extremely small. It becomes possible. Therefore, according to the present invention, it is possible to reduce the thickness of the semiconductor package while ensuring connection reliability.

  In addition, by supplying resin for underfill formation between the semiconductor chip and the wiring board in advance before flip chip bonding, the gap is such that the LSI surface and the wiring board surface are almost in contact by the surface tension of the solder bumps. Even when the size of the semiconductor device becomes smaller, it becomes possible to fill the periphery of the bumps and between the minute gaps between the LSI and the substrate with resin, and it is possible to securely seal the electronic device such as a semiconductor chip.

[Construction]
Next, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is an enlarged view of an electrode portion of FIG.
As shown in FIGS. 1 and 2, a small pad 3 having a relatively small area is formed on the surface of the semiconductor chip 1 made of LSI or the like on the circuit forming side, and the substrate 2 which is a wiring board or an interposer is formed on the surface. A large pad 4 having an area larger than that of the small pad 3 is formed. A solder resist film 6 is formed on the surface of the substrate 2 so as to surround the large pad 4. In this specification, a small pad and a large pad are conductive film regions that are not covered with an insulating film such as a solder resist film. The small pads 3 of the semiconductor chip 1 and the large pads 4 of the substrate 2 are electrically connected via bumps 5, and the semiconductor chip 1 is resin-sealed with an underfill 7 surrounding the bumps 5. The bumps 5 are wet and spread on the large pad 4, so that the maximum diameter of the bumps 5 cannot be larger than the diameter of the large pad 4. The gap between the semiconductor chip 1 and the substrate 2 is narrowed by the surface tension of the bump 5 at the time of mounting, and is about the same as or slightly thicker than the solder resist film 6 formed on the substrate 2. In the mounting structure of the present invention, the size of the opposing pads is different, and the bumps formed on the small pads 3 side of the semiconductor chip 1 are wet and spread on the large pads 4 of the substrate 2. The shape of (bump 5) is a Mt. Fuji shape in which the inclined surface of the truncated cone gradually becomes gentle downward.

  In the present invention, the small pad 3 of the semiconductor chip 1 and the large pad 4 of the substrate 2 are bonded via the bumps 5. This bonding is achieved by melting the bumps formed on the small pads 3 of the semiconductor chip 1, This is achieved by spreading on the large pad 4 of the substrate 2. As the bump 5, for example, Sn / Pb eutectic solder, Sn / Pb (excluding eutectic), Sn / Ag, Sn / Cu, Sn / Sb, Sn / Zn, Sn / Bi, and these materials are specified. A metal material having a low melting point to which the additive element is further added. Examples of frequently used materials include Sn / Pb eutectic solder and Sn / Ag / Cu solder, but are not necessarily limited thereto. Examples of the material of the small pad 3 of the semiconductor chip 1 and the large pad 4 of the substrate 2 include a Cu pad and a pad provided with an Au layer on the surface of Ni.

  The underfill 7 is a cured resin filled in the gap between the semiconductor chip and the wiring board. As the resin composition for forming the underfill 7, it is preferable to use a resin composition containing a thermosetting resin as a main component and 0 to 65% by weight of an inorganic filler. Thermosetting resins that are the base material of the underfill 7 include epoxy resins, polyester resins (unsaturated polyesters, combinations of unsaturated polyesters and compounds having active hydrogen groups), acrylate resins ((meth) acryloxypropyl poly). And silicon acrylate such as siloxane, and epoxy acrylate). Moreover, the adhesive agent etc. which harden | cure at normal temperature, such as (alpha) -cyanoacrylate, can also be used as a resin composition for underfills.

The resin composition for forming the underfill 7 has a radical initiation that generates an accelerator for accelerating curing by reacting with the thermosetting resin described above at the time of thermosetting, a radical for curing by heating, and the like. It is preferable to contain one or a combination of two or more curing agents such as an agent, an anionic initiator or a cationic initiator.
In addition, an agent (for example, an organic acid) that imparts a solder oxide film removing action can be added to the resin composition for forming the underfill. In addition, by using a material that expresses a component having a solder oxide film removing action during the resin curing reaction, a stable connection can be obtained particularly when the Cu electrode pad and the bump, which are likely to oxidize, are connected. In the case of the mounting structure of the present invention, there is almost no gap for filling the resin for forming the underfill 7 after the semiconductor chip 1 and the substrate 2 are joined. It is desirable to apply an underfill 7 to the semiconductor chip 1. This enables stable resin sealing.

The lower limit of the inorganic filler content of 0% by weight indicates that the inorganic filler may not be contained in the underfill 7, and the upper limit of the content is 65% by weight. This is because if the amount exceeds this, the increase in the viscosity of the resin does not have to be remarkably increased, and the solder connectivity is deteriorated because the resin component having a solder oxide film removing action is reduced. As the inorganic filler, silica filler and the like can be preferably used, but other inorganic fillers may be used and are not particularly limited.
The solder resist film 6 is formed by using a commercially available solder resist material.

  FIG. 3 is a sectional view showing a state in which bumps are formed on the pads of the semiconductor chip 1. As shown in the figure, the pad diameter is d1, the bump volume is V1, and the bump height is h. At this time, the bump volume V1 can be expressed by Expression (1).

リフロー工程後には、図４（ａ）に示すように、体積Ｖ１のバンプにより、上面径：ｄ１、底面径：ｄ２、高さ：ｈ１で富士山型のはんだフィレットが形成される。このような円錐台の斜面が徐々に緩くなるバンプ形状を実現するためには、バンプ体積Ｖ１が、図４（ｂ）に示す上面径：ｄ１、底面径：ｄ２、高さ：ｈ１で規定される円錐台の体積よりも小さければよい。つまり、式（２）の関係を満たす必要がある。式（２）の右辺は円錐台の体積を示す。

After the reflow process, as shown in FIG. 4 (a), a Mt. Fuji solder fillet is formed with a top surface diameter: d1, a bottom surface diameter: d2, and a height: h1 by bumps of volume V1. In order to realize such a bump shape in which the slope of the truncated cone gradually loosens, the bump volume V1 is defined by the top surface diameter: d1, the bottom surface diameter: d2, and the height: h1 shown in FIG. It is sufficient if it is smaller than the volume of the truncated cone. That is, it is necessary to satisfy the relationship of Expression (2). The right side of equation (2) indicates the volume of the truncated cone.

V1 <(a + b + √ab) × h1 / 3 (2)
In the above formula, a represents the area a = (d2 / 2) ² × π of the large pad on the substrate side, and b represents the area volume b = (d1 / 2) ² × π of the small pad on the semiconductor device side. .
Here, an example of a design value for realizing the mounting structure of the present invention using the above formulas (1) and (2) is shown.

The small pad diameter d1 on the semiconductor device side is 130 μm, the large pad diameter d2 on the substrate side is 180 μm, and the bump volume V1 is considered as the volume when using a solder ball with a diameter D = 100 μm (V1 = 4 / 3π (D / 2 ³ ). First, the bump height h in FIG. 3 formed on the small pad on the semiconductor chip side is h = 62 μm from the equation (1).
Next, h1 in FIG. 4 is considered. Before that, assuming that the height when the bump shape is a truncated cone in the values of D, d1, and d2 is h2, h2 is equal to the equation (2). And the value is h2 = 28 μm. Therefore, in order to realize a truncated conical bump shape whose slope is gradually loosened, the thickness of the solder resist film is 28 μm or more (h1> 28 μm).

  The example of the design values shown above can be summarized as follows. The small pad diameter d1 on the semiconductor device side is 130 μm, the large pad diameter d2 on the substrate side is 180 μm, and bumps are formed using solder balls with a diameter D = 100 μm. If the solder resist film thickness is 30 μm, the bump height h before mounting formed on the semiconductor device is 62 μm, and since the solder resist film thickness is higher than 30 μm, the bump and the large pad on the substrate side can be surely mounted. Since the bump height is 30 μm, which is thicker than the 28 μm bump height when the solder resist film thickness becomes a truncated cone after mounting, the bumps wet and spread on the large pads on the substrate side, so that the Fuji-mountain solder fillet A thin semiconductor that has a very small gap between the semiconductor chip and the substrate, where the solder resist film and the semiconductor chip are almost in contact. You can get a package. That is, according to the present invention, both stable connection and thinning of the semiconductor package can be achieved.

[Production method]
Next, an embodiment of a method for manufacturing a semiconductor device will be described with reference to FIG. First, as shown in FIG. 5A, a semiconductor chip 1 provided with bumps 5 on a small pad 3 and a substrate 2 provided with large pads 4 are prepared. Here, the standard of the bump height in FIG. 5A is preferably equal to or smaller than the diameter of the small pad 3. Resin 7 a for forming an underfill is applied to the mounting area of the semiconductor chip 1 on the substrate 2.
The underfill 7 is formed using a resin having a flux action. This resin is obtained by adding an agent having a flux action to a thermosetting resin, and is a resin composition having a solder oxide film removing action for removing the solder and the oxide film on the solder connection surface. In this embodiment, since the underfill 7 is formed using this active resin composition, oxidation in a heated state at the time of solder connection is prevented by the flux action of itself even without using a flux. In addition, it is possible to remove the oxide film on the solder and the solder connection surface and to perform highly reliable solder connection. Since the agent having the action of removing the solder oxide film in the active resin composition used is bonded to the base resin and becomes chemically stable after curing, the formed underfill has sufficient electrical insulation. Have.
As a method of applying a resin for forming an underfill on the substrate 2, a method of applying a single point to the central portion of the substrate 2 is generally used. However, when the semiconductor chip 1 is large, the mounting position is diagonally located. A method of coating so that “x” is drawn on the surface or a method of coating in several points are preferably applied.

  Next, as shown in FIG. 5B, the semiconductor chip 1 adsorbed by a tool (not shown) is aligned on the substrate 2 and then mounted while applying a predetermined load. Thereafter, the bump is melted by using a reflow furnace heated to a predetermined temperature, and the bump is wet spread on the large pad 4 on the substrate side. Thereafter, the resin is cured in an oven or the like to form the underfill 7, and the manufacturing process of the semiconductor device according to the present invention is completed.

  As another mounting method, when the semiconductor device is mounted on the substrate, the semiconductor chip 1 may be connected by heating with a heater built in the tool, or it is built in a stage (not shown) on which the substrate 2 is placed. The substrate 2 may be heated and connected by a heater. When the bump 5 is melted and bonded to the large pad 4 on the substrate side, it is possible to obtain a stable connection without short-circuiting the bump even if the connection is made while applying a load for the purpose of improving the connectivity.

  The preferred embodiment of the present invention has been described above. However, the present invention is not limited to this example, and appropriate modifications can be made without departing from the scope of the present invention. For example, in the embodiment, the planar shapes of the small pad and the large pad are both assumed to be circular, but one or both may be a polygon such as a square. The present invention can be applied not only to mounting a semiconductor chip on a substrate but also to all cases in which pads are joined using solder. For example, the case of solder connection between semiconductor chips, CSP (chip size package) and a wiring board, or wiring boards is mentioned.

1 is a cross-sectional view illustrating an embodiment of a semiconductor device of the present invention. FIG. 2 is an enlarged view of a solder joint portion in FIG. 1. Sectional drawing which shows the state by which bump was formed in the semiconductor chip. Sectional drawing which shows the junction part after the semiconductor chip which has a bump shown in FIG. 3 was mounted in the board | substrate, and sectional drawing of a truncated cone. Sectional drawing of process order which shows one Embodiment of the manufacturing method of the semiconductor device of this invention. Sectional drawing of the order of the process which shows the manufacturing method of the conventional semiconductor device. Sectional drawing which shows an example of the soldering part of the semiconductor device manufactured by the manufacturing method shown by FIG. Sectional drawing of the wiring board with a solder bump of a prior art.

Explanation of symbols

1 Semiconductor chip 2 Substrate 3 Small pad 4 Large pad 5 Bump 6 Solder resist film 7 Underfill 7a Resin 8 Flux 9 Chip side pad 10 Substrate side pad

Claims (9)

In a semiconductor device in which a first pad formed on a first electronic device and a second pad formed on a second electronic device opposite to the first pad are electrically connected by a solder fillet, 2. The semiconductor device according to claim 2, wherein the second pad is larger than the first pad, and the inclination of the side surface of the solder fillet formed in the shape of a truncated cone or a truncated pyramid is gradually loosened toward the second pad. In a semiconductor device in which a first pad formed on a first electronic device and a second pad formed on a second electronic device opposite to the first pad are electrically connected by a solder fillet, The second pad is larger than the first pad, and the surface of the second electronic device facing the first electronic device is covered with an insulating film surrounding the second pad, and the solder fillet A volume of the semiconductor device is smaller than a volume of a truncated cone or a truncated pyramid defined by thicknesses of the first pad, the second pad, and the insulating coating. The semiconductor device according to claim 1, wherein a gap formed between the first and second electronic devices is filled with a resin surrounding the solder fillet. The semiconductor device according to claim 3, wherein a material having a solder oxide film removing action is added to the resin filled between the first and second electronic devices. The combination of the first electronic device and the second electronic device is a semiconductor chip and a wiring board (including an interposer), a semiconductor chip and a semiconductor chip, a CSP (chip size package) and a wiring board, or a wiring board (interposer). The semiconductor device according to claim 1, wherein the semiconductor device is a wiring board. A first pad formed on the first electronic device and a second pad having a larger area than the first pad formed on the second electronic device are substantially frustum-shaped or frustum-shaped solder. In the method of manufacturing a semiconductor device electrically connected by a fillet, the surface on which the second pad of the second electronic device is formed or the first pad of the first electronic device is A resin application step of applying a resin to the formed surface, and solder terminals formed on the first pads of the first electronic device (including solder bumps and solder balls; the same applies to the following claims) Positioning on the second pad of the second electronic device and mounting the first electronic device on the second electronic device, and the solder end The method of manufacturing a semiconductor device, wherein a is melted; and a soldering step of spreading wetting the second pad. A solder terminal on the first pad formed in the first electronic device is formed on the surface of the second electronic device by being surrounded by an insulating film, and has a second area larger than that of the first pad. In a method of manufacturing a semiconductor device connected to a pad, a solder terminal formed on a first pad of the first electronic device is aligned on the second pad of the second electronic device, and the first A positioning and mounting step of mounting one electronic device on the second electronic device, and a soldering step of melting the solder terminal and spreading it onto the second pad, the height of the solder terminal Is larger than the film thickness of the insulating coating, and the volume of the solder terminal is a truncated cone or a truncated pyramid defined by the distance between the first pad, the second pad, and both pads after completion. volume The method of manufacturing a semiconductor device which can, wherein the small Ri. Prior to the alignment / mounting step, the surface of the second electronic device on which the second pad is formed or the surface of the first electronic device on which the first pad is formed. The method of manufacturing a semiconductor device according to claim 7, wherein a resin application step of applying a resin is performed. 9. The method of manufacturing a semiconductor device according to claim 6, wherein a material having a metal oxide film removing action is added to the resin.

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