JP4626839B2 - Mounting method of semiconductor device - Google Patents

Mounting method of semiconductor device Download PDF

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JP4626839B2
JP4626839B2 JP2001150645A JP2001150645A JP4626839B2 JP 4626839 B2 JP4626839 B2 JP 4626839B2 JP 2001150645 A JP2001150645 A JP 2001150645A JP 2001150645 A JP2001150645 A JP 2001150645A JP 4626839 B2 JP4626839 B2 JP 4626839B2
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semiconductor device
thermosetting resin
resin
mounting
solder
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JP2002343829A (en
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明 大内
芳正 加藤
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置の実装方法に関し、特に、半導体装置と配線基板との間の熱硬化性樹脂におけるボイドの発生を抑制し、高い接続信頼性が得られる半導体層装置の実装方法に関する。
【０００２】
【従来の技術】
従来のはんだバンプを用いたフリップチップ実装方法を図７に示す。図７に示すように、従来は、バンプ２形成後のＬＳＩチップ等の半導体装置１のバンプ先端または配線基板３にフラックス１０を付着させた後、配線基板３に位置合わせして半導体装置１を搭載した後、リフローを行い、その後、フラックス１０を洗浄した後、毛細管現象により半導体装置１と配線基板３のギャップにアンダーフィル樹脂（熱硬化性樹脂６）の充填を行い、最後に熱硬化性樹脂６を硬化させる方法が行われている。
【０００３】
また、はんだを有するフリップチップ実装方法のうち、あらかじめ配線基板３上に封止樹脂６を塗布しておき、半導体装置１をマウント後、加熱することではんだ接続および樹脂硬化を行なう実装方法として、例えば、特開平１１−２３３５５８号公報に開示されている方法がある。この方法による実装プロセスを図８に示す。
【０００４】
まず、半導体装置１を配線基板３上に搭載する前工程として、半導体装置１の端子電極にバンプ２を形成し（ステップ１）、パッド４にはんだ５を形成する（ステップ２）。次に、予め配線基板３の半導体装置１が搭載される部分に、半導体装置１と配線基板３の間を充分に介在させる量の樹脂６を塗布する（ステップ３）。次に、この樹脂６を塗布したパッド４上のはんだ５にバンプ２が位置するように半導体装置１を配線基板３に位置決め搭載する。その後、半導体装置１を吸着したボンディングツ−ル７に備えられたヒ−タ−等の加熱手段により、位置決め搭載した半導体装置１を加熱すると同時に、配線基板３を載せた基板ステ−ジ８に備えられたヒ−タ−等の加熱手段で加熱を行なう（ステップ４）。この加熱工程では、最初、はんだ融点以上の温度に加熱してバンプ２とはんだ５との接合部を金属結合させた後、はんだ融点以下に加熱温度を下げて樹脂６を硬化させて実装が完了する。
【０００５】
他の従来例として、バンプ２がはんだバンプであり、樹脂６に酸化膜除去作用を含んだ樹脂を用いる場合がある。これらの方法により、半導体装置と基板のギャップにアンダーフィル樹脂充填する工程を削除し、生産性を向上させている。
【０００６】
【発明が解決しようとする課題】
図７に示すフラックスを用いてはんだバンプを接続する従来のフリップチップ実装方法では、以下の問題点がある。
【０００７】
まず、第１の問題点は、ＬＳＩの高密度化による狭ピッチ化が進むにつれ、バンプ２が微細化し、半導体装置１と配線基板３間の隙間が狭くなる傾向があり、フラックス洗浄が益々困難な状況となってきている。フラックス残渣が引き起こす問題点としては、活性剤がＬＳＩ等の電子部品に残留し、この残留した活性剤が吸湿すると、そのイオン成分が電気的絶縁性を低下させ、マイグレーション等により製造された電子部品の信頼性を低下させるといった問題を引き起こす。また、アンダーフィル充填をも阻害することとなり、樹脂封止層にボイドが発生するなど実装信頼性を低下させるという問題がある。
【０００８】
第２の問題点は、フラックス洗浄工程やアンダ−フィル充填工程などのプロセスを必要とする為、フラックス洗浄に必要な設備を必要としたり、アンダ−フィル充填に時間がかかる等、生産コストが高くなることである。
【０００９】
このような問題に関して、図８に示すようなあらかじめ配線基板３上に熱硬化性樹脂６を塗布しておき、半導体装置１を搭載後、熱硬化性樹脂６を硬化させる一括プロセスが提案されている。しかしながら、この方法では、半導体装置１を熱硬化性樹脂６が塗布された配線基板３上に搭載する際に、半導体装置１側の突起電極間凹部の外気が抜けきれずに残ったり、樹脂６を外側に強制的に押し出すこととなるため、バンプ２や配線基板３の凹凸があると樹脂６が乱流になって外気を巻き込む等の影響でボイドが発生しやすい。
【００１０】
この現象は、半導体装置１と配線基板３を接続する電極が半導体装置１表面全体に配置しているエリア配置の場合に特に顕著に発生する。電極間にボイドがある状態では、ボイド部のバンプ２に応力が集中して接続破壊を起こすことがあるだけでなく、装置動作時に発生する熱応力で電極金属を塑性変形させ、場合によってはボイドを介して隣り合った電極が連結してしまうショ−トを引き起こす等、接続信頼性に対して重大な問題となる。
【００１１】
また、はんだ酸化膜除去作用を含む樹脂を使用し、はんだ接続を行なう場合、ボイドがあると酸化膜除去作用が弱くなり、はんだ表面の酸化膜を除去しにくくなる為、ボイド部分のバンプは接続不良を起こしやすくなる。
【００１２】
前記のようなボイドが引き起こす問題は、接続信頼性を向上させるために熱硬化性樹脂の熱膨張係数を調整する手段として樹脂中にシリカ等のフィラ−を添加すると、樹脂粘度が相対的に上昇する為、樹脂がなめらかに流れず半導体装置や配線基板に濡れにくくなるためさらに顕著になることから、信頼性の高い実装品を得ることは困難である。
【００１３】
本発明の目的は、はんだバンプが形成されたベアチップまたはチップサイズパッケージ等の半導体装置において、接続信頼性を確保するとともに生産性に優れた実装方法を提供することにある。
【００１４】
【課題を解決するための手段】
本発明の半導体装置の実装方法は、半導体装置の電極と配線基板の電極とがバンプを介して電気的に接続され、前記半導体装置と前記配線基板との間を熱硬化性樹脂により封止してなる半導体装置の実装方法において、前記配線基板上に熱硬化性樹脂を塗布する工程と、前記半導体装置を前記配線基板上に搭載するに際し、前記半導体装置と前記熱硬化性樹脂とが接触する直前に、前記半導体装置を載置するツールの移動速度を減速又は一旦停止させる工程と、前記半導体装置の電極と前記配線基板の電極とが前記バンプを介して接触した状態で、前記半導体装置を加熱して前記半導体装置の電極と前記配線基板間の電極とを電気的に接続するバンプ接続工程と、前記半導体装置の搭載が完了した前記配線基板を、前記バンプ接続工程以下の温度雰囲気中に保持し、前記熱硬化性樹脂を硬化させる樹脂硬化工程と、を含むものである。
【００１５】
本発明においては、前記半導体装置と前記熱硬化性樹脂とが接触する前における前記ツールの移動速度が、略１０ｍｍ／ｓ以下に設定される構成とすることができる。
【００１７】
また、本発明の半導体装置の実装方法は、半導体装置の電極と配線基板の電極とがバンプを介して電気的に接続され、前記半導体装置と前記配線基板との間を熱硬化性樹脂により封止してなる半導体装置の実装方法において、前記配線基板上に熱硬化性樹脂を塗布する工程と、前記半導体装置を前記配線基板上に搭載するに際し、前記半導体装置と前記熱硬化性樹脂とが接触する前に、前記半導体装置を少なくとも前記配線基板より高い温度で加熱する予備加熱工程と、前記半導体装置と前記熱硬化性樹脂とが接触する直前に、前記半導体装置を載置するツールの移動速度を減速又は一旦停止させる工程と、前記半導体装置の電極と前記配線基板の電極とが前記バンプを介して接触した状態で、前記半導体装置を前記予備加熱工程以上の温度に加熱して前記半導体装置の電極と前記配線基板間の電極とを電気的に接続するバンプ接続工程と、前記半導体装置の搭載が完了した前記配線基板を、前記バンプ接続工程以下の温度雰囲気中に保持し、前記熱硬化性樹脂を硬化させる樹脂硬化工程と、を含むものである。
【００２２】
本発明の実装方法の場合、半導体装置の搭載に際し、半導体装置と熱硬化性樹脂とが接触する前に半導体装置を少なくとも前記配線基板より高い温度で加熱することで、配線基板側に塗布した熱硬化性樹脂が半導体装置と接触すると、瞬時に樹脂粘度が低下して半導体装置側に濡れやすくなる。このため、半導体装置側の突起電極間の凹部にも樹脂が入り込みやすくなる。また、中央部の樹脂が押し出されることにより、樹脂充填される半導体装置外周については樹脂が濡れやすくなることで押し出される樹脂速度に対して樹脂の濡れが追従可能となる。このため、搭載時に発生するボイドを防止することが可能となる。
【００２３】
また、フィラ−添加した時など粘度が高い樹脂の場合、樹脂の濡れ性や流動性が不足するが、加熱に加えて半導体装置と熱硬化性樹脂が接触する直前に半導体装置の搭載速度を減速させることにより、突起電極間の凹部へ樹脂が入り込みやすくなり、樹脂の濡れが樹脂押し出し速度に追従可能となるため、搭載時に発生するボイドを防止することが可能となる。
【００２４】
また、使用する樹脂によっては、高温で長時間加熱すると樹脂自体からボイドが発生するものがあるが、短時間の高温加熱で接続を行い、低い温度で樹脂硬化させる方法にすれば、ボイドを防止できる。
【００２５】
従って、本実装方法を行なえば、熱硬化性樹脂の熱膨張係数を調整する為にシリカ等のフィラ−を添加した場合であっても、搭載時のボイドや接続不良を生じることがない為、信頼性の高い実装品を得ることが出来る。
【００２６】
【発明の実施の形態】
次に、本発明の一実施の形態について図面を参照して詳細に説明する。図２を参照して、エリアに配列されたＣｕパッド９上に高融点バンプ２が形成されたＬＳＩを、同一配列位置にＣｕパッド４を形成し、且つパッド４上に共晶はんだ５が予備はんだとして形成されたプリント配線基板３上に実装する時の一例について説明する。
【００２７】
まず、図２（ａ）に示すように、予備はんだ５が形成されたプリント配線基板３を加熱されたステ−ジ８上に置き、昇温する。昇温の目的は、熱硬化性樹脂６を塗布する際にプリント配線基板３表面の樹脂の濡れ性を向上させ、樹脂塗布時に配線基板３表面の凹凸の影響で空気を巻き込みにくくする為である。この時の温度は熱硬化性樹脂６の硬化反応があまり進まないことが望ましく、６０℃〜１００℃程度が良い。プリント配線基板３は、濡れ性改善のためにステ−ジ８に置く前にプラズマ等の表面処理により、表面改質することも有効である。
【００２８】
次に、図２（ｂ）に示すように、プリント配線基板３上の半導体装置１搭載位置に熱硬化性樹脂６をディスペンサ−等により塗布する。塗布形状は、中央部分に１点塗布する方法が一般的であるが、半導体装置１搭載位置の対角線上に「×」を描くように塗布する方法、数点に分けて塗布する方法等がある。
【００２９】
次に、図２（ｃ）に示すように、ツ−ル７に吸着された半導体装置１をプリント配線基板３上に位置合わせした後、ツ−ル７に内蔵された加熱ヒ−タにより、半導体装置１を加熱する。加熱の目的は、半導体装置１のバンプ２と熱硬化性樹脂６とが接触した際に、接触した熱硬化性樹脂６の粘度を瞬時に低下させ、バンプ２へ濡れやすくさせる為であり、この作用により半導体装置１搭載時にバンプ２間の凹部の空気が取り残されてボイドになることを未然に防いでいる。この時のツ−ル７の加熱温度は１５０℃以上であることが望ましい。また半導体装置１は、ツ−ル７に吸着する前にプラズマ等の表面処理により、表面改質することも有効である。
【００３０】
また、使用する熱硬化性樹脂６にフィラ−を添加する場合、その添加量が５０％以上になると加熱時の樹脂粘度が低下しにくくなり、半導体装置１の加熱によるボイド防止効果が薄れる為、半導体装置１の加熱と同時に半導体装置１と熱硬化性樹脂６とが接触する直前に、半導体装置１の搭載速度を減速させると効果がある。この場合の搭載速度は１０ｍｍ／ｓ以下が効果的である。ツ−ル７の搭載速度を制御する方法として、半導体装置１と熱硬化性樹脂６とが接触する直前に一度停止させてもよい。
【００３１】
次に、図２（ｄ）に示すように、半導体装置１に対して所定の荷重をかけ、はんだ融点以上に昇温する事で電極部のはんだ接続を行なう。この際、熱硬化性樹脂６に付与されているはんだ酸化膜除去作用も加わり、短時間で確実なはんだ結合が行なわれる。このとき、熱硬化性樹脂６は硬化反応がほとんど進んでいない状態であるため、樹脂粘度は十分に低くはんだ接続を阻害することはない。なお、半導体装置１に加える荷重は半導体装置１のサイズやバンプ２のピッチ、サイズ、数などにより異なるが、目安として１バンプあたり０．１〜５ｇ程度が望ましく、加熱温度ははんだ融点温度より２０〜５０℃高いことが望ましく、この条件にてはんだ接続を行なう時間は、３〜１０秒程度が望ましい。
【００３２】
また、半導体装置１をプリント配線基板３に搭載する際に、振動を加えながら加熱して搭載し、電気的接続を行う方法を用いれば、熱硬化性樹脂６にはんだ酸化膜除去作用を添加する必要が無くなる。
【００３３】
次に、はんだ接続が完了した上記実装品の熱硬化性樹脂６を硬化させるが、樹脂を完全に硬化させる手段としては、はんだ接続を行った後の実装品を複数個まとめて樹脂硬化可能な温度雰囲気に保たれた恒温槽等に移して行なうと良い。これにより、個々の搭載サイクルタイムははんだ接続に必要な時間のみで良いため、時間の短縮が可能となり、かつ一定の樹脂硬化時間で複数個の半導体装置１の樹脂硬化が可能となるため、生産性が向上する。
【００３４】
図１に、実装が完了した本実施の形態の一例として、バンプ２にはんだバンプを用いて製作した場合のフリップチップ実装構造体の断面図を示す。図１において、配線基板３のパッド４上にプリコ−トされたはんだ５と半導体装置１の突起電極であるバンプ２とがそれぞれ対応する位置にて金属接合されることで、半導体装置１と配線基板３の電気的接続が行われている。半導体装置１と配線基板３の間の封止樹脂は、熱硬化性樹脂６で構成されている。
【００３５】
はんだ５の材質の例としてはＳｎ／Ｐｂ共晶はんだがあるが、Ｓｎ／Ｐｂ共晶はんだに限定されず、たとえばＳｎ／Ｐｂ（共晶を除く）、Ｓｎ／Ａｇ、Ｓｎ／Ｃｕ、Ｓｎ／Ｓｂ、Ｓｎ／Ｚｎ、Ｓｎ／Ｂｉおよびこれら前記した材料に特定の添加元素をさらに加えた材料を挙げることができ、これらが適宜用いられる。また、バンプ２ははんだ５と同じでも異なる材質であってもよく、融点の異なるはんだであっても良い。よく用いられる材料はＰｂリッチなＳｎ／Ｐｂがあげられる。異なる材質の一例としてはＡｕバンプがあげられる。
【００３６】
また、電気的接続部を除く半導体装置１と配線基板３の間は、電気的接続部を保護すると共に、半導体装置１と配線基板３の熱膨張係数の違いにより生じる熱応力が電気的接続部に集中することを緩和し、接続信頼性を向上させる目的で熱硬化性樹脂６により樹脂封止されている。
【００３７】
熱硬化性樹脂６は、はんだ接続を行なう場合、活性樹脂（はんだ酸化膜を除去する効果がある熱硬化性樹脂）を用いることが望ましい。例えば、基材となる熱硬化性樹脂６にフラックス効果を有する剤を添加した構成であり、はんだおよび被はんだ接続面の酸化膜を除去する作用を持つ。すなわち、はんだ接続での硬化前の加熱状態において、フラックス作用を有する剤が作用し、はんだおよび被はんだ接続面の酸化膜が除去される。活性樹脂は、硬化後は基材樹脂と結合することにより化学的に安定となり、十分な電気的絶縁性を有する。
【００３８】
また、熱硬化性樹脂６にフラックス作用を与えるには、（メタ）アクリル酸、マレイン酸などの不飽和酸、蓚酸、マロン酸などの有機二酸、クエン酸などの有機酸をはじめ、炭化水素の側鎖に、ハロゲン基、水酸基、ニトリル基、ベンジル基、カルボキシル基等を少なくとも１つ以上を添加することにより可能である。また、(メタ)アクリルアルコールなどの不飽和アルコール、トリメリット酸、テトラメリット酸および一般的に知られているキレート剤を用いることもできる。このような前記フラックス作用を有する剤は、二種以上組合せて用いることができる。なお、フラックスには、公知のゲル化剤を含むこともできる。
【００３９】
また、半導体装置実装工程においては、熱硬化性樹脂６に活性樹脂を使用することで、フラックスを使用する必要が無くなるため、フラックス洗浄工程を省略でき、また、洗浄不良によって生じるフラックス残渣に起因する信頼性への悪影響を防止することができる。
【００４０】
熱硬化性樹脂の基材としては、エポキシ、ポリエステル（不飽和ポリエステル、不飽和ポリエステルと活性水素基を有する化合物の組合せなど）、アクリレート（（メタ）アクリロキシプロピルポリシロキサンなどのシリコンアクリレート、エポキシアクリレートを含む）などである。熱硬化時に前記した熱硬化性樹脂と反応して硬化を促進する促進剤、および／または硬化剤（加熱によって硬化するためのラジカル等が発生するラジカル開始剤、アニオン開始剤またはカチオン開始剤）等を有している。なお、αーシアノアクリレートなどの常温で硬化する接着剤等を用いることもできる。前記熱硬化性樹脂、促進剤、硬化剤および開始剤等は、２種以上、組合せて用いることができる。さらに、熱硬化性樹脂には、熱膨張係数等を調整し接続信頼性を向上させる目的でシリカ等のフィラ−を添加しても良い。
【００４１】
なお、バンプ形成された半導体装置１を短時間で確実にはんだ接続させる為に、搭載時に加熱とともに加圧を行なったり、振動によりはんだ接続させることもできる。
【００４２】
図３は、プリント配線基板３上に予備はんだが形成されていない場合のはんだバンプを用いた本発明の実施の形態を示す図である。実装方法に関しては図２で示した例と同様であるが、この場合、加熱加圧時にバンプ２を潰してしまわないように、半導体装置１と配線基板３との隙間を一定に保つような位置制御を行なう必要がある。
【００４３】
【実施例】
上記した本発明の実施の形他についてさらに詳細に説明すべく、本発明の実施例について図面を参照して説明する。本実施例では、上記実装方法により、半導体装置を熱硬化性樹脂が塗布された配線基板上に搭載する際に、半導体装置側の突起電極間凹部の外気が抜けきれずに残り、ボイドとなる不具合が発生しないことを確認するとともに、その際の接続信頼性を確認するため以下の実験を行なった。まず、使用機材について説明する。
【００４４】
半導体装置１は、サイズ１０ｍｍ□であり、はんだバンプが０．２４ｍｍピッチで半導体装置１表面全面に配置されているフルグリッドエリア配置である。はんだバンプ材質はＰｂ９５％、Ｓｎ５％である。配線基板３は、半導体装置１に対応した電極が配置されており、パッド４上には予備はんだが約２０μｍの高さで形成されている。予備はんだ材質は共晶はんだである。なお、実装後の半導体装置１と配線基板３は電気的接続の確認が行なえる構造となっている。
【００４５】
熱硬化性樹脂６はエポキシであり、フェノ−ル系硬化剤を使用した樹脂Ａと酸無水物系硬化剤を使用した樹脂Ｂを用い、共にはんだ酸化膜除去作用を有する樹脂である。さらにこれらの樹脂にシリカフィラ−を添加したものについても評価を行なった。ここで、熱硬化性樹脂６は、エポキシに限られるものではなく、上述したように、ポリエステルやアクリレートなどでも良い。
【００４６】
次に、実装方法について説明する。
【００４７】
まず、半導体装置１にＡｒプラズマ処理を行い、プラズマの表面改質効果による半導体装置１と樹脂６の濡れ性向上及びはんだバンプ２の接続性向上を図った。続いて、配線基板３をステ−ジ８上に置き、ディスペンサ−により熱硬化性樹脂６を配線基板３上の半導体装置１が搭載される中央部に約２０ｍｇ塗布した。続いて、半導体装置１をツ−ル７に吸着し、配線基板３との位置合わせを行ない、半導体装置１を配線基板３上に搭載し、半導体装置１のはんだバンプ２と配線基板３の予備はんだ５が接触後、半導体装置１を２３０℃に加熱しながら３ｇ／バンプの加圧を５秒間行ない、電極間のはんだ接続をした。なお、接続の際、加圧を行なわない方法も試みたが、この場合、フィラー添加量４０％以上の樹脂は、ほとんどの接続部ではんだ濡れ不良が発生し、未接続となった。
【００４８】
続いて、はんだ接続の完了した実装品を１５０℃大気雰囲気中の恒温槽に９０分間入れて、熱硬化性樹脂６の硬化を行ない実装を完了した。
【００４９】
半導体装置搭載時のボイド評価として、半導体装置１の搭載速度とステ−ジ８及びツ−ル７の温度条件を変えて比較評価を行なった。本実施例で使用した樹脂における温度と樹脂粘度の関係を、表１に示す。２５℃に比べ５０℃ではかなり樹脂粘度が低下しており、７０℃近傍から昇温に連れて急に樹脂粘度が低下している事がわかる。
【００５０】
評価条件詳細および結果として、表２は常温で搭載速度が速い従来条件に対して搭載速度を遅くし、ツ−ル温度及びステ−ジ温度を変化させたときのボイド観察結果、表３は表２の条件でボイドが発生しなかった温度条件に関して、樹脂にフィラ−添加し、搭載速度を速くしたときのボイド観察結果を示す。ボイドの観察方法としては、実装が完了したサンプルについて、樹脂層部分の断面を顕微鏡で観察した。
【００５１】
また、それぞれの搭載時の加熱及びツ−ル変位を示すプロファイル図を図４乃至図６に示す。なお、表２又は表３の搭載プロファイル欄の番号と図４乃至図６の番号とが対応している。図４乃至図６に示す▲１▼は、はんだバンプと熱硬化性樹脂とが接触した時点であり、▲２▼ははんだバンプと基板（基板上のパッド）とが接触した時点である。また、ツール温度は、▲２▼以降はんだバンプの融点以上の温度に上昇されている。表２および表３において、ツール温度は、はんだバンプと熱硬化性樹脂が接触した時点での温度である。
【００５２】
【表１】

Figure 0004626839
【００５３】
【表２】
Figure 0004626839
【００５４】
【表３】
Figure 0004626839
【００５５】
表２に関して、ツール及びステージを常温にて４０ｍｍ／ｓで搭載した従来条件の場合は、封止樹脂全面に多数発生した。これに対し、半導体装置と樹脂が接触する直前に搭載速度を０．１ｍｍ／ｓと遅くした場合、ボイドが減っていることは確認できたが、主に樹脂塗布した中央部分にはボイドが残っており、完全にボイドを無くすまでには至らなかった。さらにツール及びステージ温度を変化させていくと、ツール温度１５０℃、ステージ温度６０℃以下のときボイドが発生しなかった。
【００５６】
次に、表３に示すように、ボイドが発生しなかったツール温度１５０℃、ステージ温度６０℃の温度条件において、再び搭載速度を４０ｍｍ／ｓとし、樹脂にシリカフィラーを添加したものを含め、ボイド観察を行なった。結果はフィラー添加量４０％まではボイドが発生しなかったが、フィラー添加量６０％の場合、ボイドが発生した。そこでフィラー添加量６０％については、この温度条件のまま搭載速度を１０ｍｍ／ｓとするとボイドが発生しなかった。
【００５７】
この結果から、フィラ−添加量が４０％以下の樹脂に関しては、半導体装置１側を配線基板３側より高い温度で加熱しておき、半導体装置１に熱硬化性樹脂６が接触した際、半導体装置１側に熱硬化性樹脂６が濡れやすくなる状況を作り出す本実装方法を行なうことで、半導体装置１搭載時のボイドを未然に防げることを確認した。ここで、ツール温度は、１５０℃としたが、ツール温度は、基板３よりも高い温度であれば、半導体装置１の搭載速度と使用する熱硬化性樹脂６の温度による樹脂粘度の変化によって変える事が可能である事はもちろんである。
【００５８】
また、フィラ−添加量の割合が多く樹脂粘度が４０Ｐａ・s（２５℃の時）以上の樹脂は半導体装置側の加熱と共に搭載速度を減速させることで、半導体装置搭載時のボイドを未然に防げることを確認した。また、これらのサンプルのうち、フィラー添加量４０％以上のものについて−４０℃〜１２５℃の温度サイクル試験を行い接続信頼性を評価した結果、樹脂Ａ，Ｂ共に１０００サイクル以上接続信頼性が確保できていることを確認した。この結果から、本発明の実装方法により、樹脂層にボイドが無く接続信頼性が高い実装品が得られることを確認した。
【００５９】
【発明の効果】
以上説明したように、本発明の半導体装置の実装方法によれば、配線基板上に熱硬化性樹脂を塗布後、半導体装置を配線基板上に搭載するに際し、半導体装置と熱硬化性樹脂とが接触する前に、半導体装置を少なくとも配線基板より高い温度で加熱、又は、半導体装置の搭載速度を減速又は一旦停止、又はこれらを組み合わせて、半導体装置側に熱硬化性樹脂を濡れやすくすることにより、樹脂層に発生しやすいボイドを未然に防ぐとともに、シリカフィラ−を添加し、熱膨張係数を調整した熱硬化性樹脂を用いてもはんだ接続を行うことができ、接続信頼性の高い実装品を得る事ができる。
【図面の簡単な説明】
【図１】本発明の実装方法により実装したフリップチップ実装構造体を示す断面図である。
【図２】配線基板に予備はんだが形成された場合における本発明の実装方法を示す工程断面図である。
【図３】配線基板に予備はんだが形成されていない場合における本発明の実装方法を示す工程断面図である。
【図４】半導体装置搭載時の加熱及びツ−ル変位を示すプロファイル図である。
【図５】半導体装置搭載時の加熱及びツ−ル変位を示すプロファイル図である。
【図６】半導体装置搭載時の加熱及びツ−ル変位を示すプロファイル図である。
【図７】従来のフラックスによるはんだ接合を行なった場合の実装方法を示す工程断面図である。
【図８】従来の配線基板に樹脂塗布して半導体装置を搭載する実装方法を示す工程断面図である。
【符号の説明】
１ 半導体装置
２ バンプ
３ 配線基板
４ パッド(配線基板)
５ はんだ
６ 熱硬化性樹脂
７ ツ−ル
８ ステ−ジ
９ パッド（半導体装置）
１０ フラックス[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for mounting a semiconductor device, and more particularly, to a method for mounting a semiconductor layer device that suppresses the generation of voids in a thermosetting resin between a semiconductor device and a wiring board and provides high connection reliability.
[0002]
[Prior art]
A conventional flip chip mounting method using solder bumps is shown in FIG. As shown in FIG. 7, conventionally, after flux 10 is attached to the bump tip of the semiconductor device 1 such as an LSI chip after the bump 2 is formed or to the wiring substrate 3, the semiconductor device 1 is aligned with the wiring substrate 3. After mounting, reflow is performed, then the flux 10 is washed, and the gap between the semiconductor device 1 and the wiring board 3 is filled with an underfill resin (thermosetting resin 6) by capillary action, and finally thermosetting is performed. A method of curing the resin 6 is performed.
[0003]
Among the flip chip mounting methods having solder, as a mounting method in which the sealing resin 6 is applied on the wiring substrate 3 in advance, and the semiconductor device 1 is mounted and then heated to perform solder connection and resin curing. For example, there is a method disclosed in Japanese Patent Laid-Open No. 11-233558. A mounting process according to this method is shown in FIG.
[0004]
First, as a pre-process for mounting the semiconductor device 1 on the wiring substrate 3, bumps 2 are formed on the terminal electrodes of the semiconductor device 1 (step 1), and solder 5 is formed on the pads 4 (step 2). Next, an amount of resin 6 that sufficiently interposes between the semiconductor device 1 and the wiring substrate 3 is applied to the portion of the wiring substrate 3 where the semiconductor device 1 is mounted (step 3). Next, the semiconductor device 1 is positioned and mounted on the wiring board 3 so that the bumps 2 are positioned on the solder 5 on the pads 4 coated with the resin 6. Thereafter, the positioning and mounting of the semiconductor device 1 is heated by a heating means such as a heater provided in the bonding tool 7 that has adsorbed the semiconductor device 1, and at the same time, the substrate stage 8 on which the wiring board 3 is placed is mounted. Heating is performed by a heating means such as a heater (step 4). In this heating process, first, after heating to a temperature equal to or higher than the melting point of the solder to bond the joint between the bump 2 and the solder 5, the mounting is completed by lowering the heating temperature below the melting point of the solder and curing the resin 6 To do.
[0005]
As another conventional example, the bump 2 is a solder bump, and a resin including an oxide film removing function may be used as the resin 6. By these methods, the process of filling the gap between the semiconductor device and the substrate with an underfill resin is eliminated, and productivity is improved.
[0006]
[Problems to be solved by the invention]
The conventional flip chip mounting method for connecting solder bumps using the flux shown in FIG. 7 has the following problems.
[0007]
First, the first problem is that as the pitch becomes narrower due to the higher density of LSI, the bumps 2 become finer and the gap between the semiconductor device 1 and the wiring board 3 tends to become narrower, and flux cleaning becomes more difficult. It has become a situation. The problem caused by the flux residue is that the activator remains in the electronic parts such as LSI, and when the remaining activator absorbs moisture, the ionic component lowers the electrical insulation, and the electronic parts manufactured by migration etc. This causes problems such as lowering the reliability. Further, underfill filling is also hindered, and there is a problem that the mounting reliability is lowered, for example, voids are generated in the resin sealing layer.
[0008]
The second problem is that a process such as a flux cleaning process and an underfill filling process is required, so that the equipment required for flux cleaning is required, and it takes time to fill the underfill, resulting in high production costs. It is to become.
[0009]
Regarding such a problem, a batch process is proposed in which a thermosetting resin 6 is applied on the wiring board 3 in advance as shown in FIG. 8 and the thermosetting resin 6 is cured after the semiconductor device 1 is mounted. Yes. However, in this method, when the semiconductor device 1 is mounted on the wiring substrate 3 to which the thermosetting resin 6 is applied, the outside air in the recesses between the protruding electrodes on the semiconductor device 1 side remains without being removed, or the resin 6 Therefore, if the bumps 2 and the wiring substrate 3 are uneven, the resin 6 becomes turbulent and voids are easily generated due to the influence of outside air.
[0010]
This phenomenon occurs particularly conspicuously in the case of an area arrangement in which the electrodes connecting the semiconductor device 1 and the wiring board 3 are arranged on the entire surface of the semiconductor device 1. In the state where there is a void between the electrodes, stress concentrates on the bump 2 in the void portion, and connection breakage may occur, or the electrode metal is plastically deformed by the thermal stress generated during the operation of the device, and in some cases the void This causes a serious problem in connection reliability, such as causing a short circuit in which adjacent electrodes are connected via each other.
[0011]
Also, when using a resin that has a solder oxide film removal action and soldering, if there is a void, the oxide film removal action will be weak and it will be difficult to remove the oxide film on the solder surface. It tends to cause defects.
[0012]
The problem caused by voids as described above is that when a filler such as silica is added to the resin as a means for adjusting the thermal expansion coefficient of the thermosetting resin in order to improve the connection reliability, the resin viscosity is relatively increased. Therefore, since the resin does not flow smoothly and becomes difficult to get wet with the semiconductor device or the wiring board, it becomes more prominent, and it is difficult to obtain a highly reliable mounted product.
[0013]
An object of the present invention is to provide a mounting method that secures connection reliability and is excellent in productivity in a semiconductor device such as a bare chip or a chip size package on which solder bumps are formed.
[0014]
[Means for Solving the Problems]
In the semiconductor device mounting method of the present invention, the electrode of the semiconductor device and the electrode of the wiring board are electrically connected via bumps, and the semiconductor device and the wiring board are sealed with a thermosetting resin. In the method for mounting a semiconductor device, the step of applying a thermosetting resin on the wiring substrate and the semiconductor device and the thermosetting resin come into contact with each other when the semiconductor device is mounted on the wiring substrate. Immediately before , the step of decelerating or temporarily stopping the moving speed of the tool for mounting the semiconductor device, and the semiconductor device in a state where the electrode of the semiconductor device and the electrode of the wiring board are in contact via the bumps A bump connection step for electrically connecting the electrode of the semiconductor device and the electrode between the wiring substrates by heating, and the wiring substrate on which the mounting of the semiconductor device has been completed. Kept in degrees atmosphere, a resin curing step of curing the thermosetting resin, it is intended to include.
[0015]
In this invention, it can be set as the structure by which the moving speed of the said tool before the said semiconductor device and the said thermosetting resin contact is set to about 10 mm / s or less .
[0017]
In the semiconductor device mounting method of the present invention, the electrode of the semiconductor device and the electrode of the wiring board are electrically connected via bumps, and the semiconductor device and the wiring board are sealed with a thermosetting resin. In the mounting method of the semiconductor device, the step of applying a thermosetting resin on the wiring substrate, and the mounting of the semiconductor device on the wiring substrate, the semiconductor device and the thermosetting resin Before the contact, a preheating step of heating the semiconductor device at a temperature higher than at least the wiring substrate, and a movement of a tool for mounting the semiconductor device immediately before the semiconductor device and the thermosetting resin contact each other a step of stopping the speed reduction or once, the state where the electrode of the semiconductor device and the electrode of the wiring board are in contact via the bumps, the semiconductor device above the preheating step temperature A bump connecting step of electrically connecting the electrodes between the wiring substrate and electrodes of the semiconductor device heated to, the wiring board mounting of the semiconductor device is completed, in a temperature atmosphere below the bump connection step Holding and curing the thermosetting resin.
[0022]
In the case of the mounting method of the present invention, when the semiconductor device is mounted, the heat applied to the wiring board side by heating the semiconductor device at a temperature higher than at least the wiring board before the semiconductor device and the thermosetting resin come into contact with each other. When the curable resin comes into contact with the semiconductor device, the resin viscosity is instantaneously reduced and the semiconductor device is easily wetted. For this reason, the resin easily enters the recesses between the protruding electrodes on the semiconductor device side. In addition, by extruding the resin at the center, the outer periphery of the semiconductor device filled with the resin can easily wet the resin, so that the resin can follow the speed of the extruded resin. For this reason, it becomes possible to prevent the void which generate | occur | produces at the time of mounting.
[0023]
Also, in the case of a resin with high viscosity, such as when a filler is added, the wettability and fluidity of the resin are insufficient. However, in addition to heating, the mounting speed of the semiconductor device is reduced immediately before the semiconductor device contacts the thermosetting resin. By doing so, it becomes easier for the resin to enter the recesses between the projecting electrodes, and the wetting of the resin can follow the resin extrusion speed, so that it is possible to prevent voids generated during mounting.
[0024]
Depending on the resin used, there may be voids generated from the resin itself when heated at a high temperature for a long time. However, if a method is used in which the resin is cured at a low temperature for a short time, the void can be prevented. it can.
[0025]
Therefore, if this mounting method is performed, even when a filler such as silica is added to adjust the thermal expansion coefficient of the thermosetting resin, voids and poor connection during mounting will not occur. A highly reliable mounted product can be obtained.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIG. 2, an LSI in which high melting point bumps 2 are formed on Cu pads 9 arranged in an area, Cu pad 4 is formed at the same arrangement position, and eutectic solder 5 is preliminarily placed on pad 4. An example of mounting on the printed wiring board 3 formed as solder will be described.
[0027]
First, as shown in FIG. 2A, the printed wiring board 3 on which the preliminary solder 5 is formed is placed on the heated stage 8, and the temperature is raised. The purpose of raising the temperature is to improve the wettability of the resin on the surface of the printed wiring board 3 when the thermosetting resin 6 is applied, and to make it difficult to entrain air due to the unevenness of the surface of the wiring board 3 when applying the resin. . The temperature at this time is preferably such that the curing reaction of the thermosetting resin 6 does not proceed so much, and is preferably about 60 ° C. to 100 ° C. It is also effective to modify the surface of the printed wiring board 3 by surface treatment such as plasma before placing it on the stage 8 in order to improve wettability.
[0028]
Next, as shown in FIG. 2B, a thermosetting resin 6 is applied to the mounting position of the semiconductor device 1 on the printed wiring board 3 by a dispenser or the like. As for the application shape, a method of applying one point to the central portion is generally used, but there are a method of applying so as to draw “x” on the diagonal line of the mounting position of the semiconductor device 1, a method of applying in several points, and the like. .
[0029]
Next, as shown in FIG. 2C, the semiconductor device 1 adsorbed by the tool 7 is aligned on the printed wiring board 3, and then heated by a heater built in the tool 7. The semiconductor device 1 is heated. The purpose of heating is to instantaneously lower the viscosity of the thermosetting resin 6 in contact with the bump 2 of the semiconductor device 1 and the thermosetting resin 6 so that the bump 2 is easily wetted. This prevents the air in the recesses between the bumps 2 from being left behind when the semiconductor device 1 is mounted, thereby preventing voids. The heating temperature of the tool 7 at this time is desirably 150 ° C. or higher. It is also effective to modify the surface of the semiconductor device 1 by surface treatment such as plasma before adsorbing to the tool 7.
[0030]
In addition, when a filler is added to the thermosetting resin 6 to be used, if the addition amount is 50% or more, the resin viscosity at the time of heating is difficult to decrease, and the void prevention effect due to heating of the semiconductor device 1 is reduced. It is effective to reduce the mounting speed of the semiconductor device 1 immediately before the semiconductor device 1 and the thermosetting resin 6 come into contact with the heating of the semiconductor device 1. In this case, the mounting speed is effectively 10 mm / s or less. As a method for controlling the mounting speed of the tool 7, it may be stopped once immediately before the semiconductor device 1 and the thermosetting resin 6 come into contact with each other.
[0031]
Next, as shown in FIG. 2D, a predetermined load is applied to the semiconductor device 1 and the temperature is raised to the melting point of the solder or higher so that the electrodes are soldered. At this time, a solder oxide film removing action applied to the thermosetting resin 6 is also added, so that reliable solder bonding is performed in a short time. At this time, since the thermosetting resin 6 is in a state in which the curing reaction hardly proceeds, the resin viscosity is sufficiently low and does not hinder the solder connection. The load applied to the semiconductor device 1 varies depending on the size of the semiconductor device 1 and the pitch, size, number, and the like of the bumps 2, but as a guideline, it is preferably about 0.1 to 5 g per bump, and the heating temperature is 20 times higher than the solder melting point temperature. It is desirable that the temperature is higher by about 50 ° C., and the time for performing solder connection under this condition is preferably about 3 to 10 seconds.
[0032]
Further, when the semiconductor device 1 is mounted on the printed wiring board 3, the solder oxide film removing action is added to the thermosetting resin 6 by using a method in which the semiconductor device 1 is heated and mounted while applying vibration and is electrically connected. There is no need.
[0033]
Next, the thermosetting resin 6 of the above-mentioned mounted product after the solder connection is completed is cured. As a means for completely curing the resin, a plurality of mounted products after the solder connection can be collectively cured. It may be carried out by moving to a thermostatic chamber or the like maintained in a temperature atmosphere. As a result, since the individual mounting cycle time is only required for solder connection, the time can be shortened, and a plurality of semiconductor devices 1 can be cured with a certain resin curing time. Improves.
[0034]
FIG. 1 shows a cross-sectional view of a flip-chip mounting structure when a bump 2 is manufactured using solder bumps as an example of the present embodiment in which mounting is completed. In FIG. 1, the solder 5 pre-coated on the pads 4 of the wiring substrate 3 and the bumps 2 that are the protruding electrodes of the semiconductor device 1 are metal-bonded at corresponding positions, whereby the semiconductor device 1 and the wiring are connected. The board 3 is electrically connected. The sealing resin between the semiconductor device 1 and the wiring board 3 is composed of a thermosetting resin 6.
[0035]
Examples of the material of the solder 5 include Sn / Pb eutectic solder, but are not limited to Sn / Pb eutectic solder. For example, Sn / Pb (excluding eutectic), Sn / Ag, Sn / Cu, Sn / P Examples thereof include Sb, Sn / Zn, Sn / Bi, and materials obtained by further adding a specific additive element to the above-described materials, and these are used as appropriate. The bump 2 may be the same as or different from the solder 5 and may be a solder having a different melting point. A frequently used material is Pb-rich Sn / Pb. An example of the different material is an Au bump.
[0036]
In addition, the electrical connection portion is protected between the semiconductor device 1 and the wiring substrate 3 except for the electrical connection portion, and thermal stress generated due to the difference in thermal expansion coefficient between the semiconductor device 1 and the wiring substrate 3 is caused by the electrical connection portion. The resin is sealed with the thermosetting resin 6 for the purpose of alleviating concentration on the surface and improving connection reliability.
[0037]
As the thermosetting resin 6, it is desirable to use an active resin (thermosetting resin having an effect of removing the solder oxide film) when performing solder connection. For example, it is the structure which added the agent which has a flux effect to the thermosetting resin 6 used as a base material, and has the effect | action which removes the oxide film of a solder and a to-be-soldered connection surface. That is, the agent having a flux action acts in the heated state before hardening in the solder connection, and the solder and the oxide film on the soldered connection surface are removed. The active resin becomes chemically stable by being bonded to the base resin after curing, and has sufficient electrical insulation.
[0038]
Moreover, in order to give a flux action to the thermosetting resin 6, unsaturated acids such as (meth) acrylic acid and maleic acid, organic diacids such as oxalic acid and malonic acid, organic acids such as citric acid, and hydrocarbons This is possible by adding at least one halogen group, hydroxyl group, nitrile group, benzyl group, carboxyl group or the like to the side chain. Further, unsaturated alcohols such as (meth) acrylic alcohol, trimellitic acid, tetramellitic acid and generally known chelating agents can also be used. Two or more kinds of such agents having the flux action can be used in combination. In addition, a well-known gelatinizer can also be included in a flux.
[0039]
Further, in the semiconductor device mounting process, the use of an active resin for the thermosetting resin 6 eliminates the need to use flux, so that the flux cleaning process can be omitted, and it is caused by a flux residue caused by poor cleaning. An adverse effect on reliability can be prevented.
[0040]
Thermosetting resin base materials include epoxy, polyester (unsaturated polyester, combination of unsaturated polyester and compound having active hydrogen group), acrylate (silicon acrylate such as (meth) acryloxypropylpolysiloxane, epoxy acrylate) Etc.). An accelerator that accelerates curing by reacting with the above-described thermosetting resin at the time of thermosetting, and / or a curing agent (a radical initiator, an anionic initiator, or a cationic initiator that generates radicals for curing by heating), etc. have. An adhesive such as α-cyanoacrylate that cures at room temperature can also be used. The thermosetting resin, accelerator, curing agent, initiator and the like can be used in combination of two or more. Furthermore, a filler such as silica may be added to the thermosetting resin for the purpose of adjusting the coefficient of thermal expansion and improving the connection reliability.
[0041]
In addition, in order to reliably solder-connect the bump-formed semiconductor device 1 in a short time, it is possible to pressurize together with heating at the time of mounting, or to solder-connect by vibration.
[0042]
FIG. 3 is a diagram showing an embodiment of the present invention using solder bumps when no preliminary solder is formed on the printed wiring board 3. The mounting method is the same as the example shown in FIG. 2, but in this case, the position where the gap between the semiconductor device 1 and the wiring board 3 is kept constant so that the bumps 2 are not crushed during heating and pressing. Control is required.
[0043]
【Example】
The embodiments of the present invention will be described in more detail with reference to the drawings in order to explain the embodiment and the like of the present invention in more detail. In this embodiment, when the semiconductor device is mounted on the wiring substrate coated with the thermosetting resin by the above mounting method, the outside air remains in the recesses between the protruding electrodes on the semiconductor device side, and becomes a void. The following experiment was conducted to confirm that no defects occurred and to confirm the connection reliability at that time. First, the equipment used will be explained.
[0044]
The semiconductor device 1 has a size of 10 mm □ and a full grid area arrangement in which solder bumps are arranged on the entire surface of the semiconductor device 1 at a pitch of 0.24 mm. The solder bump material is Pb 95% and Sn 5%. The wiring board 3 is provided with electrodes corresponding to the semiconductor device 1, and preliminary solder is formed on the pads 4 at a height of about 20 μm. The preliminary solder material is eutectic solder. The mounted semiconductor device 1 and the wiring board 3 have a structure in which electrical connection can be confirmed.
[0045]
The thermosetting resin 6 is an epoxy, which is a resin having a solder oxide film removing action, using a resin A using a phenolic curing agent and a resin B using an acid anhydride curing agent. Further, evaluations were made on those resins to which silica filler was added. Here, the thermosetting resin 6 is not limited to epoxy, but may be polyester or acrylate as described above.
[0046]
Next, a mounting method will be described.
[0047]
First, the Ar plasma treatment was performed on the semiconductor device 1 to improve the wettability between the semiconductor device 1 and the resin 6 and the connectivity between the solder bumps 2 by the plasma surface modification effect. Subsequently, the wiring board 3 was placed on the stage 8, and about 20 mg of the thermosetting resin 6 was applied to the central portion of the wiring board 3 on which the semiconductor device 1 is mounted using a dispenser. Subsequently, the semiconductor device 1 is attracted to the tool 7, aligned with the wiring board 3, the semiconductor device 1 is mounted on the wiring board 3, and the solder bumps 2 of the semiconductor device 1 and the spare wiring board 3 are reserved. After contact with the solder 5, 3 g / bump was applied for 5 seconds while heating the semiconductor device 1 at 230 ° C., and solder connection between the electrodes was performed. In addition, although the method which does not pressurize was also tried at the time of connection, in this case, the resin with the filler addition amount of 40% or more was not connected because solder wettability occurred at most connection portions.
[0048]
Subsequently, the mounted product in which the solder connection was completed was placed in a thermostatic chamber in a 150 ° C. air atmosphere for 90 minutes, and the thermosetting resin 6 was cured to complete the mounting.
[0049]
As a void evaluation at the time of mounting the semiconductor device, a comparative evaluation was performed by changing the mounting speed of the semiconductor device 1 and the temperature conditions of the stage 8 and the tool 7. Table 1 shows the relationship between the temperature and the resin viscosity in the resin used in this example. It can be seen that the resin viscosity is considerably reduced at 50 ° C. as compared to 25 ° C., and that the resin viscosity suddenly decreases with increasing temperature from around 70 ° C.
[0050]
Table 2 shows the details of the evaluation conditions and the results. Table 2 shows the results of void observation when the tool temperature and stage temperature are changed by slowing the mounting speed with respect to the conventional conditions where the mounting speed is high at normal temperature. With respect to the temperature condition in which no void was generated under the condition of 2, the filler observation result when the filler was added to the resin and the mounting speed was increased is shown. As a method for observing the void, the cross section of the resin layer portion was observed with a microscope for the sample for which mounting was completed.
[0051]
Moreover, the profile figure which shows the heating at the time of each mounting and tool displacement is shown in FIG. 4 thru | or FIG. The numbers in the mounting profile column in Table 2 or Table 3 correspond to the numbers in FIGS. 4 to 6 show the time point (1) when the solder bump and the thermosetting resin are in contact, and (2) time point when the solder bump and the substrate (pad on the substrate) are in contact. The tool temperature has been raised to a temperature equal to or higher than the melting point of the solder bump since (2). In Tables 2 and 3, the tool temperature is the temperature at the time when the solder bump contacts the thermosetting resin.
[0052]
[Table 1]
Figure 0004626839
[0053]
[Table 2]
Figure 0004626839
[0054]
[Table 3]
Figure 0004626839
[0055]
Regarding Table 2, in the case of the conventional conditions in which the tool and the stage were mounted at room temperature at 40 mm / s, a large number occurred on the entire surface of the sealing resin. On the other hand, when the mounting speed was slowed down to 0.1 mm / s just before the semiconductor device and the resin contacted, it was confirmed that the void was reduced, but the void remained mainly in the central portion where the resin was applied. The void was not completely eliminated. Furthermore, when the tool and stage temperature were changed, no void was generated when the tool temperature was 150 ° C. and the stage temperature was 60 ° C. or less.
[0056]
Next, as shown in Table 3, in the temperature conditions of the tool temperature of 150 ° C. and the stage temperature of 60 ° C. in which no voids were generated, the mounting speed was again 40 mm / s, including the resin added with the silica filler, Void observation was performed. As a result, voids were not generated up to 40% filler addition, but voids were generated when the filler addition amount was 60%. Therefore, with respect to the filler addition amount of 60%, when the mounting speed was 10 mm / s with this temperature condition, no void was generated.
[0057]
From this result, when the filler addition amount is 40% or less, the semiconductor device 1 side is heated at a higher temperature than the wiring substrate 3 side, and when the thermosetting resin 6 comes into contact with the semiconductor device 1, the semiconductor It has been confirmed that voids when the semiconductor device 1 is mounted can be prevented by performing this mounting method that creates a situation in which the thermosetting resin 6 is easily wetted on the device 1 side. Here, the tool temperature is set to 150 ° C. However, if the tool temperature is higher than that of the substrate 3, the tool temperature varies depending on the mounting speed of the semiconductor device 1 and the change in resin viscosity depending on the temperature of the thermosetting resin 6 to be used. Of course, things are possible.
[0058]
Further, a resin having a high filler addition ratio and a resin viscosity of 40 Pa · s (at 25 ° C.) or more can prevent voids when the semiconductor device is mounted by reducing the mounting speed together with the heating on the semiconductor device side. It was confirmed. Of these samples, those with a filler addition amount of 40% or more were subjected to a temperature cycle test of −40 ° C. to 125 ° C. and the connection reliability was evaluated. I confirmed that it was made. From this result, it was confirmed that a mounting product having no void in the resin layer and having high connection reliability can be obtained by the mounting method of the present invention.
[0059]
【The invention's effect】
As described above, according to the semiconductor device mounting method of the present invention, when the semiconductor device is mounted on the wiring board after the thermosetting resin is applied on the wiring board, the semiconductor device and the thermosetting resin are separated from each other. By heating the semiconductor device at a temperature at least higher than that of the wiring board before contact, or by reducing or temporarily stopping the mounting speed of the semiconductor device, or by combining these, the thermosetting resin is easily wetted on the semiconductor device side. In addition to preventing voids that are likely to occur in the resin layer, it is possible to make solder connections even with the use of thermosetting resins with added silica filler and adjusted thermal expansion coefficient. Can be obtained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a flip chip mounting structure mounted by a mounting method of the present invention.
FIG. 2 is a process cross-sectional view showing a mounting method of the present invention when preliminary solder is formed on a wiring board.
FIG. 3 is a process cross-sectional view illustrating the mounting method of the present invention when preliminary solder is not formed on the wiring board.
FIG. 4 is a profile diagram showing heating and tool displacement when a semiconductor device is mounted.
FIG. 5 is a profile diagram showing heating and tool displacement when a semiconductor device is mounted.
FIG. 6 is a profile diagram showing heating and tool displacement when a semiconductor device is mounted.
FIG. 7 is a process cross-sectional view illustrating a mounting method in the case of performing solder bonding with a conventional flux.
FIG. 8 is a process cross-sectional view showing a mounting method for mounting a semiconductor device by applying resin to a conventional wiring board.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Bump 3 Wiring board 4 Pad (wiring board)
5 Solder 6 Thermosetting resin 7 Tool 8 Stage 9 Pad (semiconductor device)
10 Flux

Claims (3)

半導体装置の電極と配線基板の電極とがバンプを介して電気的に接続され、前記半導体装置と前記配線基板との間を熱硬化性樹脂により封止してなる半導体装置の実装方法において、
前記配線基板上に熱硬化性樹脂を塗布する工程と、前記半導体装置を前記配線基板上に搭載するに際し、前記半導体装置と前記熱硬化性樹脂とが接触する直前に、前記半導体装置を載置するツールの移動速度を減速又は一旦停止させる工程と、前記半導体装置の電極と前記配線基板の電極とが前記バンプを介して接触した状態で、前記半導体装置を加熱して前記半導体装置の電極と前記配線基板間の電極とを電気的に接続するバンプ接続工程と、前記半導体装置の搭載が完了した前記配線基板を、前記バンプ接続工程以下の温度雰囲気中に保持し、前記熱硬化性樹脂を硬化させる樹脂硬化工程と、を含むこと特徴とする半導体装置の実装方法。In the mounting method of the semiconductor device, wherein the electrode of the semiconductor device and the electrode of the wiring substrate are electrically connected via bumps, and the space between the semiconductor device and the wiring substrate is sealed with a thermosetting resin.
Placing a step of applying the thermosetting resin on the wiring substrate, upon mounting the semiconductor device on the wiring board, immediately before said semiconductor device with said thermosetting resin is in contact, the semiconductor device Decelerating or temporarily stopping the moving speed of the tool, and heating the semiconductor device in a state where the electrode of the semiconductor device and the electrode of the wiring board are in contact with each other via the bump. A bump connection step for electrically connecting electrodes between the wiring substrates, and the wiring substrate on which mounting of the semiconductor device is completed is held in a temperature atmosphere below the bump connection step, and the thermosetting resin is A method of mounting a semiconductor device, comprising: a resin curing step of curing. 前記半導体装置と前記熱硬化性樹脂とが接触する前における前記ツールの移動速度が、略１０ｍｍ／ｓ以下に設定されることを特徴とする請求項１に記載の半導体装置の実装方法。The method for mounting a semiconductor device according to claim 1, wherein a moving speed of the tool before the semiconductor device and the thermosetting resin come into contact with each other is set to about 10 mm / s or less . 半導体装置の電極と配線基板の電極とがバンプを介して電気的に接続され、前記半導体装置と前記配線基板との間を熱硬化性樹脂により封止してなる半導体装置の実装方法において、
前記配線基板上に熱硬化性樹脂を塗布する工程と、前記半導体装置を前記配線基板上に搭載するに際し、前記半導体装置と前記熱硬化性樹脂とが接触する前に、前記半導体装置を少なくとも前記配線基板より高い温度で加熱する予備加熱工程と、前記半導体装置と前記熱硬化性樹脂とが接触する直前に、前記半導体装置を載置するツールの移動速度を減速又は一旦停止させる工程と、前記半導体装置の電極と前記配線基板の電極とが前記バンプを介して接触した状態で、前記半導体装置を前記予備加熱工程以上の温度に加熱して前記半導体装置の電極と前記配線基板間の電極とを電気的に接続するバンプ接続工程と、前記半導体装置の搭載が完了した前記配線基板を、前記バンプ接続工程以下の温度雰囲気中に保持し、前記熱硬化性樹脂を硬化させる樹脂硬化工程と、を含むこと特徴とする半導体装置の実装方法。 In the mounting method of the semiconductor device, wherein the electrode of the semiconductor device and the electrode of the wiring substrate are electrically connected via bumps, and the space between the semiconductor device and the wiring substrate is sealed with a thermosetting resin.
A step of applying a thermosetting resin on the wiring board; and when mounting the semiconductor device on the wiring board, before the semiconductor device and the thermosetting resin contact each other, the semiconductor device is at least A preheating step of heating at a temperature higher than the wiring substrate, a step of decelerating or temporarily stopping a moving speed of a tool on which the semiconductor device is placed, immediately before the semiconductor device and the thermosetting resin are in contact with each other; With the electrode of the semiconductor device and the electrode of the wiring substrate in contact with each other via the bump, the semiconductor device is heated to a temperature equal to or higher than the preheating step, and the electrode of the semiconductor device and the electrode between the wiring substrate and A bump connection step for electrically connecting the semiconductor device, and the wiring board on which the semiconductor device has been mounted is held in a temperature atmosphere equal to or lower than the bump connection step, and the thermosetting resin is hardened. Mounting method of a semiconductor device comprising: the resin curing step of, between this and the characteristics, including.
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