JPH03171643A - Jointing of metal member, method and device for manufacture of semiconductor integrated circuit device using same - Google Patents

Abstract

PURPOSE:To reduce heat damage to a semiconductor chip and to realize a reduction in a reflow time and a reduction in the size of a reflow furnace by a method wherein an atomic beam or an ion energy beam is irradiated on the joint surfaces of a pair of metal members housed in a vacuum container and thereafter, the metal members are transferred to a container, in which a high-purity inert gas-containing atmosphere is formed, and the joint surfaces of the metal members are pressure-welded to each other under normal pressures. CONSTITUTION:A pair of source guns 18 for transforming Ar gas introduced in a surface activating chamber 17 into an atom beam are installed in the chamber 17 and a semiconductor chip 5 and a package substrate 3 are irradiated with this atomic beam. Thereby, an activating treatment is performed on the surfaces of CCB bumps 2 and electrodes 4. After that, the chip 5 and the substrate 3 are immediately transferred to a jointing chamber 20 as they are respectively housed in trays 15a and 15b through a second load-lock chamber 19. A high-purity inert gas-containing atmosphere of normal pressures is formed in the chamber 20. A temporary jointing mechanism and a fusion jointing mechanism are provided in the interior of the chamber 20 and the temporary jointing and the final jointing are performed using these mechanisms.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a metal bonding method and a manufacturing technology of semiconductor integrated circuit devices using the same.
ip chip) method, T A B (Tape A
The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device using an automated bonding method.

[Conventional technology]

In recent years, in logic LSIs such as gate arrays and microcomputers, the number of terminals (output pins) for connecting with external circuits has rapidly increased as integrated circuits have become more multifunctional and denser. The wire bonding method, in which wires are connected to bonding holes provided at the edges of a semiconductor chip to connect external circuits, has reached its limit. In addition, the wire bonding method has the disadvantage that the wiring in the internal circuit area must be routed to the bonding pad in the peripheral area, which increases the wiring length, resulting in a delay in signal transmission speed. This is not suitable as a mounting method for logic LSIs that require high performance.

For these reasons, the flip-chip method, in which a CCB bump (bump, protruding electrode) made of a solder material is bonded onto the A1 electrode of a semiconductor chip, and the semiconductor chip is mounted on a substrate via this CCB bump, and the above-mentioned Al A on the electrode
The TAB method is attracting attention in which bumps made of a u/Sn eutectic alloy are bonded and a semiconductor chip is mounted via the bumps on leads formed on the main surface of an insulating film. In particular, the Frisob chip method is an extremely effective mounting method for increasing the number of bins of semiconductor chips because it is possible to provide terminals not only in the periphery of the semiconductor chip but also in the internal circuit area. Furthermore, since the wiring length is shortened by providing terminals in the internal circuit area, it is extremely useful as a mounting method for high-speed logic LSIs.

Conventionally, solder vapor deposition and solder ball supply methods have been used as methods for forming CCB bumps, which are categorized into the above-mentioned flip-chip method. For example, in the solder vapor deposition method, CCB bumps are formed as follows.

First, on the All electrode of the semiconductor chip, for example, Cr, C
A solder base layer (
BLM; Bump Limiting Me
tallurgy). Of the solder base layers, Cr in the lowest layer is provided to prevent an alloying reaction between the solder bumps and the AA electrode, and Cu in the intermediate layer is provided to improve solder wettability. Further, the uppermost layer of Au is provided to prevent corrosion of the lower layer of Cu.

Next, after selectively depositing a solder film made of a Pb/Sn alloy or the like on the solder base layer, this solder film is heated and melted in a melting furnace with an inert gas atmosphere. Spherical CCB bumps are created using surface tension. On the other hand, the solder ball supply method, published in July 1987, for example,
As described in "Welding Techniques" on pages 88 to 91, after completely removing contaminants such as oxides, moisture, and fats and oils adhering to the surface of the Af electrode by ion bombardment, spherical solder is formed in an ultra-high vacuum. This is a method of joining balls by overlapping them.

One of the semiconductor integrated circuit devices using the flip-chip method is the chip carrier.
There is. Regarding this chip carrier, for example, JP-A-62-249429, JP-A-63-3-10139,
It is stated in the issue bulletin etc.

FIG. 15 shows a cross-sectional structure of the chip carrier described in the above-mentioned document. This chip carrier 50 includes a package substrate 5l made of a ceramic material such as mullite.
It has a package structure in which a semiconductor chip 54 is hermetically sealed with a cap 55, which is connected to an electrode 52 formed on the main surface of the semiconductor chip 54 via a CCB bump 53. The cap 55 is made of aluminum nitride (A f N), for example, and is bonded to the main surface of the package substrate 51 via a sealing solder 56 .

The back surface (upper surface) of the semiconductor chip 54 is bonded to the lower surface of the cap 55 via heat transfer solder 57. this is,
This is to transfer heat generated from the semiconductor chip 54 to the cap 55 through the solder 57. Furthermore, CCB bumps 58 are formed on the electrodes 52 on the lower surface of the package substrate 51 for mounting the chip carrier 50 on a modular substrate or the like. After the assembly of the chip carrier 50 is completed, the CCB bumps 58 are bonded to the electrodes 52 by, for example, a solder ball supply method.

An internal wiring 59 made of, for example, W (tungsten) is formed inside the package substrate 51, and electrodes 52 and 52 on the main surface and the bottom surface of the package substrate 51 are electrically connected through this internal wiring 59. There is.

To assemble the chip carrier, first, a chip mounting device is used to accurately position the CCB bumps of the semiconductor chip on the electrodes on the main surface of the package substrate. At this time, flux is applied to the joint between the CCB bump and the electrode. Flux is applied for the purpose of removing a natural oxide film formed on the surface of the solder constituting the CCB bump and preventing re-oxidation of the solder surface during reflow. Further, flux is applied for the purpose of improving solder wettability during reflow.

Subsequently, the package substrate is transferred to a reflow oven.

At this time, it is necessary to prevent displacement of the CCB bump due to vibrations, and the flux also plays a role in preventing this displacement. Then, an inert gas atmosphere is created in the reflow oven, and the CCB bumps are heated and remelted in the atmosphere to perform face-down bonding of the semiconductor chip to the main surface of the package substrate.

Next, a cap is soldered to the main surface of the package substrate using sealing solder. Further, the back surface of the semiconductor chip is soldered to the bottom surface of the cap using heat transfer solder. To solder the cap to the main surface of the package board, apply preliminary solder for sealing to the main surface of the package board and the legs of the cap in advance, and then apply flux to the surface of this preliminary solder. After that, a cap is mounted on the main surface of the package substrate, and then the preliminary solder is heated and remelted in a reflow oven. To solder the back of the semiconductor chip to the bottom of the cap, apply preliminary solder to the bottom of the cap or the back of the semiconductor chip in advance, and then apply flux to the surface of this preliminary solder. After that, this preliminary solder is heated and remelted in the reflow oven.

The operation of soldering the cap to the main surface of the package substrate and the operation of soldering the back surface of the semiconductor chip to the lower surface of the cap are performed in the same process. Therefore, the sealing solder and the heat transfer solder are made of solder materials having approximately the same melting temperature. In addition, the sealing solder and the heat transfer solder are made of solder having a lower melting temperature than the solder that protects the CCB bump. Otherwise, the CCB bump will remelt when the pre-solder is heated and melted in the reflow oven, and the CCB bump will be damaged by the load of the cap.
This is because the CB bumps are crushed, resulting in short circuits between adjacent CCB bumps. For this reason, for CCB bump 1, for example, about 2 to 3% by weight of S.
P b /S n alloy containing n (melting temperature = 32
The sealing solder and the heat transfer solder contain, for example, about 10% by weight of S.
P b /S n alloy containing n (melting temperature = 29
The solder is made of a low melting point solder (about 0 to 300°C).

In this way, the chip carrier assembly process involves mounting the semiconductor chip on the main surface of the package substrate via CCB bumps, and hermetically sealing the semiconductor chip by soldering a cap to the main surface of the package substrate. Since this method involves a step of soldering the back surface of the semiconductor chip to the bottom surface of the cap, the quality of the soldering greatly affects the connection reliability of the CCB bumps, the hermetic reliability of the package, and the cooling efficiency.

In addition, as another method for joining solder balls, as described in "Welding Technology" published in July 1987, pages 88 to 91, there is a method to remove contaminants such as oxides, moisture, oil, and fats adhering to the joining surface. A method is also known in which the material is completely removed by ion bombardment and then the materials are stacked and bonded in an ultra-high vacuum.

[Problem to be solved by the invention]

The TAB method and flip-chip method have the following problems.

First, in the TAB method, bumps containing expensive Au are formed on the AI electrodes of the semiconductor chip.
It has been pointed out that there is a problem of increased manufacturing costs.

On the other hand, the flip-chip method has the following problems.

■After the reflow process, a flux cleaning process is required, which increases the number of mounting processes.

Additionally, the use of cleaning liquids such as chloro hydrocarbons and fluoro hydrocarbons used in the flux cleaning process is being regulated from the standpoint of protecting the natural environment, and from this perspective, there is an urgent need to abolish the flux cleaning process. .

■Even if flux is cleaned, it is difficult to completely remove it, so corrosion of integrated circuit wiring due to flag residue is unavoidable. In addition, flux residue induces defects such as voids in solder joints, leading to a decrease in the connection reliability of CCB bumps, and in the case of chip carriers, it can further decrease the hermetic reliability of the package and the cooling efficiency. cause etc.

■Even if flux is used, it is difficult to remove the natural oxide film formed on the solder surface in a short time. Therefore, when heating and remelting the solder in a reflow oven, the temperature inside the oven must be made much higher than the solder melting temperature, so thermal damage to the semiconductor chip is unavoidable. Furthermore, since it takes a long time for the solder to remelt, the reflow oven becomes large.

■Ultra-high vacuum area (10-' to 10-” Tor
r) Handling such as chucking, moving, and positioning of the materials to be joined is difficult, and mass productivity is poor. That is, in order to grasp the materials to be joined in a vacuum chamber, move them to a predetermined position, overlap the joining surfaces, and join them, the mechanism becomes extremely complicated, and it becomes difficult to join them with high dimensional accuracy. Also, in a vacuum, there is a problem of adhesion on mechanical sliding parts.

■Ion beam irradiation is difficult to apply to semiconductors (such as LSI) and ceramics. That is, since the surface of a semiconductor chip is generally covered with an insulating film, ion beam irradiation causes damage to the device due to charging (charge-up). Furthermore, it is difficult to clean the joint surface of highly insulating ceramics by direct ion beam irradiation.

■ Conventional bonding methods had the problem that the bonding surfaces had to be finished extremely smooth in order to ensure sufficient adhesion between the bonding surfaces. In reality, bonding surfaces are uneven, and even when they are stacked on top of each other, they hardly stick together (the vacuum connection area is very small).Therefore, the bonding surfaces must be made ultra-smooth.

An object of the present invention is to provide a technique that can solve the above-mentioned problems associated with the use of flux in a flip-chip type semiconductor integrated circuit device.

Another object of the present invention is to provide a technique that can reduce the manufacturing cost of a TAB type semiconductor integrated circuit device.

Still another object of the present invention is to provide a joining technique that is easy to handle and suitable for mass production.

Still another object of the present invention is to provide a technique for cleaning the bonding surfaces of insulating materials such as semiconductor chips and ceramics.

Still another object of the present invention is to provide a technique for making the joining surface ultra-smooth.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

The flip chip manufacturing method, which is one of the inventions of the present application, is based on CC
When face-down bonding a semiconductor chip to a substrate via a B bump, the semiconductor chip and substrate are first housed in a vacuum container, and the surfaces of the CCB bumps and electrodes of the substrate are irradiated with an energy beam of atoms or ions. After cleaning the bonding surfaces, the semiconductor chip and substrate were transferred to a container with a high-purity inert gas atmosphere, and temporary bonding was performed by pressing the CCB bumps against the electrodes under normal pressure (about 1 atmosphere). , a method in which the CCB bumps are bonded by reflow soldering. Note that in order to form the high-purity inert gas atmosphere, for example, oil and fat content and oxygen are both 10 ppb.
Hereinafter, a single gas or a mixed gas with a moisture content of 100 ppb or less and a dew point of -70°C or less will be used.

The method for manufacturing a flip chip, which is another invention of the present application, is
The CB bump is made of non-eutectic solder, and after the non-eutectic solder is melted and immediately rapidly cooled, a eutectic solder layer or a nearby solder layer is segregated on its surface. , is a method of performing face-down bonding by a method similar to the above invention.

In a method for manufacturing a TAB, which is still another invention of the present application, when gang bonding a semiconductor chip to leads formed on the main surface of an insulating film via bumps, the semiconductor chip and the insulating film are first housed in a vacuum container. After irradiating the surfaces of the bumps and the leads with an energy beam of atoms or ions, the semiconductor chip and the insulating film are immediately transferred to a container with a high-purity inert gas atmosphere, and the leads are attached to the bumps in this container. This is a method of performing gang bonding by pressure contact.

A metal bonding method according to still another invention of the present application includes irradiating the bonding surfaces of a pair of metal members housed in a vacuum container with an energy beam of atoms or ions, and then moving the metal members into a container with a high-purity inert gas atmosphere. In this method, the joint surfaces are brought into pressure contact with each other under normal pressure. When the joint surfaces are pressed together, the metal part may be heated to a temperature below its melting temperature. Alternatively, a metal softer than the metal to be joined may be formed in advance on at least one surface of the metal member, and the joining may be performed using plastic deformation of the soft metal. At that time, the joint may be heated to lower the yield point of the soft metal in order to lower the joining pressure.

[Effect]

According to the method for manufacturing a flip chip, which is one of the inventions of the present application, the following effects are achieved.

■By irradiating the surface of the CCB bump and the surface of the electrode of the substrate with an energy beam of atoms or ions,
Since the natural oxide film and foreign matter are removed by the spatter effect, the surface of the CCB pump and the surface of the electrode can be activated.

■After the surface activation treatment by irradiation with the energy beam, the semiconductor chip and substrate are immediately transferred to a container with a high-purity inert gas atmosphere for temporary bonding and reflow, thereby forming a natural oxide film on the surface of the CCB bump. It is possible to prevent re-formation and re-adhesion of foreign substances.

(2) When the energy beam is an electrically neutral atomic beam, unlike an ion beam, the irradiated surface is not charged, so that damage to the semiconductor chip due to the irradiation can be reduced. Furthermore, the surface of insulating materials such as glass, ceramics, or plastic can be easily cleaned by irradiation with the atomic beam. On the other hand, in order to clean the surface of an insulating material by irradiation with an ion beam, it is preferable to simultaneously irradiate an electron shower to neutralize the ion charges.

(2) Prior to the reflow process, by press-contacting the CCB bumps to the electrodes of the substrate for temporary bonding, it is possible to prevent the CCB bumps from shifting due to vibrations or the like when the substrate is transferred to the reflow process.

(2) According to (1) to (2) above, flux is not required when face-down bonding a semiconductor chip to a substrate via a CCB bump.

(2) By performing reflow without a natural oxide film on the surface of the CCB bump, the CCB bump can be melted at a temperature lower than its melting temperature, thereby reducing thermal damage to the semiconductor chip. Further, the time required for the CCB bump to melt and the subsequent cooling time can be shortened, and the reflow oven can be downsized.

■ By temporarily bonding the CCB bumps to the electrodes of the substrate by pressing them, it is possible to bring the CCB bumps into complete contact with the electrodes prior to the reflow process. Poor connection of bumps can be prevented.

According to the flip chip manufacturing method, which is another invention of the present application, by pre-segregating a eutectic solder layer or a solder layer with a similar composition to the surface of the CCB bump made of non-eutectic solder, the solder The eutectic point of (eutectic point, approx. 18
Since reflow can be performed at a temperature around 3℃,
Thermal damage to the semiconductor chip can be further reduced. Moreover, it is possible to further promote shortening of reflow time and miniaturization of a reflow oven.

According to the method for manufacturing the TAB, which is still another aspect of the present invention, the bumps can be formed using a metal material that is cheaper than Au, so the manufacturing cost of the TAB can be reduced.

According to the metal joining method which is still another invention of the present application, by heating the metals to be joined, the metals to be joined themselves are softened, and the adhesion of the joining surfaces is improved.

Further, by forming a metal softer than the metal to be joined in advance on the joint surface, the adhesion of the joint surface can be easily improved by utilizing the plastic deformation of the soft metal.

〔Example〕

FIG. 14 shows a cross-sectional structure of the chip carrier 1 obtained by the manufacturing method of this example.

This chip carrier 1 has a package structure in which a semiconductor chip 5 is face-down bonded onto an electrode 4 on the main surface of a package substrate 3 via a CCB bump 2 and hermetically sealed with a cap 6. The cap 6 is soldered to the main surface of the socket cage substrate 3 via a sealing solder 7, and the back surface of the semiconductor chip 5 is soldered to the bottom surface of the cap 6 via a heat transfer solder 8. ing. A CCB bump 9 having a larger diameter than the CCB bump 2 is bonded to the electrode 4 on the lower surface of the package substrate 3 .

This CCB bump 9 is connected to an internal wiring 10 made of W (tungsten), etc., provided inside the package substrate 3.
It is electrically connected to the CCB bump 2 and further to the semiconductor chip 5 through it. The CCB bumps 9 serve as external terminals when the chip carrier 1 is mounted on the module substrate, and are bonded to the electrodes 4 on the lower surface of the package substrate 3 after the hermetic sealing process of the chip carrier 1 is completed.

At the periphery of the main surface of the package substrate 3 and the legs of the cap 6, a solder metallized layer is formed of a composite metal film such as Ti/Ni/Au or 'v\/Ni/Au. 11 is formed as necessary.

Furthermore, a solder metallized layer 11 made of the composite metal film is formed on the lower surface of the cap 6 as required. These solder metallized layers 1l mainly contain sealing solder 7.
It is formed for the purpose of improving the wettability of the heat transfer solder 8.

Note that the package substrate 3 is made of a ceramic material such as mullite, and the cap 6 is made of, for example, aluminum nitride (AIIN). The CCB bump 2 is made of, for example, Pb containing about 2 to 3% by weight of Sn.
/Sn alloy (melting temperature = about 320-330℃)
The CCB bread 9 is made of, for example, a Sn/Ag alloy (melting temperature: about 220 to 230°C) containing about 3.5% by weight of Ag. The sealing solder 7 and the heat transfer solder 8 are made of, for example, a P′b/Sn alloy (melting temperature: about 290 to 300° C.) containing about 10% by weight of Sn.

FIG. 2 shows the main parts of a manufacturing apparatus 12 used in the assembly process of the chip carrier 1. As shown in FIG.

A load magazine 14a. 14b is digitized by one. One load magazine 14a has a large number of chip trays 1.
A predetermined number of semiconductor chips 5 are placed on each chip tray 15a. Each semiconductor chip 5 is placed with the surface to which the CCB bumps 2 are bonded facing upward. The other load magazine 14b
A large number of board trays 15b are accommodated in the board tray 15b, and a predetermined number of package boards 3 are placed on each board tray 15b. Each package substrate 3 is placed with its main surface facing upward.

Tray 15 accommodated in load magazines 14a, 14b
a, 15b are first transferred to the surface activation chamber 17 through the first load lock chamber l6.

This surface activation chamber 17 can be evacuated to a vacuum level of 10-' Torr or less. A pair of source guns 18 and 18 are installed in the surface activation chamber l7 to convert the Ar gas introduced into the chamber into an atomic beam, and by irradiating the semiconductor chip 5 and the package substrate 3 with this atomic beam, , CC (described later)
Surface activation treatment of the B bumps 2 and electrodes 4 is performed.

After the surface activation process is completed, the semiconductor chip 5 and the package substrate 3 are immediately transferred to the bonding chamber 2 through the second load lock chamber 19 while being accommodated in the trays 15a and 15b.
0. A high-purity inert gas atmosphere at normal pressure (approximately 1 atmosphere) is formed in this bonding chamber 20 . The high-purity inert gas atmosphere refers to an inert gas atmosphere such as nitrogen or Ar that has been chemically removed from moisture, oil, and oxygen through a gas purifier or the like.

Inside the bonding chamber 20, there are a chip inversion stage 21, a chip inversion unit 22, a chip mounting hand 23, a temporary bonding stage 24, a prism mirror 25, and a position recognition camera 26.
A temporary bonding mechanism consisting of a melt bonding stage 27, a heat block 28, a chip transfer hand 29, an alignment stage 30, etc. are provided.
Temporary bonding and permanent bonding, which will be described later, are performed using these mechanisms.

After the preliminary bonding and main bonding are completed, the package substrate 3 to which the semiconductor chip 5 is face-down bonded is
The third load lock chamber 3 is placed on the substrate tray 15b.
1 and is housed in the unload magazine 37.

Next, a method for assembling the chip carrier 1 using the manufacturing apparatus 12 will be described in detail.

First, as shown in FIG. 3, a solder film 40 is selectively formed on each electrode 4 of the semiconductor chip 5 using, for example, a solder vapor deposition method. The electrode 4 of the semiconductor chip 5 is made of Af, and a solder base layer made of a composite metal film of CrSCu and AU is deposited on the surface thereof. The solder film 40 is made of a non-eutectic Pb/Sn alloy (melting temperature: about 320 to 330°C) containing about 2 to 3% by weight of Sn.

Subsequently, the solder film 4o is heated and melted in a melting furnace in which an inert gas atmosphere such as nitrogen or Ar is formed, and a spherical ccB bump 2 is formed using the surface tension during melting. At that time, by immediately quenching the CCB bump 2, as shown in FIG. 4, a thin eutectic solder layer (or a The solder layer (41) of a nearby assembly is segregated. The melting point (eutectic point) of this eutectic solder layer 41 is CCB
The temperature is about 183° C., which is slightly lower than the melting temperature of the non-eutectic P b /S n alloy that constitutes the inner layer of the bump 2 .

Next, a predetermined number of the semiconductor chips 5 are placed on the chip tray 15.
the load magazine 14a of the manufacturing apparatus 12.
to be accommodated. Further, a predetermined number of package substrates 3 are placed on the substrate tray 15b and housed in the load magazine 14b.

Hereinafter, the process of face-down bonding the semiconductor chip 5 onto the main surface of the package substrate 3 will be explained according to the flow shown in FIG.

First, one chip tray 15a and one substrate tray 15b are transferred to the load lock chamber 16, and once this chamber is
After evacuating to a degree of vacuum of about 0-'Torr,
The chip tray 15a and substrate tray 15b are transferred to the surface activation chamber 17. This surface activation chamber 17 is evacuated in advance to a degree of vacuum of about 10 −1 Torr. Next, high-purity Ar gas (moisture in the 8R gas is 100ppb or less, dew point is -70°C or less) is supplied to the surface activation chamber 17, and the interior is heated to 10-3 to 10-100°C.
r. After achieving a certain degree of vacuum, the source gun 18 is activated to irradiate the semiconductor chip 5 and package substrate 3 with an Ar atomic beam generated from the source gun 18 for about 5 minutes. At that time, tray 15a. By rotating 15b, Ar is uniformly applied to the surface of the CCB bump 2 and the surface of the electrode 4.
Can irradiate with atomic beams.

In this way, by uniformly irradiating the semiconductor chip 5 and the package substrate 3 with the Ar atomic beam in the vacuum surface activation chamber 17, the natural oxide film on the surface of the CCB bump 2 and the surface of the electrode 4 is formed by the spatter effect. remove foreign substances and activate their surfaces.

Next, tray 15a. 15b is transferred from the surface activation chamber 17 to the second load opening ivy chamber 19. Load lock chamber 1
No. 9 is evacuated to a degree of vacuum of about 10 −3 to 10 Torr in advance. Next, high-purity nitrogen gas (or Ar gas) is supplied to the load port chamber 19 to bring the pressure inside the chamber to normal pressure (approximately 1 atm), and then the trays 15a and 15b are transferred to the bonding chamber 20, where the chips are bonded. The tray 15a is placed on the chip inversion stage 21, and the substrate tray 15b is placed on the temporary bonding stage 24. The bonding chamber 20 is supplied with the high-purity nitrogen gas (or Ar gas) in advance to maintain normal pressure inside.The high-purity gas supplied to the bonding chamber 20 is, for example, 10 to 20% nitrogen gas A reducing gas to which a certain amount of hydrogen gas is added may also be used.

In this way, after the surface activation treatment by Ar atomic beam irradiation, the semiconductor chip 5 and the package substrate 3 are immediately transferred to the bonding chamber 20 in a high-purity inert gas atmosphere. This prevents the natural oxide film from being reformed on the surface of the CCB bump 2 and the surface of the electrode 4 and foreign matter from re-adhering during the transfer to the CCB bump 20.

Next, as shown in FIG. 5(a), the push-up pins 32 embedded in the chip inversion stage 21 are
One semiconductor chip 5 is lifted up from the back surface of a. Then, as shown in FIG. 5(b), the semiconductor chip 5 is vacuum-adsorbed onto the lower end of the collet 33 which is kept in standby above the semiconductor chip 5. Next, Figure 5 (C
), after inverting the collet 33 by 180 degrees, the semiconductor chip 5 is vacuum-adsorbed to the lower end of the chip mounting hand 23 that is waiting above the collet 33, and the semiconductor chip 5 is placed on the temporary bonding stage 24. Transfer to.

During this transfer, the semiconductor chip 5 is heated by a heater (not shown) built into the chip mounting hand 23.The heating temperature is slightly lower than the melting point (183°C) of the eutectic solder (for example, 150°C). ℃).

As shown in FIG. 6, a predetermined number of package substrates 3 placed on a substrate tray 15b are waiting on the temporary bonding stage 24. After the chip mounting hand 23 with the semiconductor chip 5 sucked and held thereon is stopped above the temporary bonding stage 24, the image of the semiconductor chip 5 projected onto the prism mirror 25 is detected by the position recognition camera 26', and precision By driving the XY table 34, high-speed XY table 35, and rotary table 36, the position of each CCB bump 2 and the corresponding position of each electrode 4 are made to correspond accurately.

Subsequently, as shown in FIG. 7, the chip mounting hand 23 is lowered, and a zero point is placed on the back surface of the semiconductor chip 5. 5kgf/
The CCB bump 2 is pressed against the electrode 4 for about 10 seconds while applying a load of about crl. This allows C to be heated to a temperature somewhat lower than the melting point of the eutectic solder.
The CB bump 2 is easily plastically deformed and temporarily joined to the electrode 4.

In this way, by temporarily bonding the CCB bumps 2 to the electrodes 4 prior to the actual bonding, all the CCB bumps 2 are brought into complete contact with the electrodes 4, and variations in the diameter of the CCB bumps 2 and warpage of the package substrate 3 are avoided. This prevents a connection failure between the CCB bump 2 and the electrode 4 that may otherwise occur.

Next, the semiconductor chip 5 temporarily bonded to the main surface of the puff cage substrate 3 as described above is sucked and held by the chip mounting hand 23 again, and transferred to the melt bonding stage 27 together with the package substrate 3.

After temporarily bonding the CCB bump 2 to the electrode 4 in this way,
By transferring the package substrate 3 (and the semiconductor chip 5 temporarily bonded to its main surface) to the melting bonding stage 27, displacement between the CCB bumps 2 and the electrodes 4 due to vibrations during transfer is prevented.

Subsequently, as shown in FIG. 8, the heat block 28 installed above the melting bonding stage 27 is lowered, and while applying a load of approximately 0.5 to 5 kgf/cnt to the back surface of the semiconductor chip 5, the semiconductor chip 5 is heated. Heat chip 5. The heating temperature is somewhat higher (for example, 200° C.) than the melting point of the eutectic solder (183° C.).

Due to this addition, the thin eutectic solder layer 4l, which has been segregated on the surface of the CCB bump 2 in advance, melts and spreads into the inside of the CCB bump 2 and the inside of the electrode 4.
The B bump 2 and the electrode 4 are firmly bonded. Furthermore, by applying a load to the back surface of the semiconductor chip 5, the wettability of the melted eutectic solder layer 41 is improved.

After the semiconductor chip 5 is face-down bonded to the main surface of the puff cage substrate 3 as described above, the semiconductor chip 5 is adsorbed by the chip transfer node 29, and transferred together with the package substrate 3 to the alignment stage 30, where the substrate Place it on the tray 15a. After cooling the semiconductor chip 5 and the puff cage substrate 3 to room temperature, the substrate tray 15a is housed in the unload magazine 37 through the third load lock chamber, thereby completing the face-down bonding process.

As described above, in the face-down bonding process of this embodiment, the semiconductor chip 5 and the package substrate 3 are first irradiated with an Ar atomic beam in the vacuum surface activation chamber 17, thereby forming the surfaces of the CCB bumps 2 and the electrodes. 4
The natural oxide film and foreign matter on the surface of the semiconductor chip 5 and the package substrate 3 are removed, and then the semiconductor chip 5 and the package substrate 3 are immediately transferred to the bonding chamber 20 in a high-purity inert gas atmosphere, thereby transferring them from the surface activation chamber 17 to the bonding chamber 20. During this process, the natural oxide film is prevented from re-forming on the surface of the CCB bump 2 and the surface of the electrode 4, and foreign matter is prevented from re-adhering. Next, the CCB bump 2 is temporarily bonded to the electrode 4, and all CCB By bringing the bumps 2 into complete contact with the electrodes 4, poor connection between the CCB bumps 2 and the electrodes 4 due to variations in the diameter of the CCB bumps 2 or warping of the package substrate 3 can be prevented. By transferring the semiconductor chip 5) temporarily bonded to the main surface to the melting bonding stage 27, the CCB bumps 2 and electrodes 4 are
Then, the eutectic solder layer 41, which has been segregated in advance on the surface of the CCB bump 2, is spread inside the CCB bump 2 and the electrode 4 to connect the CCB bump 2 and the electrode 4. Join.

As a result, the semiconductor chip 5 can be face-down bonded to the main surface of the package substrate 3 at a temperature close to the melting point of the eutectic solder. Compared to the conventional technology that performs face-down bonding by reflowing, it is possible to significantly reduce thermal damage to semiconductor chips. ■Face-down bonding can be performed in a short time. ■The device can be made smaller.

Next, a process for hermetically sealing the semiconductor chip 5 by soldering the cap 6 to the main surface of the package substrate 3 will be described.

First, as shown in FIG. 9, preliminary sealing solder 7a and preliminary heat transfer solder 8a are applied to the surface of the solder metallized layer 1l formed on the cap 6. These preliminary solders 7a, 8a
are Pb containing approximately 10% by weight of Sn.
/Sn alloy (melting temperature = about 290 to 300°C). To apply the preliminary solder ?a, 8a, a solder preform (not shown) of a predetermined shape is placed on the solder metallized layer 11. This solder preform is then heated in a melting furnace with an inert gas atmosphere such as nitrogen or Ar.
melt.

The sealing preliminary solder 7a and the heat transfer preliminary solder 8a are
As shown in Figure O, the solder metallized layer l1 of the package substrate 3 after the face-down bonding process has been completed.
and the back surface of the semiconductor chip 5. Further, it may be applied to both the cap 6 and the package substrate 3. In the following description, a case will be described in which preliminary solder 7a, 8a is applied only to the cap 6 side (FIG. 9).

Next, a predetermined number of the caps 6 are placed on a dedicated cap tray (not shown) and housed in the load magazine 14a of the manufacturing apparatus 12. Further, a predetermined number of package substrates 3 that have undergone the face-down bonding process are placed on the substrate tray 15b and housed in the load magazine 14b.

Thereafter, surface activation treatment, temporary bonding, and reflow are performed in accordance with the face-down bonding process described above.

That is, one each of the cap tray and the substrate tray 15b is transferred to the surface activation chamber 17 through the load lock chamber l6, and sourced in a high purity Ar gas atmosphere of about 10-' to 10-' Torr. Activate gun 18 and press A
By uniformly irradiating the main surface of the package substrate 3 and the cap 6 with the r-atomic beam, natural oxide films and foreign substances on the surface of the preliminary solder 7a8a adhered to the cap 6 are removed and the surfaces thereof are activated. . At the same time, natural oxide films and foreign substances on the surface of the solder metallized layer l1 formed on the main surface of the package substrate 3 are removed, and the surfaces thereof are activated.

Next, the cap tray and substrate tray 15b are heated through the second load lock chamber 19 using high-purity nitrogen gas (or
The cap tray is placed on the chip inversion stage 2l, and the substrate tray 15b is placed on the temporary bonding stage 24. Then, the push-up pin 32 and the collet 3
3 to invert the cap 6 by 180 degrees, then use the chip mounting hand 23 to temporarily attach the cap 6 to the temporary bonding stage 2.
Transfer to 4. During this transfer, the cap 6 is heated by a heater built into the chip mounting hand 23.

Is the heating temperature pre-soldering? The temperature is somewhat lower (for example, 250° C.) than the melting temperature of a and 8a. Note that the eutectic solder layer 41 segregated on the surface of the CCB bump 2 spreads into the inside of the CCB bump 2 and the inside of the electrode 4 during the face-down bonding process, so the CCB bump The surface of 2 will not re-melt.

Next, the position of the cap 6 projected on the prism mirror 25 is detected by the position recognition camera 26, and the precision XY table 34, high speed After positioning, as shown in FIG. 11, the chip mounting hand 23 is lowered and the legs of the cap 6 are pressed against the main surface of the package substrate 3 (load: -0.5 to 5 kg f).
/ crl) 1; the cap 6 is temporarily bonded to the main surface of the package substrate 3, and the package substrate 3 (and the cap 6 temporarily bonded to the main surface thereof) is transferred to the melt bonding stage 27. This prevents misalignment between the cap 6 and the package substrate 3 due to vibration or the like.

Next, after transferring the cap 6 together with the package substrate 3 to the melting bonding stage 27 using the chip mounting hand 23, the heat block 28 is lowered as shown in FIG. ~5 kg f
/ cI1! The cap 6 is heated while applying a certain amount of load. This heating temperature is somewhat higher than the melting temperature of the preliminary solders 7a and 8a (for example, 310° C.). As a result of this heating, the preliminary sealing solder 7a and the preliminary heat transfer solder 8a are remelted. Cap 6 is package substrate 3
At the same time, the back surface of the semiconductor chip 5 is soldered to the lower surface of the cap. Further, by applying a load to the upper surface of the cap 6, the preliminary solder 7a,
The wettability of 8a is improved. Note that since the melting temperature of the CCB bump 2 is about 320 to 330°C, the preliminary solder 7a
, 8a are melted, the CCB bump 2 will not be melted again.

After the semiconductor chip 5 is hermetically sealed with the cap 6 as described above, the cap 6 is sucked by the chip transfer hand 29 and aligned with the package substrate 3 on the alignment stage 30.
After cooling to room temperature, the chips are stored in the unload magazine 37 through the third load lock chamber, thereby completing the airtight sealing process and the chip carrier 1 is completely sealed.

In this way, in the hermetic sealing process of this embodiment, the semiconductor chip 5 is heated at a temperature close to the melting temperature of the preliminary solders 7a and 3a.
Pre-solder so you can do an airtight seal? a, 8
Preliminary soldering in a glue flow furnace at a temperature much higher than the melting temperature of a? Compared to the conventional technique in which airtight sealing is performed by reflowing a and 8a, thermal damage to the semiconductor chip can be significantly reduced. (2) The semiconductor chip 5 can be hermetically sealed in a short time.

Next, a process of bonding the CCB bumps 9 to the electrodes 4 on the lower surface of the package substrate 3 will be explained.

First, as shown in FIG. 13, solder balls 9a are supplied to the main surface of a glass jig 43 in which a large number of holes 42 are formed, and one solder ball 9a is inserted into each hole 42. The number of holes 42 and their positions correspond to the number of electrodes 4 formed on the lower surface of package substrate 3 and their positions.

The solder ball 9a is made of an Sn/Ag alloy (melting temperature: about 220 to 230°C) containing about 3.5% by weight of Ag.

Next, a predetermined number of the glass jigs 43 are placed on a special tray.
(not shown) and housed in the load magazine 14a of the manufacturing apparatus l2.Also, a predetermined number of the chip carriers l are placed on the substrate tray 15b, and the load magazine 1
It is accommodated in 4b. The chip carrier l has its underside (CC
The electrode 4 to which the B bump 9 is to be bonded is placed with the side (on which the shaped surface) is facing upward.

Thereafter, surface activation treatment, temporary bonding, and reflow are performed in accordance with the face-down bonding process and hermetic sealing process.

That is, the glass jig 43 and the chip carrier 1 are transferred to the surface activation chamber 17 through the load lock chamber 16, and the solder balls 9a and the electrodes 4 are irradiated with an Ar atomic beam to remove the natural oxide film on their surfaces. remove foreign matter. Subsequently, the glass jig 43 and the chip carrier 1 are transferred to the bonding chamber 20 through the load lock chamber 19, and the chip carrier 1 is turned over by 180° to attach the electrode 4.
Temporary bonding is performed by pressing the solder ball 9a against the solder ball 9a.

This temporary bonding is performed at a temperature somewhat lower than the melting temperature of the solder balls 9a (for example, 150° C.). Next, the chip carrier l is transferred to the melting bonding stage 27, and the solder balls 9a are
at a temperature somewhat higher than its melting temperature (e.g. 250°C)
Heat it up. As a result, the solder ball 9a melts and the CCB bump 9 is joined to the electrode 4 (FIG. 14).

In this manner, in the bump bonding process of this embodiment, the CCB bumps 9 can be bonded to the electrodes 4 on the lower surface of the package substrate 3 at a temperature close to the melting temperature of the solder balls 9a and in a short time.

As described above, source gun 1 that generates an Ar atomic beam
A vacuum surface activation chamber 17 equipped with According to this embodiment, in which the chip carrier 1 is assembled (face-down bonding, hermetic sealing, and CCB bump bonding) by using a flux, good soldering can be performed without using flux in any process. It becomes possible. Therefore, (1) the flux application process and the flux cleaning process are unnecessary, and the number of assembly processes for the chip carrier 1 is reduced accordingly.

■It is possible to avoid wiring corrosion of integrated circuits caused by flux residue. ■Since defects in solder joints caused by flux residue can be avoided, it is possible to improve the connection reliability of the CCB bumps 2 and 9, and improve the airtight reliability and cooling efficiency of the chip carrier 1. .

As above, the invention made by the present inventor has been specifically explained based on Examples, but the present invention is not limited to the above-mentioned Examples, and it is understood that various changes can be made without departing from the gist thereof. Needless to say.

In the above embodiment, after a CCB bump is formed on the electrode of a semiconductor chip, the CCB bump is immediately quenched to segregate a eutectic solder layer (or a solder layer with a similar composition) on its surface. Although the semiconductor chip is face-down bonded to the package substrate using the diffusion of the solder layer, the invention is not limited to this, and a CCB pump without a eutectic solder layer on the surface can also be used. In this case as well, after removing the oxide film and foreign matter from the surface of the CCB bump in a surface activation chamber, the CCB bump is assembled by immediately performing temporary bonding and reflow in a bonding chamber with a high-purity inert gas atmosphere. Since face-down bonding can be performed at a temperature close to the melting point of the non-eutectic solder, it is possible to perform face-down bonding by reflowing the CCB bump in a glue flow furnace at a temperature considerably higher than the melting temperature of the non-eutectic solder. Compared to other techniques, thermal damage to semiconductor chips can be significantly reduced, and face-down bonding can be performed in a short time.

Furthermore, in order to make the bonding surface ultra-smooth, a metal softer than the metal to be bonded is preformed on the surface of at least one of the CCB bumps or electrodes, and the plastic deformation of this soft metal is utilized. It is also possible to achieve close contact. At that time, the joint may be heated to lower the yield point of the soft metal in order to lower the joining pressure. The above soft metals include:
For example, Sn can be used.

In the above embodiment, the case where the present invention is applied to a method of assembling a chip carrier (face-down bonding, hermetic sealing, bonding of CCB bumps) was explained, but it is also applicable to the process of mounting this chip carrier on a module board via CCB bumps. You can also.

The present invention can also be applied to a so-called multi-chip package tying method in which a plurality of semiconductor chips face-down bonded to the main surface of a package substrate are hermetically sealed with a cap.

Further, the present invention can be applied not only to flip chips but also to a method for manufacturing TAB as shown in FIG. 16.

That is, when gang-bonding the semiconductor chip 60 to the leads 62 formed on the main surface of the insulating film 61 via the bumps 63, first the A of the semiconductor chip 60 is
After a solder base layer made of a composite metal film of CrSCu and Au, for example, is deposited on the surface of the I electrode 64, solder bumps 63 are formed on the electrode using a solder vapor deposition method or a solder ball supply method. At this time, by immediately rapidly cooling the solder pan 63, a eutectic solder layer (or a solder layer with a similar composition) is segregated on its surface.

Then, this semiconductor chip 60 and the insulating film 61
was housed in a vacuum container such as the surface treatment chamber, and the surfaces of the solder bumps 63 and the leads 62 were irradiated with an Ar atomic beam to remove oxide films and foreign substances on the surfaces of the solder bumps 63 and the leads 62. After that, the semiconductor chip 60
Then, the insulating film 61 is immediately transferred to a container with a high-purity inert gas atmosphere, and gang bonding is performed by pressing the leads 62 onto the solder bumps 63 in this container.

According to this TAB manufacturing method, the bumps can be shaped using solder that is cheaper than Au, so the TAB
The manufacturing cost of AB can be reduced.

In the above explanation, the invention made by the present inventor was mainly applied to flip chips and TABs, which are the background application fields, but the present invention is not limited to this, and for example, LSI It can be widely applied as a metal bonding method for semiconductor components, electronic components, and optical components in ultrasonic probes, EDX entrance windows, laser diode packages, etc. When joining these parts, if there is no problem even if the joint surfaces of the metal members become charged (charge-up), an ion beam such as Ar ions can be used instead of surface activation by Ar atomic beam irradiation. Surface activation may be performed by irradiation.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

(1). When face-down bonding a semiconductor chip to a substrate via a CCB bump, the semiconductor chip and substrate are housed in a vacuum container, and after irradiating the surface of the CCB bump and the surface of the electrode of the substrate with an energy beam of atoms or ions, The semiconductor chip and the substrate were immediately transferred to a container with a high-purity inert gas atmosphere, and the CCB bumps were pressed against the electrodes to perform temporary bonding under normal pressure.
According to the method for manufacturing a semiconductor integrated circuit device of the present invention in which the CCB bumps are reflowed, the CC and B bumps can be reflowed at a temperature close to their melting temperature, so that thermal damage to the semiconductor chip can be reduced. can. Also,
It is possible to shorten the reflow time and downsize the reflow oven.

Further, according to the method for manufacturing a semiconductor integrated circuit device of the present invention, flux is not required when face-down bonding a semiconductor chip to a substrate via a CCB bump, so a flux application process and a flux cleaning process are not required. The face-down bonding process is reduced accordingly.

Moreover, wiring corrosion of the integrated circuit caused by flux residue can be avoided. Furthermore, since the occurrence of defects in solder joints due to flux residue can be avoided, the connection reliability of CCB bumps is improved.

(2). After constructing the CCB bump with non-eutectic solder, melting the non-eutectic solder, and immediately rapidly cooling it, a eutectic solder layer or a solder layer having a similar composition is segregated on the surface of the bump, and then According to the method for manufacturing a semiconductor integrated circuit device that performs face-down bonding by the same method as the invention (11) above, CCB bumps can be reflowed at a lower temperature than the invention (1) above, so that the semiconductor chip Thermal damage can be further reduced. Also, the reflow time can be shortened and the size of the reflow oven can be further promoted.

[3). When manufacturing a TAB in which a semiconductor chip is gang-bonded via bumps to leads formed on the main surface of an insulating film, the semiconductor chip and the insulating film are housed in a vacuum container, and atoms or After irradiation with the ion energy beam, the semiconductor chip and the insulating film are immediately transferred to a container with a high-purity inert gas atmosphere, and gang bonding is performed by pressing the leads to the bumps in this container. According to the method for manufacturing a semiconductor integrated circuit device, the bumps can be formed using a metal material that is cheaper than Au, so the manufacturing cost of the TAB can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a flow diagram showing the manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention, FIG. 2 is a schematic perspective view of the manufacturing equipment used in this embodiment, and FIGS. 3 and 4. FIG. 5(a) is a cross-sectional view of a semiconductor chip showing the CCB bump forming process in this embodiment.
5(C) is a partial front view showing the temporary joining mechanism of the manufacturing apparatus used in this example, and FIG. 6 is a partial perspective view showing the temporary joining mechanism of the manufacturing apparatus used in this example, 7 and 8 are cross-sectional views of the semiconductor chip and the package substrate showing the face-down bonding process in this example. FIG. 9 is a cross-sectional view of the cap showing the preliminary solder forming process in this example. 11 and 12 are cross-sectional views of the chip carrier showing the hermetic sealing process of this example, and FIG. The figure is a partial cross-sectional view of a glass protrusion jig showing the CCB bump shape forming process in this example, FIG. 14 is a cross-sectional view showing a chip carrier manufactured by this example, and FIG. 15 is a conventional chip 16 is a sectional view showing a main part of a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention. FIG. 1.50...Chip carrier, 2,9,53.58.
・CCB bump, 3.51 ・Package board, 4
, 52.64... Electrode, 5, 54.60... Semiconductor chip, 6.55... Cap, 7.56... Solder for sealing, 7a... Preliminary solder for sealing, 8 .57... Solder for heat transfer, 8a... Preliminary solder for heat transfer, 9a... Solder ball, 10.59... Internal wiring, 11... Solder metallized layer, 12... Manufacturing equipment , l3... base, 1
4a, 14b -- 0-door magazine, 15a... Chip tray, 15b... Board tray, 16, 19.31
...Loadlock chamber, 17...Surface activation chamber, 18
... Source gun, 20... Bonding chamber, 2l... Chip inversion stage, 22... Chip inversion unit, 23
...Chip loading hand, 24...Temporary bonding stage,
25... Prism mirror 26... Position recognition camera, 27... Melting bonding stage, 28... Heat block, 29... Chip transfer node, 30... Alignment stage, 32...・Push-up pin, 33...Collet, 34...Precision XY table, 35...High speed XY
Table, 36...Rotary table, 37...●Unload magazine, 40...Solder film, 41...Eutectic solder layer, 42...Hole, 43...Glass jig, 6l...・
- Insulating film, 62...Lead, 63...Solder handle.

Claims (1)

[Claims] 1. After irradiating the joint surface of a pair of metal members housed in a vacuum container with an energy beam of atoms or ions, the metal members are transferred to a container with a high-purity inert gas atmosphere and A metal joining method characterized by pressing the joining surfaces together under pressure. 2. The metal joining method according to claim 1, wherein the metal member is heated at a temperature below its melting temperature when the joining surfaces are pressed together. 3. At least one of the metal members is made of a non-eutectic alloy,
Claim 1, wherein the non-eutectic alloy is melted in advance and then rapidly cooled to segregate a eutectic alloy layer or an alloy layer having a composition close to it on its surface.
Or the metal joining method described in 2. 4. TAB, which gang-bonds the semiconductor chip to the leads formed on the main surface of the insulating film via bumps.
4. A method for manufacturing a semiconductor integrated circuit device, wherein the gang bonding is performed using the metal bonding method according to claim 1, 2, or 3. 5. When manufacturing a flip chip in which a semiconductor chip is face-down bonded to a substrate via a CCB bump, after temporarily bonding the CCB bump to an electrode of the substrate using the metal bonding method according to claim 1, 2 or 3, Said CC
A method for manufacturing a semiconductor integrated circuit device, comprising reflowing B bumps. 6. In the semiconductor integrated circuit device, the semiconductor chip is hermetically sealed by soldering a cap to the main surface of the package substrate on which the semiconductor chip is face-down bonded via CCB bumps, and the back surface of the semiconductor chip is hermetically sealed. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein the chip carrier has a package structure formed by soldering to the bottom surface of a cap. 7. When the semiconductor chip is hermetically sealed and the back surface of the semiconductor chip is soldered to the bottom surface of the cap, preliminary solder for sealing is applied to the main surface of the package substrate or the legs of the cap in advance. At the same time, preliminary solder for heat transfer is applied to the back surface of the semiconductor chip or the lower surface of the cap, and the cap is temporarily bonded to the main surface of the package substrate using the metal bonding method according to claim 1, 2, or 3. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the preliminary solder for sealing and the preliminary solder for heat transfer are then reflowed. 8. When mounting the chip carrier on the main surface of the module substrate via the CCB bump, bonding the CCB bump to the electrode on the lower surface of the package substrate using the metal bonding method according to claim 1, 2 or 3. The method of manufacturing a semiconductor integrated circuit device according to claim 6 or 7, characterized in that: 9. A vacuum surface activation chamber equipped with a source gun that generates an atomic or ion energy beam, and a normal pressure bonding chamber equipped with a temporary bonding mechanism and a fusion bonding mechanism and with a high-purity inert gas atmosphere. 9. A manufacturing apparatus for use in a method of manufacturing a semiconductor integrated circuit device according to claim 5, 6, 7, or 8, wherein the semiconductor integrated circuit devices are connected to each other via a load lock chamber.