JP2007059703A - Semiconductor chip and semiconductor package packaging same in circuit board, and their method of manufacturing semiconductor chip and semiconductor package packaging same in circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To satisfactorily fill a sealing resin between bumps of a semiconductor chip during pressure-contacting electrodes of a circuit board through a sealing resin to electrically contact the electrodes in a sealed condition, even though the bumpe are arranged in narrow pitch, which enhances a reliablity of an electrical insulation to prolong the life. <P>SOLUTION: The semiconductor chip includes: an insulating protective film 2 formed on an arrangement surface 1a of the electrode 3; and the bump 4 exposing from the film 2 on the electrode 3 to the outside and used for electrically connecting to the electrode 6 of the circuit board 7 through the sealing resin 5. The thickness of the film 2 in a narrow part 11 sandwiched by the bump 4 on the electrode 3 is made thicker than that of the film 2 at the part other than it. The bump 4 is press-contacted and electrically connected to the electrode 6 of the board 7 through the liquid or sheet-like sealing resin 5, and the surrounding of the electrical connection part is sealed by the solidification and the curing of the resin 5. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  In the present invention, an insulating protective film is formed on the arrangement surface of the electrodes, and is electrically exposed to the outside of the insulating protective film on the arranged electrodes through a sealing resin with the electrode of the circuit board. The present invention relates to a semiconductor chip having a bump to be provided, a semiconductor package in which the semiconductor chip is mounted on a circuit board, and a manufacturing method thereof.

  As semiconductor chips are mainly used in flip chip mounting in which electrical connection with a circuit board is achieved by bumps on electrodes typified by Au bumps in response to the recent increase in signal speed, semiconductor chips are becoming even finer. Narrow pitches of bumps have been remarkably advanced due to further increase in the number of devices, the number of signals, the number of electrodes, and the number of bumps. FIG. 3 shows an example in which bumps b are formed on the electrodes g arranged at a narrow pitch along two sides of the semiconductor chip a. For further increase in the number of bumps, each side of the semiconductor chip a is shown. In other words, the bumps b are arranged in the form of a peripheral along the four sides, and the bumps b are arranged in two or more rows as shown in FIG. 4, which also has a small dead space as shown in FIG. They are also arranged in a staggered pattern.

  On the other hand, such a narrow pitch of the bumps b is obtained by placing the sealing resin c in a liquid or sheet form in advance on the circuit board d as shown in FIG. In order to electrically connect and seal between the sealing resin c, the sealing resin c is not completely filled between adjacent bumps b arranged in a narrow pitch due to the influence of surface tension, and is shown in FIG. Such a gap f remains. Such a gap f causes a decrease in the temperature reflow property of the semiconductor package and the reliability of bonding with respect to external force, and the electrical insulation between the electrodes g and the bumps b.

As a method of reducing the generation of such voids f, although not shown, the central portion of the sealing resin sheet is made thicker than the peripheral portion, and the semiconductor chip is pressed against the circuit board to electrically Bumps that are arranged around the semiconductor chip while expanding the pressure area from the thick central part to the periphery between the semiconductor chip and the circuit board when connecting to and mounting in a sealed state A technique is known that allows filling with a small amount of residual gap by extruding in between (see, for example, Patent Document 1).
JP-A-9-129659

  However, if a sealing resin sheet having a thicker central part than the peripheral part is used as in the prior art, the sealing resin sheet must be remade according to the semiconductor chip size and bump arrangement being different. There is a problem that it takes time to produce the resin-stopping sheet, resulting in a delay in delivery and an increase in cost.

  An object of the present invention is to electrically connect bumps of a semiconductor chip to electrodes of a circuit board via a sealing resin and mount them in a sealed state. Even if the bumps are arranged in a narrow pitch, the sealing resin is between the bumps. An object of the present invention is to provide a semiconductor chip capable of filling various semiconductor devices with high reliability, electrical insulation reliability and long life, a semiconductor device having the semiconductor chip mounted on a circuit board, and a manufacturing method thereof.

  In order to achieve the above object, the semiconductor chip of the present invention has an insulating protective film formed on the arrangement surface of the electrodes, and is exposed to the outside from the insulating protective film on the arranged electrodes. The semiconductor chip having bumps used for electrical connection via the sealing resin of the insulating film, wherein the insulating protective film is mainly thicker in the portion sandwiched between the bumps It is a feature.

  In such a configuration, the semiconductor chip has an insulating protective film formed on the electrode array surface, leaving the electrodes, and bumps formed on the electrodes and exposed to the outside from the insulating protective film are used as the electrodes of the circuit board. When subjected to electrical connection via the sealing resin, the sealing resin is pressed between the protective film of the semiconductor chip and the circuit board and pushed away from the electrically connected region between the bump and the electrode. While being filled between the semiconductor chip and the circuit board, the protective film is thicker than the other parts in the narrow area between the bumps, and the space ratio to be filled with the sealing resin is reduced, It is possible to increase the filling rate and filling speed of the sealing resin, and to prevent residual voids from being generated therein. In addition, the insulating protective film can be formed without any trouble with necessary partial steps in addition to the openings corresponding to the electrodes at the time of molding.

  That is, in such a semiconductor chip, in order to form an insulating protective film on the electrode array surface of each semiconductor chip corresponding part in the semiconductor wafer, the part between the electrodes on which the bump is formed is laminated thicker than the other part. Alternatively, the insulating protective film is formed so as to be thicker than the other portions by forming the same thickness once and then reducing the thickness except for the portion between the electrodes where the bumps are formed. A manufacturing method characterized by forming bumps on the electrodes through the steps can be manufactured without any special steps or labor.

  In the semiconductor chip of the present invention as described above, an insulating protective film is formed on the arrangement surface of the electrode between the circuit board and the circuit is exposed to the outside from the insulating protective film on the arranged electrode. A semiconductor chip having a bump provided for electrical connection with an electrode of a substrate, and a portion sandwiched between the bumps of the insulating protective film formed thicker than the other portion; A circuit board in which the bump and its own electrode are electrically connected, and a sealing resin that seals the semiconductor chip and the circuit board in the electrically connected state with solidification or curing between the semiconductor chip and the circuit board. The semiconductor device characterized by the above can be provided, and the characteristic sealing function with the circuit board can be exhibited.

  In such a semiconductor package, an insulating protective film is formed on the arrangement surface of the electrodes, and is exposed to the outside from the insulating protective film on the arranged electrodes and used for electrical connection with the electrodes of the circuit board. In the semiconductor chip having bumps, the portion of the insulating protective film sandwiched between the bumps is formed thicker than the other portions, and the bumps of the semiconductor chip and the electrodes of the circuit board are arranged on the side of the semiconductor chip. Alternatively, a liquid or sheet-shaped sealing resin previously provided on the circuit board side, or a sheet-shaped sealing resin sandwiched between the semiconductor chip and the circuit board, is electrically connected by being pressed, and the sealing resin Thus, the semiconductor chip and the circuit board can be easily manufactured by a manufacturing method mainly characterized by sealing the semiconductor chip and the circuit board in an electrically connected state.

  Further features and actions of the present invention will become apparent from the detailed description and drawings that follow. Each feature of the present invention can be used alone or in combination in various combinations as much as possible.

  According to the present invention, the insulating protective film of the semiconductor chip is only thicker in the narrow area between the bumps than in the other areas, and the space ratio to be filled with the sealing resin in the narrow area is reduced to reduce the narrow area. Increases the filling rate and filling speed of the sealing resin to the part and prevents the formation of residual voids in the part, thus improving the heat absorption reflow characteristics of the semiconductor package and the reliability of the bondability to external force, resulting in a longer life Reduce costs.

  Hereinafter, a semiconductor chip according to an embodiment of the present invention, a semiconductor device in which the semiconductor chip is mounted on a circuit board, and a manufacturing method thereof will be described in detail with reference to the drawings to provide an understanding of the present invention. The following embodiments are specific examples of the present invention and do not limit the technical scope of the present invention.

  As shown in FIG. 1, the semiconductor chip of the present embodiment has an insulating protective film 2 formed on the electrode array surface 1 a on which the electrode 3 of the semiconductor chip 1 is formed, and is electrically connected to the electrode 3. The bump 4 is exposed to the outside. At the same time, openings 8 are formed in the insulating protective film 2 from the surface to the electrodes 3, and the bumps 4 connected to the electrodes 3 are formed in the openings 8, and are exposed outside the surface of the insulating protective film 2. I am doing so. As described above, in the present embodiment, the conventional insulating protective film 2 is formed on the electrode array surface 1 a of the semiconductor chip 1, and the openings 8 are provided on the electrodes 3 of the insulating protective film 2. The bumps 4 connected to the electrodes 3 are formed by using the bumps 4, and these bumps 4 are brought into contact with or pressed against the electrodes 6 of the circuit board 7, whereby the semiconductor chip 1 and the electrodes 6 of the circuit board 7 are Are electrically connected via the sealing resin 5, and the semiconductor resin 12 can be flip-chip mounted on the circuit board 7 with the solidification or curing of the sealing resin 5.

  Here, silicon nitride is generally employed for the insulating protective film 2 and is often added by a film forming method such as a CVD method at the final stage of the semiconductor diffusion process. Therefore, a pattern is formed at a time at the stage of the semiconductor wafer on which ICs for a large number of semiconductor chips are formed, and openings 8 having a predetermined arrangement, a predetermined shape, and a predetermined dimension corresponding to the electrodes 3 are simultaneously formed. Specifically, it is formed in a pattern excluding the electrode 3 portion using a single dedicated mask, and the film thickness becomes uniform in the plane. In addition, polyimide resin material can be used in place of silicon nitride. In this case, it is applied to a uniform thickness by spin coating or roll coating method, etc., or after printing and drying and solidifying, The opening 8 can be patterned, but in the case of coating, the opening 8 is formed by pattern exposure using a mask of a photolithography technique, removal of the pattern by development, and pattern thinning, in particular, using polyimide resin as a photosensitivity. The For example, the size is about several tens to 100 μm. However, it is not limited to this.

  On the other hand, the bumps 4 on the electrodes 3 are formed through the openings 8 of the insulating protective film 2, but are generally formed in a form corresponding to the type of the sealing resin 5 when the semiconductor chip 1 is mounted on the circuit board 7. . For example, when the sealing resin 5 is a film and NCF, it is formed at a predetermined height as a stud bump by wire bonding using Au wire or the like, and the shape thereof is generally a base portion bonded to the electrode 3 and this It is formed with a protruding portion that is slightly thin and protrudes in various forms from the base portion, and has a step portion between the base portion and the protruding portion as shown in one example in FIG. When the sealing resin 5 is ACF, it is formed to a predetermined thickness by plating with Au or the like. Further, when the sealing resin 5 is used in a liquid form, both stud bumps and plating bumps are used, and Au is used as the material thereof.

  By the way, with the recent miniaturization and higher functionality of the semiconductor chip 1, as described above, the number of bumps 4 formed on the semiconductor chip 1 per unit area continues to increase. Also, a multi-row arrangement such as two to four rows as shown in FIG. 1 is adopted to arrange in a rectangular area along the periphery of the periphery, and the bumps 4 in such a multi-row arrangement are staggered as illustrated in FIG. Since the arrangement density of the bumps 4 is increasing rapidly, the bumps 4 of the semiconductor chip 1 are electrically connected to the electrodes 6 of the circuit board 7 via the sealing resin 5, When the encapsulating resin 5 is mounted with solidification and curing, the encapsulating resin 5 is not filled between the narrow bumps 4 and is not completely cut out, and a residual space as illustrated in FIG. 2 is generated. This is because the sealing resin 5 is placed between the semiconductor chip 1 and the circuit board 7 in a liquid state due to thermoplasticity, thermosetting incompleteness, etc., regardless of whether the sealing resin 5 is preceded by the semiconductor chip 1 or the circuit board 7 or sandwiched between both. For the purpose of filling, the semiconductor chip 1 and the bumps 4 and the electrodes 6 of the circuit board 7 are simply brought close to each other and brought into pressure contact with each other so that the sealing resin 5 can be formed. This is due to the fact that the narrow region 11 between the bumps 4 arranged at a narrow pitch is not sufficiently filled by the action of a relatively high surface tension commensurate with the viscosity.

  The residual space created in this way causes poor insulation between the electrodes 3 when moisture or moisture enters, and causes an electrical open due to popcorn phenomenon during reflow and concentration of lift when physical external force is applied. Since it also causes defects, that is, electrical connection and bonding defects, the reliability of the semiconductor package 12 is remarkably lowered and the life is shortened.

  In order to cope with this, in the present embodiment, in particular, the portion 2a of the insulating protective film 2 in the narrow portion 11 sandwiched between the bumps 4 on the electrodes 3 arranged as shown in FIG. It is thicker than 2b. The semiconductor chip 1 has an electrode array surface 1a formed with an insulating protective film 2 leaving the electrode 3, and a bump 4 formed on the electrode 3 and exposed to the outside from the insulating protective film 2 is provided on the circuit board 7. When the electrode 6 is electrically connected to the electrode 6 via the sealing resin 5, the sealing resin is pressed between the insulating protective film 2 of the semiconductor chip 1 and the circuit board 7, and the bump 4 and the electrode 6 are pressed. The space ratio that should be filled with the sealing resin 5 in the narrow area portion 11 that is filled between the semiconductor chip 1 and the circuit board 7 while being pushed away from the electrically connected area is reduced. The filling rate and filling speed of the sealing resin 5 to the narrow area 11 can be increased, and a conventional residual gap can be prevented from being formed in the narrow area 11 between the bumps 4. In addition, the insulating protective film 2 can be formed easily without any necessary partial steps in addition to the openings 8 corresponding to the electrodes 3 at the time of molding. For that purpose, the thickness of the portion 2a of the narrow area 11 of the insulating protective film 2 should be equal to or higher than the height of the stepped portion of the bump 4, and if it is too thick, the bump 4 pushes the sealing resin 5 away to the electrode 6. It may interfere with the electrical connection. Specifically, bubbles may get caught between the bumps 4 and the electrodes 6 and disturb the electrical connection between the two. Therefore, it is preferable to suppress the thickness of the portion 2a of the narrow portion 11 in the insulating protective film 2 to such an extent that the flow of the sealing resin 5 at the time of electrical connection between the bump 4 and the electrode 6 is not hindered. It is.

  In other words, in order to form the insulating protective film 2 on the electrode array surface of the part corresponding to each semiconductor chip 1 in the semiconductor wafer, the part between the electrodes 3 where the bumps 4 are to be formed is laminated thicker than the other part. The insulating protective film is formed so that the portion 2a sandwiched between the electrodes 3 is thicker than the other portions 2b by forming the same thickness once and then reducing the thickness at portions other than the portion between the electrodes 3 where the bumps 4 are formed. This can be easily realized by forming the bumps 4 on the electrodes 3 through the process of forming 2.

  More specifically, in order to pattern the insulating protective film 2 by sputtering using silicon nitride as a material, an in-plane uniform using an exclusive mask excluding the electrode 3 portion on the electrode array surface 1a of the semiconductor chip 1 is used. After forming the layer, by forming an in-plane uniform layer using a dedicated mask excluding the portion sandwiched between the electrodes 3, the portion 2 a sandwiched by the bump 4 later becomes thicker than the other portion 2 b. The film 2 can be formed.

  In place of the above, the silicon nitride layer formed by sputtering with a uniform in-plane thickness required for the portion 2a is left with the portion 2a, the portion of the electrode 3 is eliminated, and the other portion 2b is replaced. Etching may be performed to reduce the thickness to a predetermined thickness.

  In addition, depending on the type of the semiconductor chip 1, a silicon nitride layer is formed and then a polyimide resin is applied or printed, so that a predetermined portion corresponding to the portion 2 b or the electrode 3 by the holographic technique described above is determined. In the case of printing by removing the pattern to the thickness or reducing the thickness, a pattern layer having an opening corresponding part corresponding to the electrode 3 is separately formed, and then the opening corresponding part corresponding to the electrode 3 and the electrode 3 or bump. A predetermined insulating protective film 2 can also be provided by forming a pattern layer having a thickened portion corresponding to the portion 2 a sandwiched between 4.

  In any case, the insulating protective film 2 of the semiconductor chip 1 is only thicker at the portion 2a of the narrow area 11 between the bumps 4 than at the other portion 2b, and the sealing resin 5 of the narrow area 11 is filled. The power space ratio is reduced to increase the filling rate and filling speed of the sealing resin 5 into the narrow area 11 and prevent the formation of residual voids therein. Reliability is improved, the service life is longer, and the cost is reduced.

  Here, in the semiconductor chip 1 as described above, the insulating protective film 2 is formed on the arrangement surface 1a of the electrode 3 between the circuit board 7 and the insulating protective film 2 is formed on the arranged electrode 3 from the outside. The bumps 4 exposed to the electrodes 6 for electrical connection with the electrodes 6 of the circuit board 7 are formed, and the portion 2a sandwiched between the bumps 4 of the insulating protective film 2 is formed thicker than the other portions 2b. The semiconductor chip 1, the circuit board 7 in which the bumps 4 of the semiconductor chip 1 and its own electrodes 6 are electrically connected, and the semiconductor chip 1 and the circuit board 7 are solidified or hardened together with the above. A semiconductor device 12 as shown in FIG. 1 provided with a sealing resin 5 for sealing in an electrically connected state can be provided, and the characteristic sealing function with the circuit board 7 can be exhibited. Can do.

  In such a semiconductor package 12, the insulating protective film 2 is formed on the array surface 1 a of the electrode 3, and is exposed to the outside from the insulating protective film 2 on the arrayed electrode 3. In the semiconductor chip 1 having the bumps 4 used for electrical connection, a portion 2a sandwiched between the bumps 4 of the insulating protective film 2 is formed thicker than the other portions 2b. 1 or 4 between the semiconductor chip 1 and the circuit board 7, or between the semiconductor chip 1 and the circuit board 7. Manufacturing method in which the semiconductor chip 1 and the circuit board 7 are sealed in an electrically connected state with solidification or curing of the sealing resin 5 by being pressed and electrically connected via a sheet-shaped sealing resin 5 sandwiched between the two. Easy by It can be produced.

  INDUSTRIAL APPLICABILITY The present invention is practically applied to a technique for mounting a semiconductor chip on a circuit board with a bump through a sealing resin, and can improve insulation and bondability in a semiconductor package with a sealing resin at a recent narrow pitch.

It is sectional drawing which shows one example of the semiconductor chip which concerns on embodiment of this invention, and the semiconductor device which mounted it on the circuit board. It is sectional drawing which shows one example of the conventional semiconductor element and the semiconductor device which mounted it on the circuit board. It is a perspective view which shows one example of the conventional semiconductor chip by which the pitch was narrowed. It is a perspective view which shows one example of the conventional semiconductor chip by which narrow pitch and multi-row arrangement | positioning were carried out.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Insulation protective film 3, 6 Electrode 4 Bump 5 Sealing resin 7 Circuit board 8 Opening 11 Narrow area 12 Semiconductor device

Claims (4)

An insulating protective film is formed on the arrangement surface of the electrode, and the bump exposed to the outside from the insulating protective film on the arranged electrode and used for electrical connection with the electrode of the circuit board via the sealing resin A semiconductor chip having
The semiconductor chip according to claim 1, wherein the insulating protective film is thicker at a portion sandwiched between the bumps than other portions. An insulating protective film is formed on the arrangement surface of the electrode, and the bump exposed to the outside from the insulating protective film on the arranged electrode and used for electrical connection with the electrode of the circuit board via the sealing resin In a method for manufacturing a semiconductor chip having
In order to form an insulating protective film on the electrode array surface of each semiconductor chip corresponding part on the semiconductor wafer, the part between the electrodes on which the bumps are formed is laminated thicker than the other part or once formed to an equal thickness. Then, the thickness of the bumps is reduced at a portion other than the portion between the electrodes, or the portion sandwiched between the electrodes is subjected to a process of forming an insulating protective film thicker than the other portions, A method of manufacturing a semiconductor chip, comprising forming a bump. An insulating protective film is formed on the arrangement surface of the electrodes, and has bumps exposed to the outside from the insulating protective film and used for electrical connection with the electrodes of the circuit board on the arranged electrodes. A semiconductor chip in which a portion sandwiched between the bumps of the protective film is made thicker than other portions, a circuit board in which the bumps of the semiconductor chip and its own electrodes are electrically connected, the semiconductor chip and the circuit A semiconductor package comprising: a sealing resin that seals them in the electrically connected state with solidification or curing with a substrate. In a semiconductor chip having an insulating protective film formed on an array surface of electrodes, and having bumps exposed to the outside from the insulating protective film on the arrayed electrodes and used for electrical connection with electrodes of a circuit board The portion of the insulating protective film sandwiched between the bumps is formed thicker than the other portions, and the bumps of the semiconductor chip and the electrodes of the circuit board are attached in advance to the semiconductor chip side or the circuit board side. A liquid or sheet-shaped sealing resin, or a sheet-shaped sealing resin sandwiched between a semiconductor chip and a circuit board, is electrically connected by pressure contact, and the semiconductor is accompanied by solidification or curing of the sealing resin. A method of manufacturing a semiconductor package, wherein a chip and a circuit board are sealed in an electrically connected state.

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