JP2002026070A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JP2002026070A JP2002026070A JP2000202484A JP2000202484A JP2002026070A JP 2002026070 A JP2002026070 A JP 2002026070A JP 2000202484 A JP2000202484 A JP 2000202484A JP 2000202484 A JP2000202484 A JP 2000202484A JP 2002026070 A JP2002026070 A JP 2002026070A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- electrodes
- solder
- chip
- bare chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、配線基板にベアチ
ップＩＣを実装した半導体装置およびその製造方法に関
する。The present invention relates to a semiconductor device having a bare chip IC mounted on a wiring board and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】シリコンのベアチップＩＣを配線基板に
直接に実装する、ベアチップ実装技術は携帯電話やパソ
コン等の製造工程での適用を中心に進展を見せている。
特に、ベアチップＩＣの接続用電極を配線基板に対向し
て、フェイスダウンボンディングするフリップチップ実
装技術が、最も高密度実装に優れているために実用化が
進んでいる。2. Description of the Related Art Bare chip mounting technology, in which a silicon bare chip IC is directly mounted on a wiring board, has been progressing mainly in application to manufacturing processes of mobile phones and personal computers.
In particular, flip-chip mounting technology in which a connection electrode of a bare chip IC faces the wiring substrate and face-down bonding is performed has been put to practical use because it is excellent in the highest density mounting.
【０００３】これらのフリップチップ実装の第１の例を
以下に説明する。A first example of the flip chip mounting will be described below.
【０００４】図９（ａ）から（ｆ）はフリップチップ実
装の各工程ごとの模式説明図であり、図１０は、そのう
ちの加熱工程での温度プロファイルと封止樹脂（封止樹
脂）の硬化反応率との関係を示すグラフである。FIGS. 9 (a) to 9 (f) are schematic diagrams for each step of flip-chip mounting, and FIG. 10 is a diagram showing a temperature profile in the heating step and curing of the sealing resin (sealing resin). It is a graph which shows the relationship with a reaction rate.
【０００５】まず、ガラスエポキシ板等の配線基材の表
面に銅パターン等の電極５２ａ、５２ｂ、５２ｃ…５２
ｎにはんだ処理した配線基板５１と、接続電極５４ａ、
５４ ｂ、５４ｃ…５４ｎの形成されたベアチップＩＣ５
４とを準備する（ａ）。次に、配線基板５１にフラック
ス５９を塗布して、はんだ付け性を向上させるための表
面処理を行う。また、ベアチップＩＣ５４の接続電極５
４ａ、５４ｂ、５４ｃ…５４ｎには、錫と鉛系の共晶は
んだ等で、接続用のバンプ５３ａ、５３ｂを形成する
（ｂ）。続いて、配線基板５１の電極５２ａ、５２ｂ、
５２ｃ…５２ｎとベアチップＩＣ５４の接続電極５
４ａ、５４ｂ、５４ｃ…５４ｎに形成されたバンプ５３
ａ、５３ｂを位置合わせして、ボンディングツール６４
で加熱加圧して配線基板５１にベアチップＩＣ５４を実
装する（ｃ）。First, a table of a wiring base material such as a glass epoxy plate is shown.
Electrodes 52 such as copper pattern on the surfacea, 52b, 52c... 52
nWiring board 51 soldered toa,
54 b, 54c… 54nChip IC5 formed with
4 is prepared (a). Next, a flux is attached to the wiring board 51.
Table for improving solderability by applying solder 59
Perform surface treatment. Also, the connection electrode 5 of the bare chip IC 54
4a, 54b, 54c… 54nThe tin-lead eutectic is
The connection bumps 53a, 53bForm
(B). Subsequently, the electrode 52 of the wiring board 51a, 52b,
52c... 52nAnd connection electrode 5 of bare chip IC 54
4a, 54b, 54c… 54nBump 53 formed on
a, 53bAlign the bonding tool 64
Heating and pressurizing to form bare chip IC 54 on wiring board 51
(C).
【０００６】続いて、ベアチップＩＣ５４が実装された
配線基板５１をリフロー炉（不図示）等を用いて加熱処
理を行なう。図１０で、加熱温度Ｔ１によって示すよう
に、その際の加熱のピーク温度Ｔ１は２４０℃程度であ
る。この温度ではんだを溶融し、配線基板５１とベアチ
ップＩＣ５４を電気的に接続する。その後に、ベアチッ
プＩＣ５４の接続面側に残存しているフラックス５９を
溶剤等で除去する（ｄ）。Subsequently, the wiring board 51 on which the bare chip IC 54 is mounted is subjected to a heat treatment using a reflow furnace (not shown) or the like. As shown by the heating temperature T1 in FIG. 10, the peak temperature T1 of the heating at that time is about 240 ° C. The solder is melted at this temperature, and the wiring board 51 and the bare chip IC 54 are electrically connected. Thereafter, the flux 59 remaining on the connection surface side of the bare chip IC 54 is removed with a solvent or the like (d).
【０００７】続いて、ベアチップＩＣ５４と配線基板５
１の接続強度の向上のために、べアチップＩＣ５４の接
続面と配線基板５１との間と、側面に封止ようの封止樹
脂５５を充填する。この封止樹脂５５の充填は、ディス
ぺンサ６３を用いて行い、ベアチップＩＣ５４の端面に
封止樹脂５５を塗布して、毛細管現象によりべアチップ
ＩＣ５４の接続面と配線基板５１の間に樹脂充填を行な
う（ｅ）。Subsequently, the bare chip IC 54 and the wiring board 5
In order to improve the connection strength of No. 1, a sealing resin 55 for sealing is filled between the connection surface of the bare chip IC 54 and the wiring board 51 and the side surface. The filling of the sealing resin 55 is performed by using the disperser 63, the sealing resin 55 is applied to the end surface of the bare chip IC 54, and the resin is filled between the connection surface of the bare chip IC 54 and the wiring board 51 by a capillary phenomenon. (E).
【０００８】その後、ベアチップＩＣ５４が実装された
配線基板５１をオーブン（不図示）内に収納してオーブ
ン加熱工程を施す。その際の、オーブン内の加熱条件
は、例えば、図１０で示した加熱温度Ｔ２を１５０℃で
１時間行い、封止樹脂５５を硬化させる（ｆ）。これら
の各工程により、半導体装置を製造している。After that, the wiring board 51 on which the bare chip IC 54 is mounted is housed in an oven (not shown), and an oven heating step is performed. The heating condition in the oven at this time is, for example, heating temperature T2 shown in FIG. 10 at 150 ° C. for 1 hour to cure the sealing resin 55 (f). Through these steps, a semiconductor device is manufactured.
【０００９】これらの工程で行なわれている加熱工程の
加熱条件は、図１０に温度プロファイルと封止樹脂の硬
化反応率を示すように、まず、はんだ共晶温度以上の設
定温度（Ｔ１；２４０℃）での加熱を行ない、それによ
り、はんだ溶融によるバンプ接合プロセスを実施する。The heating conditions in the heating step performed in these steps are as follows. First, as shown in FIG. 10, the temperature profile and the curing reaction rate of the sealing resin are set at a temperature equal to or higher than the solder eutectic temperature (T1; 240). C.), thereby performing a bump bonding process by solder melting.
【００１０】このリフロー工程により、はんだ接続を行
った後に、封止樹脂を塗布し、はんだの融点温度未満の
設定温度による加熱硬化工程（加熱温度Ｔ２）による封
止樹脂の加熱硬化を行う。その結果、加熱硬化終了時
に、封止樹脂の硬化反応率は１００％となる。この場
合、相互の温度の間では、Ｔ１（２４０℃）＞Ｔ２（１
５０℃）であるので、封止樹脂の樹脂封止の際に、はん
だ接合したはんだが溶融することはない。なお、これら
のリフロー工程と加熱硬化工程とは、別々の製造装置を
用いて行なわれている。In this reflow step, after the solder connection is made, a sealing resin is applied, and the sealing resin is heated and cured in a heating and curing step (heating temperature T2) at a set temperature lower than the melting point of the solder. As a result, at the end of the heat curing, the curing reaction rate of the sealing resin becomes 100%. In this case, between the mutual temperatures, T1 (240 ° C.)> T2 (1
(50 ° C.), so that the solder joined with the solder does not melt during the sealing of the sealing resin. Note that the reflow step and the heat curing step are performed using different manufacturing apparatuses.
【００１１】また、フリップチップの実装では、はんだ
と封止樹脂とを一括して加熱することによって接合する
方式も用いられている。In flip chip mounting, a method is also used in which the solder and the sealing resin are joined together by heating them together.
【００１２】この一括加熱方式について、第２の例とし
て以下に説明する。図１１はフリップチップ実装の各工
程ごとの模式説明図であり、図１２はそれに対応した温
度プロファイルと封止樹脂の硬化反応率との関係を示す
グラフである。This batch heating method will be described below as a second example. FIG. 11 is a schematic explanatory view of each step of flip chip mounting, and FIG. 12 is a graph showing a relationship between a corresponding temperature profile and a curing reaction rate of the sealing resin.
【００１３】まず、ガラスエポキシ基板等の配線基材の
表面に銅パターン等の電極７２ａ、７２ｂ、７２ｃ…７
２ｎにはんだ処理した配線基板７１を準備する（ａ）。
次に、配線基板７１の表面の所定個所に封止樹脂７５を
ディスペンサ７９で塗布する。また、ベアチップＩＣ７
４の接続電極７４ａ、７４ｂ、７４ｃ…７４ｎに上述の
場合と同様に、錫と鉛系の共晶はんだ等で接続用のバン
プ７３ａ、７３ｂを形成する（ｂ）。続いて、配線基板
７１の電極７２ａ、７２ｂ、７２ｃ…７２ｎとベアチッ
プＩＣ７４の接続電極７４ａ、７４ｂ、７４ｃ…７４ｎ
に形成されたバンプ７３ａ、７３ｂとを位置合わせし、
ボンディングツール８４で加熱・加圧して、配線基板７
１にベアチップＩＣ７４を実装する（ｃ）。First, electrodes 72 a , 72 b , 72 c ... 7 of a copper pattern or the like are formed on the surface of a wiring base material such as a glass epoxy substrate.
A 2n soldered wiring board 71 is prepared (a).
Next, a sealing resin 75 is applied to a predetermined location on the surface of the wiring board 71 with a dispenser 79. In addition, bare chip IC7
Fourth connection electrode 74 a, 74 b, the 74 c ... 74 n as in the above, to form a bump 73 a, 73 b for connection eutectic solder of tin and lead-based (b). Subsequently, the electrode 72 a of the wiring board 71, 72 b, 72 c ... 72 n connected electrodes 74 of the bare chip IC74 a, 74 b, 74 c ... 74 n
Aligning the bump 73 a, 73 b formed,
The wiring board 7 is heated and pressed by the bonding tool 84.
1 is mounted with a bare chip IC 74 (c).
【００１４】その後、ベアチップＩＣ７４が実装された
配線基板７１をリフロー炉で熱処理を施す。その際の熱
処理の加熱条件は、図１２で示すように、ピーク温度Ｔ
１は２４０℃程度ではんだを溶融し、配線基板７１とベ
アチップＩＣ７４を電気的に接続する。この加熱によ
り、封止樹脂７５ははんだ溶融と同時に加熱されて硬化
する（ｄ）。Thereafter, the wiring board 71 on which the bare chip IC 74 is mounted is subjected to a heat treatment in a reflow furnace. The heating conditions for the heat treatment at this time are as shown in FIG.
1 melts the solder at about 240 ° C. and electrically connects the wiring board 71 and the bare chip IC 74. Due to this heating, the sealing resin 75 is heated and cured simultaneously with the melting of the solder (d).
【００１５】従って、この場合は上述の場合のように、
フラックスの塗布とフラックスの除去工程が不要であ
る。また、毛細管現象によりベアチップＩＣ７４の接続
面と配線基板７１との間に封止樹脂を注入して充填する
工程が不要である。Therefore, in this case, as in the above case,
No flux application and flux removal steps are required. Further, a step of injecting and filling the sealing resin between the connection surface of the bare chip IC 74 and the wiring board 71 due to the capillary phenomenon is unnecessary.
【００１６】その後、ベアチップＩＣ７４が実装された
配線基板７１をオーブン（不図示）内に収納してオーブ
ン加熱工程を施す。その際の、オーブン内の加熱条件
は、例えば、図１２で示した加熱温度Ｔ２を１５０℃で
１時間行い封止樹脂を硬化させる（ｅ）。これらの各工
程により、半導体装置を製造している。Thereafter, the wiring board 71 on which the bare chip IC 74 is mounted is housed in an oven (not shown) and an oven heating step is performed. The heating condition in the oven at this time is, for example, heating temperature T2 shown in FIG. 12 at 150 ° C. for 1 hour to cure the sealing resin (e). Through these steps, a semiconductor device is manufactured.
【００１７】その結果、加熱硬化終了時に、封止樹脂の
硬化反応率は１００％となる。なお、これらのリフロー
工程と加熱硬化工程は、別々の製造装置を用いて行なわ
れている。As a result, at the end of the heat curing, the curing reaction rate of the sealing resin becomes 100%. Note that the reflow step and the heat curing step are performed using different manufacturing apparatuses.
【００１８】これらの加熱工程での加熱条件は、図１２
に温度プロファイルと封止樹脂の硬化反応率を示すよう
に、まず、はんだ共晶温度以上の設定温度（Ｔ１）を行
ない、それにより、はんだ溶融によるバンプ接合プロセ
スを実施する。The heating conditions in these heating steps are shown in FIG.
First, a set temperature (T1) equal to or higher than the solder eutectic temperature is performed so as to show the temperature profile and the curing reaction rate of the sealing resin, thereby performing a bump joining process by solder melting.
【００１９】このリフロー工程により、はんだ接続を行
った後に、封止用の封止樹脂を塗布し、加熱硬化工程
（加熱温度Ｔ２）による封止樹脂の加熱硬化を行う。After the solder connection is performed in this reflow step, a sealing resin for sealing is applied, and the sealing resin is heated and cured in a heating and curing step (heating temperature T2).
【００２０】[0020]
【発明が解決しようとする課題】しかしながら、上述の
実装技術の第１の例では、フラックス塗布工程と、はん
だ接続後のフラックス除去工程が煩雑で好ましくない。
また、フリップチップ接続後の封止樹脂工程で、封止樹
脂をベアチップＩＣと配線基板の間の狭いギヤップに侵
入させて充填させる必要があり、短時間で効率よく処理
するのが困難であった。However, in the first example of the above-mentioned mounting technique, the flux applying step and the flux removing step after solder connection are complicated and not preferable.
In addition, in the sealing resin process after the flip chip connection, it is necessary to inject and fill the sealing resin into a narrow gap between the bare chip IC and the wiring board, and it is difficult to efficiently process the resin in a short time. .
【００２１】また、ベアチップＩＣの全面にバンプが配
置されるとフリップチップ接続が困難になる。さらに、
ベアチップＩＣの全面に、エリヤバンプ配置で、かつ、
バンプピッチが３００μｍ以下になると、封止樹脂の封
止工程がさらに困難になる。Further, if bumps are arranged on the entire surface of the bare chip IC, flip chip connection becomes difficult. further,
Area bumps are arranged on the entire surface of the bare chip IC, and
If the bump pitch is 300 μm or less, the sealing resin sealing step becomes more difficult.
【００２２】また、第２の例の場合は、プロセス上はん
だ溶融と絶縁樹脂の加熱硬化が同時に進行するために、
配線基板へのベアチップＩＣの実装後に、不良のベアチ
ップＩＣを剥離除去（リペア）することが出来ない。そ
のため、歩留りが低下する。In the case of the second example, since the melting of the solder and the heat curing of the insulating resin proceed simultaneously in the process,
After mounting the bare chip IC on the wiring board, the defective bare chip IC cannot be removed and repaired. Therefore, the yield decreases.
【００２３】さらに、これらの各例では、配線基板の電
極とベアチップＩＣの電極との電気的な接続のために、
バンプ形成が必須となるため、実装コストが高く、低コ
ストが課題であった。Further, in each of these examples, in order to electrically connect the electrode of the wiring board and the electrode of the bare chip IC,
Since bump formation is indispensable, mounting cost is high and low cost has been a problem.
【００２４】本発明はこれらの事情にもとづいてなされ
たもので、配線基板にベアチップＩＣを実装して製造す
る半導体装置で、簡便な工程で生産性の高い半導体装置
の製造方法と、それによる半導体装置を提供することを
目的としている。The present invention has been made in view of the above circumstances, and relates to a semiconductor device manufactured by mounting a bare chip IC on a wiring board. It is intended to provide a device.
【００２５】[0025]
【課題を解決するための手段】請求項１の発明による手
段によれば、配線基板の電極に異方性導電材を介してＩ
Ｃチップの電極が接合されている半導体装置において、
前記異方性導電材は、絶縁樹脂の中に前記絶縁樹脂の硬
化反応温度よりも高い融点を有する溶融形導電粒子が分
散されていることを特徴とする半導体装置である。According to the first aspect of the present invention, an electrode on a wiring board is connected to an electrode via an anisotropic conductive material.
In a semiconductor device to which electrodes of a C chip are joined,
The semiconductor device is characterized in that the anisotropic conductive material has molten conductive particles having a melting point higher than a curing reaction temperature of the insulating resin dispersed in the insulating resin.
【００２６】また請求項２の発明による手段によれば、
配線基板の電極と、ＩＣチップの電極とを封止樹脂で固
定するとともに電気的に接合する半導体装置の製造方法
において、前記封止樹脂が硬化しない温度で前記封止樹
脂に分散させた前記溶融形導電粒子を溶融することによ
って前記配線基板の電極と前記ＩＣチップとの電極とを
電気的に接続する接続工程と、前記配線基板の電極と前
記ＩＣチップとの電極とが接続された後に、前記封止樹
脂を前記溶融形導電粒子が溶融しない温度で硬化させる
硬化工程とを有することを特徴とする半導体装置の製造
方法である。According to the second aspect of the present invention,
In a method of manufacturing a semiconductor device in which an electrode of a wiring board and an electrode of an IC chip are fixed and electrically connected to each other with an encapsulating resin, the method of manufacturing a semiconductor device, wherein A step of electrically connecting the electrodes of the wiring board and the electrodes of the IC chip by melting the shaped conductive particles, and after the electrodes of the wiring board and the electrodes of the IC chip are connected, A curing step of curing the sealing resin at a temperature at which the molten conductive particles do not melt.
【００２７】また請求項３の発明による手段によれば、
前記接続工程の後の前記硬化工程の前に、前記ＩＣチッ
プの電極と前記配線基板の電極との導通検査を行なう工
程を設けたことを特徴とする半導体装置の製造方法であ
る。According to the third aspect of the present invention,
A method of manufacturing a semiconductor device, further comprising a step of performing a continuity test between electrodes of the IC chip and electrodes of the wiring board before the curing step after the connecting step.
【００２８】[0028]
【発明の実施の形態】以下、本発明の半導体装置とその
製造方法の実施の形態を、図面を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.
【００２９】図１は本発明の第１実施の形態を示す半導
体装置の側面断面図である。配線基板１は、厚さ１．０
ｍｍ程度のガラスエポキシ材の基板の表面には、３００
μｍピッチの銅の配線パターンが形成され、その一部に
金めっき、あるいは、はんだめっきを施した電極２ａ、
２ｂ、２ｃ…２ｎが形成されている。なお、基板の材料
には、ガラスエポキシ材の他に、ポリイミドやセラミッ
クス等を用いることもできる。FIG. 1 is a side sectional view of a semiconductor device according to a first embodiment of the present invention. The wiring board 1 has a thickness of 1.0
300 mm on the surface of the glass epoxy material substrate
A copper wiring pattern with a pitch of μm is formed, and a part of the electrode 2a is gold-plated or solder-plated.
2b, 2c... 2n are formed. In addition, as the material of the substrate, polyimide, ceramic, or the like can be used in addition to the glass epoxy material.
【００３０】この電極２ａ、２ｂ、２ｃ…２ｎ上には、
はんだバンプ３ａ、３ｂを介してＩＣチップであるベア
チップＩＣ４が実装されている。なお、ベアチップＩＣ
４は表面に電気めっき法により、接続電極４ａ、４ｂ、
４ｃ…４ｎの上に、はんだバンプ３ａ、３ｂ形成されて
いる。On the electrodes 2 a , 2 b , 2 c ... 2 n ,
Bare chip IC4 is an IC chip through the solder bumps 3 a, 3 b are mounted. In addition, bare chip IC
Reference numeral 4 denotes connection electrodes 4 a , 4 b ,
Over 4 c ... 4 n, are solder bump 3 a, 3 b formed.
【００３１】また、配線基板１とベアチップＩＣ４との
間、および、ベアチップＩＣ４の側面には、封止樹脂で
あるエポキシ樹脂等の絶縁樹脂５に溶融形導電粒子
６ａ、６ ｂ、６ｃ…６ｎが分散された異方性導電材７が
充填されている。The wiring board 1 and the bare chip IC 4
In between, and on the side surface of the bare chip IC 4, a sealing resin is used.
Fused conductive particles in insulating resin 5 such as epoxy resin
6a, 6 b, 6c… 6nIs dispersed in the anisotropic conductive material 7
Is filled.
【００３２】溶融形導電粒子６ａ、６ｂ、６ｃ…６
ｎは、図２（ａ）から（ｂ）に示すいずれかのものを、
単独又は任意に組合わせて用いることができる。The molten conductive particles 6 a , 6 b , 6 c ... 6
n is any of those shown in FIGS. 2A to 2B,
They can be used alone or in any combination.
【００３３】図２（ａ）に示した溶融形導電粒子６ａ、
６ｂ、６ｃ…６ｎは、粒径が３０μｍ〜５０μｍ程度の
はんだボール８の外側に、厚さ１０μｍ〜２０μｍ程度
のフラックス９の被膜がコーティグ処理により形成され
ている。なお、図示しないが、溶融形導電粒子の中央部
を粒径が２０〜３５μｍ程度のフラックスをコアとする
ボールで形成し、その外側をはんだ被膜で覆うというは
んだボールとフラックスの構成を逆にした構成であって
もよい。そのフラックスをコアとする溶融形導電粒子の
製法は、固形状のはんだとフラックスを、漸次、孔径が
小さく形成されている微小孔を通して、塑性変形させな
がら延ばして、中央部がフラックスで、その周囲がはん
だで構成される糸はんだを製作する。次に、その糸はん
だを、棒状に分断し、先端と後端を絞り成形すること
で、はんだボールを製造することが可能である。The molten conductive particles 6 a , shown in FIG.
6 b, 6 c ... 6 n, the particle size is outside of the solder balls 8 of about 30-50 microns, coating of flux 9 having a thickness of about 10μm~20μm is formed by Kotigu process. Although not shown, the configuration of the solder ball and the flux, in which the central portion of the molten conductive particles is formed of a ball having a core of a flux having a particle size of about 20 to 35 μm and the outside thereof is covered with a solder coating, are reversed. It may be a configuration. The method of producing fused conductive particles with the flux as the core is to gradually extend the solid solder and flux through plastic micro-pores with a small hole diameter while plastically deforming them. Produces thread solder consisting of solder. Next, it is possible to manufacture a solder ball by dividing the thread solder into a rod shape and drawing the front end and the rear end by drawing.
【００３４】図２（ｂ）に示した溶融形導電粒子６ａ、
６ｂ、６ｃ…６ｎは、銅等によるメタルコア１１の外側
に、はんだ１２の接合材料を被覆し、さらにその外側に
フラックス９をコーティングにより被覆して形成したも
のである。The molten conductive particles 6 a , shown in FIG.
6 b, 6 c ... 6 n is outside the metal core 11 of copper or the like, coated with a bonding material of solder 12, and is formed by further coated with a coating flux 9 on the outside.
【００３５】図２（ｃ）に示した溶融形導電粒子６ａ、
６ｂ、６ｃ…６ｎは、図２（ｂ）に示した溶融形導電粒
子６ａ、６ｂ、６ｃ…６ｎの構造において、最外層のフ
ラックス９が被覆されていない構成のものである。この
場合、異方性導電材７に分散して使用する際は、別にフ
ラックスを分散させるか、あるいは、絶縁樹脂５にフラ
ックス作用を持たせるようにする。The molten conductive particles 6 a , shown in FIG.
6 b, 6 c ... 6 n, in molten form conductive particles 6 a, 6 b, 6 c ... 6 n structure shown in FIG. 2 (b), having a structure in which the outermost layer of the flux 9 is not covered It is. In this case, when used by dispersing in the anisotropic conductive material 7, the flux is separately dispersed, or the insulating resin 5 has a flux action.
【００３６】なお、溶融形導電粒子６ａ、６ｂ、６ｃ…
６ｎは錫・鉛・インジウム・ビスマス・金等の組合せか
らなる共晶形はんだ等としても応用することが可能であ
る。その場合の、はんだの組成は、鉛３７％−錫６３
％、鉛９５％−錫５％、錫９６．５％−銀３．５％、他
インジウム添加等で、フラックス９は主剤（アビチエン
酸等のロジン）＋溶剤（アルコール等）である。The molten conductive particles 6 a , 6 b , 6 c ...
6 n is can also be applied as a co-crystal form solder consisting of a combination of such tin-lead, indium, bismuth-gold. In that case, the composition of the solder was 37% lead-63 tin.
%, Lead 95% -tin 5%, tin 96.5% -silver 3.5%, and other indium additions. The flux 9 is a main agent (rosin such as abithienoic acid) + a solvent (alcohol or the like).
【００３７】異方性導電材は、絶縁性の熱硬化形樹脂の
中に、上述の溶融形導電粒子のいずれかを１０〜２５％
程度を分散させることで製造されている。また、異方性
導電材の形状は、シート状もしくはぺースト状に形成す
ることができる。シート状の異方性導電材７の製造方法
は、硬化前のエポキシ樹脂に、溶融形導電粒子をあらか
じめ分散して混練し、その後にシート状に引き延ばし
て、仮硬化させる。また、絶縁性の熱硬化形樹脂の種類
は、アクリル（変性）樹脂、ポリイミド樹脂、ブタジエ
ン樹脂、フェノール樹脂等を用いることができる。The anisotropic conductive material contains 10 to 25% of any of the above-mentioned molten conductive particles in an insulating thermosetting resin.
It is manufactured by dispersing the degree. Further, the shape of the anisotropic conductive material can be formed in a sheet shape or a paste shape. In the method of manufacturing the sheet-shaped anisotropic conductive material 7, the molten conductive particles are dispersed and kneaded in advance in the epoxy resin before curing, and then are stretched into a sheet shape and temporarily cured. Further, as the kind of the insulating thermosetting resin, an acrylic (modified) resin, a polyimide resin, a butadiene resin, a phenol resin, or the like can be used.
【００３８】次に、本発明の第１の実施の形態である異
方性導電材を用いたフリップチップ実装方法を説明す
る。図３（ａ）〜（ｅ）は、本発明のフリップチップ実
装方法の工程模式図である。なお、ボンディング装置
は、一般に用いられている装置を使用しているので、装
置関係の説明は省略する。Next, a method of mounting a flip chip using an anisotropic conductive material according to a first embodiment of the present invention will be described. FIGS. 3A to 3E are process schematic diagrams of the flip chip mounting method of the present invention. The bonding apparatus uses a generally used apparatus, and a description of the apparatus will be omitted.
【００３９】まず、厚さ１．０ｍｍ程度のガラスエポキ
シ材の基板の表面に、３００μｍピッチの銅の配線パタ
ーンが形成され、その一部に金めっき、あるいは、はん
だ処理を施した電極２ａ、２ｂ、２ｃ…２ｎが形成され
ている配線基板１を図示しないボンディング装置にセッ
トする（ａ）。First, a copper wiring pattern having a pitch of 300 μm is formed on the surface of a glass epoxy material substrate having a thickness of about 1.0 mm, and a part of the electrode 2 a is subjected to gold plating or soldering. The wiring substrate 1 on which 2 b , 2 c ... 2 n are formed is set in a bonding device (not shown) (a).
【００４０】次に、配線基板１の電極２ａ、２ｂ、２ｃ
…２ｎの形状、もしくは、チップの外形サイズ程度に外
形を切断したシート状の異方性導電材７を配線基板１上
に形成する。Next, the electrodes 2 a , 2 b , 2 c of the wiring board 1 are
.. A sheet-shaped anisotropic conductive material 7 having a shape of 2 n or an outer shape cut to about the outer size of a chip is formed on the wiring board 1.
【００４１】または、シート状の異方性導電材７の代わ
りに異方性導電ぺースト７ａを用いて、ディスペンサ１
３により、配線基板１の表面にディスペンス塗布する
（ｂ）。[0041] or by using an anisotropic conductive paste 7 a in place of a sheet-like anisotropic conductive material 7, the dispenser 1
3 is applied to the surface of the wiring substrate 1 by dispensing (b).
【００４２】次に、ボンディングツール１４に吸着さ
れ、接続電極４ａ、４ｂ、４ｃ…４ｎ上に、はんだバン
プ３ａ、３ｂが予め形成されているベアチップＩＣ４
を、はんだバンプ３ａ、３ｂを異方性導電材７（また
は、異方性導電ペースト７ａ）を介して、配線基板１の
電極２ａ、２ｂ、２ｃ…２ｎに位置合わせして仮固定す
る（ｃ）。この際は、異方性導電材７の絶縁樹脂５であ
るエポキシ樹脂の粘着力で、ベアチップＩＣ４と配線基
板１とを固定することができる。また、ベアチップＩＣ
４のはんだバンプ３ａ、３ｂと配線基板１の電極２ａ、
２ｂ、２ｃ…２ｎとの間には、異方性導電材７の溶融形
導電粒子６ａ、６ｂ、６ｃ…６ｎの複数個が分散配置し
て介在している。Next, adsorbed to the bonding tool 14, connecting electrodes 4a, 4b, on the 4c ... 4n, bare chip solder bump 3 a, 3 b are previously formed IC4
The solder bumps 3 a, 3 b anisotropic conductive material 7 (or anisotropic conductive paste 7 a) through the electrode 2 a of the wiring board 1, 2 b, 2 c ... aligned 2 n And temporarily fixed (c). At this time, the bare chip IC 4 and the wiring board 1 can be fixed by the adhesive force of the epoxy resin as the insulating resin 5 of the anisotropic conductive material 7. In addition, bare chip IC
4 solder bumps 3 a , 3 b and the electrodes 2 a ,
Between the 2 b, 2 c ... 2 n , melt-type conductive particles 6 a of the anisotropic conductive material 7, of 6 b, 6 c ... 6 n plurality is interposed and distributed.
【００４３】次に、加熱ヒータ機能を具えたボンディン
グツール１４を用いて、加熱のピーク温度１５０℃程度
で、加熱加圧してはんだを溶融することにより、配線基
板１の電極２ａ、２ｂ、２ｃ…２ｎとはんだバンプ
３ａ、３ｂを接合して、配線基板１にチップベアチップ
ＩＣ４を電気的に接続する。なお、この接合の際に、異
方性導電材７の溶融形導電粒子６ａ、６ｂ、６ｃ…６ｎ
の中のフラックス９がはんだの濡れ性を促進して、良好
なはんだ付けが達成できる（ｄ）。Next, by using a bonding tool 14 having a heater function, the solder is melted by heating and pressing at a heating peak temperature of about 150 ° C., so that the electrodes 2 a , 2 b , by joining 2 c ... 2 n and solder bump 3 a, 3 b, to electrically connect the chip bare chip IC4 on the wiring board 1. At the time of this joining, the molten conductive particles 6 a , 6 b , 6 c ... 6 n of the anisotropic conductive material 7 are used.
The flux 9 in the above promotes solder wettability, and good soldering can be achieved (d).
【００４４】次に、異方性導電材７の絶縁樹脂５である
エポキシ樹脂を、１５０℃から２００℃程度で加熱硬化
させる。この処理により、微細はんだ接続と絶縁樹脂５
による樹脂封止とを一括リフロー工程で実現できる
（ｅ）。Next, the epoxy resin, which is the insulating resin 5 of the anisotropic conductive material 7, is cured by heating at about 150 to 200.degree. By this processing, fine solder connection and insulating resin 5
Can be realized by a batch reflow process (e).
【００４５】図４は、本発明のフリップチップ実装工程
のシーケンスを説明する温度プロファィルを示したチャ
ートである。FIG. 4 is a chart showing a temperature profile for explaining the sequence of the flip chip mounting process of the present invention.
【００４６】この実装工程では、はんだは、その溶融温
度が絶縁樹脂の硬化温度より低いものを用いている。ま
た、前半の工程で、はんだ接続（温度Ｔ２）を行い、後
半の工程で樹脂硬化（温度Ｔ１）を行っている。In this mounting step, the solder used has a melting temperature lower than the curing temperature of the insulating resin. In the first half, solder connection (temperature T2) is performed, and in the second half, resin curing (temperature T1) is performed.
【００４７】なお、絶縁樹脂の硬化のタイミングは、絶
縁樹脂の組成と硬化剤の組合せにより制御が可能である
ので、絶縁樹脂の反応硬化率を、はんだ接続時（温度Ｔ
２）では０％で、樹脂硬化時（温度Ｔ１）で１００％に
なるように樹脂組成を制御する。例えば、エポキシ樹脂
の変性と硬化反応剤（アミン系等）の組合せにより硬化
温度が、１２０〜２００℃以上の範囲内で調整が可能で
ある。The timing of curing of the insulating resin can be controlled by a combination of the composition of the insulating resin and the curing agent.
In 2), the resin composition is controlled so that it is 0% and becomes 100% when the resin is cured (temperature T1). For example, the curing temperature can be adjusted within the range of 120 to 200 ° C. or more by a combination of the modification of the epoxy resin and a curing reactant (amine or the like).
【００４８】また、硬化時間も数秒〜数時間で調整でき
る。短時間での硬化を実現するためには、硬化剤はマイ
クロカプセル化して用いると効果的である。特に、数秒
の硬化時間の場合は、硬化反応剤を薄い樹脂で覆い、所
望の温度（例えば、数１０℃）で被膜を破る様なマイク
ロカプセルを用いることにより、硬化反応のタイミング
の制御が可能である。Also, the curing time can be adjusted from several seconds to several hours. In order to realize curing in a short time, it is effective to use the curing agent in the form of microcapsules. In particular, when the curing time is several seconds, the timing of the curing reaction can be controlled by covering the curing reactant with a thin resin and using microcapsules that break the film at a desired temperature (for example, several tens of degrees Celsius). It is.
【００４９】その際には、ボンディング装置のステージ
とボンディングツールとには、加熱ヒータを装備して、
温度プロフアイルの制御を可能にすることで容易に実現
できる。At this time, the stage of the bonding apparatus and the bonding tool are equipped with a heater,
This can be easily realized by enabling control of the temperature profile.
【００５０】この方式は、はんだ接合の際にベアチップ
ＩＣ４押圧して、電極間の接続を確実にできるメリット
がある。また、後の検査工程で、不具合品を発見した際
には、加熱することにより接続部を溶融して、ベアチッ
プＩＣと配線基板とを分離し、不具合部品を交換して上
述のプロセスで接合して良品を製造することができる。This method has an advantage that the bare chip IC 4 is pressed at the time of soldering to ensure the connection between the electrodes. Further, when a defective product is found in a later inspection process, the connecting portion is melted by heating, the bare chip IC is separated from the wiring board, the defective component is replaced, and the defective component is joined by the above process. Good products can be manufactured.
【００５１】また、この第１の実施の形態には、はんだ
接続後に追加工程として、ベアチップＩＣの接続検査を
行ない、不具合品を発見した際には、加熱することによ
り接続部を溶融して、接続の修正等を行なうことができ
る。Also, in the first embodiment, as an additional step after solder connection, a bare chip IC connection inspection is performed, and when a defective product is found, the connection is melted by heating. Correction of connection and the like can be performed.
【００５２】それは、図４で示したように、はんだ接続
していても絶縁樹脂は硬化していないので、もし、接続
不良やＩＣチップの動作機能不良が確認されたときに
は、はんだ接続部を加熱溶融することで、ベアチップＩ
Ｃを配線基板から容易に取り外すことがでる。それによ
り、別のベアチップＩＣを再搭載（リぺア）することも
できる。As shown in FIG. 4, since the insulating resin is not cured even when the solder connection is made, if the connection failure or the malfunction of the operation of the IC chip is confirmed, the solder connection portion is heated. By melting, bare chip I
C can be easily removed from the wiring board. As a result, another bare chip IC can be mounted (rearranged).
【００５３】図５に、この検査工程が付加されたプロセ
スの温度プロファイルを示す。この場合、はんだ接続後
に接続の電気検査を行うため、ベアチップＩＣを実装し
た配線基板は、そのために、一度ボンディング装置から
取り外す。その後、必要に応じてリペア等の工程を行
い、それ以降に、樹脂硬化のためにオーブン乾燥等を行
う。FIG. 5 shows a temperature profile of a process to which the inspection step is added. In this case, the wiring board on which the bare chip IC is mounted is once removed from the bonding apparatus in order to perform an electrical inspection of the connection after the solder connection. After that, a process such as repair is performed as necessary, and thereafter, oven drying or the like is performed to cure the resin.
【００５４】なお、オーブン乾燥時には、絶縁樹脂の加
熱膨潤により、はんだ接続がオープンになる場合を防ぐ
ために、ベアチップＩＣの裏面から押圧手段（不図示）
を用いて押圧して行なうのが好ましい。During oven drying, a pressing means (not shown) is applied from the back surface of the bare chip IC to prevent the solder connection from being opened due to the heat swelling of the insulating resin.
It is preferable to carry out the pressing by using.
【００５５】次に、本発明の第２の実施の形態について
説明する。Next, a second embodiment of the present invention will be described.
【００５６】図６は本発明の半導体装置の一例を示す、
第２実施の形態である半導体装置の側面断面図である。FIG. 6 shows an example of the semiconductor device of the present invention.
FIG. 14 is a side sectional view of a semiconductor device according to a second embodiment;
【００５７】配線基板２１は、厚さ１．０ｍｍ程度のガ
ラスエポキシ材の基板の表面には、３００μｍピッチの
銅の配線パターンが形成され、その一部に金めっき、あ
るいは、はんだ処理を施した電極２２ａ、２２ｂ、２２
ｃ…２２ｎが形成されている。なお、基板の材料には、
ガラスエポキシ材の他に、ポリイミドやセラミックス等
を用いることもできる。The wiring board 21 has a 300 μm pitch copper wiring pattern formed on the surface of a glass epoxy material substrate having a thickness of about 1.0 mm, and a part thereof is subjected to gold plating or soldering. Electrodes 22 a , 22 b , 22
c ... 22 n are formed. In addition, the material of the substrate
In addition to the glass epoxy material, polyimide, ceramic, or the like can be used.
【００５８】この電極２２ａ、２２ｂ、２２ｃ…２２ｎ
上には、接続電極２４ａ、２４ｂ、２４ｃ…２４ｎによ
り接合したベアチップＩＣ２４が実装されている。ま
た、配線基板２１とベアチップＩＣ２４との間、およ
び、ベアチップＩＣ２４の側面には、エポキシ樹脂等の
絶縁樹脂２５に溶融形導電粒子２６ａ、２６ｂ、２６ｃ
…２６ｎが分散された異方性導電材２７が充填されてい
る。The electrodes 22 a , 22 b , 22 c ... 22 n
A bare chip IC 24 joined by connection electrodes 24 a , 24 b , 24 c ... 24 n is mounted thereon. In addition, between the wiring board 21 and the bare chip IC 24 and on the side surface of the bare chip IC 24, an insulating resin 25 such as an epoxy resin is added to the molten conductive particles 26 a , 26 b and 26 c
... anisotropic conductive material 27 26 n are dispersed is filled.
【００５９】なお、溶融形導電粒子２６ａ、２６ｂ、２
６ｃ…２６ｎおよび異方性導電材２７については、第１
の実施の形態の際に説明したものと同様なので、その説
明は省略する。The molten conductive particles 26 a , 26 b , 2
6 For c ... 26 n and the anisotropic conductive material 27, the first
Since this is the same as that described in the embodiment, the description thereof is omitted.
【００６０】次に、本発明の第２の実施の形態の実装方
法を、図７（ａ）から（ｅ）に示す工程模式図を参照し
て説明する。Next, a mounting method according to a second embodiment of the present invention will be described with reference to schematic process diagrams shown in FIGS.
【００６１】なお、第１の実施の形態と同様に、ボンデ
ィング装置は、一般に用いられている装置を用いている
ので、装置関係の説明は省略する。As in the first embodiment, the bonding apparatus uses a generally used apparatus, and a description of the apparatus will be omitted.
【００６２】まず、厚さ１．０ｍｍ程度のガラスエポキ
シ材の基板の表面に、３００μｍピッチの銅の配線パタ
ーンが形成され、その一部に金めっき、あるいは、はん
だ処理を施した電極２２ａ、２２ｂ、２２ｃ…２２ｎが
形成されている配線基板１を図示しないボンディング装
置にセットする（ａ）。First, a copper wiring pattern having a pitch of 300 μm is formed on the surface of a glass epoxy material substrate having a thickness of about 1.0 mm, and a part of the electrode 22 a is gold-plated or soldered. The wiring substrate 1 on which 22 b , 22 c ... 22 n are formed is set in a bonding device (not shown) (a).
【００６３】次に、配線基板２１の電極２２ａ、２
２ｂ、２２ｃ…２２ｎ状、もしくは、チップの外形サイ
ズ程度に外形を切断したシート状の異方性導電材２７を
配線基板２１上に形成する。または、シート状の異方性
導電材２７の代わりに異方性導電ぺースト２７ａを用い
て、ディスペンサ３３により、配線基板２１の表面にデ
ィスペンス塗布する（ｂ）。Next, the electrodes 22 a , 2
2 b, 22 c ... 22 n shaped, or, to form a sheet-like anisotropic conductive material 27 obtained by cutting the outer shape contour about the size of the chip on the wiring board 21. Or by using an anisotropic conductive paste 27 a in place of a sheet-like anisotropic conductive material 27, the dispenser 33 dispenses applied to the surface of the wiring board 21 (b).
【００６４】次に、ボンディングツール３４に吸着され
て、接続電極２４ａ、２４ｂ、２４ ｃ…２４ｎが予め形
成されているベアチップＩＣ２４を溶融導形電粒子２６
ａ、２６ｂ、２６ｃ…２６ｎが分散している異方性導電
材２７（または、異方性導電ペースト２７ａ）を介し
て、配線基板２１の電極２２ａ、２２ｂ、２２ｃ…２２
ｎに位置合わせして仮固定する（ｃ）。この際は、異方
性導電材２７の絶縁樹脂２５である、エポキシ樹脂の粘
着力で、ベアチップＩＣ２４と配線基板２１とを固定す
ることができる。また、ベアチップＩＣ２４の接続電極
２４ａ、２４ｂ、２４ｃ…２４ｎと配線基板２１の電極
２２ａ、２２ｂ、２２ｃ…２２ｎとの間には、異方性導
電材２７の溶融導形電粒子２６ａ、２６ｂ、２６ｃ…２
６ｎの複数個が分散配置して介在している。Next, it is adsorbed by the bonding tool 34.
And the connection electrode 24a, 24b, 24 c… 24nIs pre-shaped
The formed bare chip IC 24 is fused with the fused conductive particles 26.
a, 26b, 26c… 26nAnisotropic conductive with dispersed
Material 27 (or anisotropic conductive paste 27)aThrough)
And the electrode 22 of the wiring board 21a, 22b, 22c… 22
nAnd temporarily fixed (c). In this case,
Of the epoxy resin, which is the insulating resin 25 of the conductive material 27,
The bare chip IC 24 and the wiring board 21 are fixed by force.
Can be Also, the connection electrode of the bare chip IC 24
24a, 24b, 24c… 24nAnd electrodes of the wiring board 21
22a, 22b, 22c… 22nBetween the anisotropic conduction
Fused conductive particles 26 of electric material 27a, 26b, 26c… 2
6nAre distributed and interposed.
【００６５】なお、ベアチップＩＣ２４の接続電極２４
ａ、２４ｂ、２４ｃ…２４ｎは、例えばクロム、ニッケ
ル、金の金属を蒸着やスパッタ法で形成したバリヤメタ
ルも用い、その他にも、無電解ニッケルと金めっきの組
合せ処理たものを用いてもよい。また、第１の実施の形
態と同様に、はんだバンプ３ａ、３ｂを形成したものを
用いることもできる。いずれにしろ、溶融導電粒子のは
んだが溶融して濡れる、接続電極２４ａ、２４ｂ、２４
ｃ…２４ｎの表面処理であれば良い。The connection electrode 24 of the bare chip IC 24
a , 24b , 24c ... 24n are, for example, a barrier metal formed by vapor deposition or sputtering of chromium, nickel, or gold, or a combination of electroless nickel and gold plating. Is also good. Further, similarly to the first embodiment, the one having the solder bumps 3a and 3b formed thereon can be used. In any case, the connection electrodes 24 a , 24 b , and 24 melt the solder of the molten conductive particles and get wet.
c ... Any surface treatment of 24 n may be used.
【００６６】次に、加熱ヒータ機能を具えたボンディン
グツール３４を用いて、加熱のピーク温度が２４０℃程
度で、はんだを溶融して、配線基板２１の電極２２ａ、
２２ ｂ、２２ｃ…２２ｎとベアチップＩＣ２４の接続電
極２４ａ、２４ｂ、２４ｃ…２４ｎとを電気的に接続す
る。なお、この接合の際に、異方性導電材２７の溶融形
導電粒子の中のフラックス２９がはんだの濡れ性を促進
して、良好なはんだ付けが達成できる（ｄ）。Next, a bond having a heater function
Using the gutool 34, the peak temperature of the heating is about 240 ° C.
The solder is melted at a time and the electrodes 22 of the wiring board 21 are melted.a,
22 b, 22c… 22nConnection between the chip and bare chip IC24
Pole 24a, 24b, 24c… 24nElectrically connect to
You. In addition, at the time of this joining, the molten form of the anisotropic conductive material 27 is used.
Flux 29 in conductive particles promotes solder wettability
Thus, good soldering can be achieved (d).
【００６７】さらに、異方性導電材２７の絶縁樹脂２５
であるエポキシ樹脂を、１５０℃から２００℃程度で加
熱硬化させる。この処理により、微細はんだ接続と樹脂
封止とを連続した製造工程が実現できる。Further, the insulating resin 25 of the anisotropic conductive material 27
Is heated and cured at about 150 ° C. to 200 ° C. By this processing, a continuous manufacturing process of fine solder connection and resin sealing can be realized.
【００６８】図８は、これらの実装工程のシーケンスを
説明する温度プロファィルを示したチャートである。FIG. 8 is a chart showing a temperature profile for explaining the sequence of these mounting steps.
【００６９】この実装工程では、はんだは、その溶融温
度が絶縁樹脂の硬化温度より高いものを用いている。ま
た、前半の工程で、はんだ接続（Ｔ２）を行い、後半の
工程で樹脂硬化（Ｔ１）を行っている。In this mounting step, the solder used has a melting temperature higher than the curing temperature of the insulating resin. In the first half, solder connection (T2) is performed, and in the second half, resin curing (T1) is performed.
【００７０】なお、第１の実施の形態で説明したよう
に、絶縁樹脂の硬化のタイミングは、絶縁樹脂の組成と
硬化剤の組合せで制御が可能であるので、それにより、
絶縁樹脂の反応硬化性を遅くすることを用いることで、
はんだ接続時には、絶縁樹脂が未硬化状態を維持する制
御を行なうことができる。As described in the first embodiment, the curing timing of the insulating resin can be controlled by a combination of the composition of the insulating resin and the curing agent.
By slowing down the reaction curability of the insulating resin,
At the time of solder connection, control for maintaining the uncured state of the insulating resin can be performed.
【００７１】なお、異方性導電材や異方性導電ペースト
に分散する溶融形導電粒子として、図２（ａ）から
（ｃ）で示した形態の他に、使用温度によっては、はん
だボール８とフラックス９を分離して樹脂に混在分散す
る形態のものを用いることもできる。As the molten conductive particles dispersed in the anisotropic conductive material or the anisotropic conductive paste, in addition to the forms shown in FIGS. And the flux 9 may be separated and mixed and dispersed in a resin.
【００７２】以上に述べたように、本発明によれば、通
常の従来の製造工程で行なわれていたフラックス塗布と
洗浄工程が不要になり、かつ、封止樹脂工程が極めて簡
便にできるため、製造工程の簡素化が実現できる。As described above, according to the present invention, the flux application and washing steps, which are performed in the conventional manufacturing process, become unnecessary, and the sealing resin process can be extremely simplified. Simplification of the manufacturing process can be realized.
【００７３】また、配線基板へベアチップＩＣを実装後
に、不良品が発生した場合には、それを剥離除去（リぺ
ア）できる工程を付加できるので、製造工程での損失の
縮減を行なうことができる。Further, if a defective product is generated after the bare chip IC is mounted on the wiring board, a process capable of peeling and removing (repairing) the defective product can be added, so that the loss in the manufacturing process can be reduced. it can.
【００７４】[0074]
【発明の効果】本発明によれば、簡便な製造プロセスを
用いることで、配線基板とベアチップＩＣの各電極同士
の接続が良好な半導体装置とその製造方法を提供するこ
とができる。According to the present invention, by using a simple manufacturing process, it is possible to provide a semiconductor device with good connection between the wiring substrate and each electrode of the bare chip IC and a manufacturing method thereof.
【図１】本発明の一例を示す第１実施の形態である半導
体装置の側面断面図。FIG. 1 is a side sectional view of a semiconductor device according to a first embodiment showing an example of the present invention;
【図２】（ａ）から（ｃ）は、本発明の溶融形導電粒子
の構造図。FIGS. 2 (a) to 2 (c) are structural views of the molten conductive particles of the present invention.
【図３】（ａ）〜（ｅ）は、本発明の第１実施の形態の
実装方法の工程模式図。FIGS. 3A to 3E are process schematic diagrams of the mounting method according to the first embodiment of the present invention.
【図４】本発明の実装方法の温度プロファィルのチャー
ト。FIG. 4 is a chart of a temperature profile of the mounting method of the present invention.
【図５】検査工程が付加されたプロセスの温度プロファ
イルのチャート。FIG. 5 is a chart of a temperature profile of a process to which an inspection step is added.
【図６】本発明の一例を示す第２実施の形態である半導
体装置の側面断面図。FIG. 6 is a side sectional view of a semiconductor device according to a second embodiment showing an example of the present invention;
【図７】（ａ）〜（ｅ）は、本発明の第２の実施の形態
の実装方法の工程模式図。FIGS. 7A to 7E are process schematic diagrams of a mounting method according to a second embodiment of the present invention.
【図８】本発明の第２の実施の形態の温度プロファィル
を示したチャート。FIG. 8 is a chart showing a temperature profile according to the second embodiment of the present invention.
【図９】（ａ）〜（ｆ）は、従来の実装方法の工程模式
図。FIGS. 9A to 9F are process schematic diagrams of a conventional mounting method.
【図１０】従来の実施の形態の温度プロファィルを示し
たチャート。FIG. 10 is a chart showing a temperature profile according to a conventional embodiment.
【図１１】（ａ）〜（ｅ）は、従来の実装方法の工程模
式図。FIGS. 11A to 11E are process schematic diagrams of a conventional mounting method.
【図１２】従来の実施の形態の温度プロファィルを示し
たチャート。FIG. 12 is a chart showing a temperature profile according to a conventional embodiment.
２１…配線基板、２ａ、２ｂ、２ｃ〜２ｎ、２２ａ、２
２ｂ、２２ｃ〜２２ｎ…電極、３ａ、３ｂ…バンプ、
４、２４…ベアチップＩＣ、５、２５…絶縁樹脂、
６ａ、６ｂ、６ｃ〜６ｎ、２６ａ、２６ｂ、２６ｃ〜２
６ｎ…溶融形導電粒子、７、２７…異方性導電材21 ... wiring board, 2 a, 2 b, 2 c ~2 n, 22 a, 2
2 b, 22 c ~22 n ... electrode, 3 a, 3 b ... bumps,
4, 24: bare chip IC, 5, 25: insulating resin,
6 a, 6 b, 6 c ~6 n, 26 a, 26 b, 26 c ~2
6 n ... melt-type conductive particles, 7, 27 ... anisotropic conductive material
フロントページの続き (72)発明者 唐沢 純 神奈川県横浜市磯子区新磯子町33番地 株 式会社東芝生産技術センター内 Ｆターム(参考） 4M109 AA01 BA03 CA04 EB11 5F044 KK01 LL05 LL09 QQ01 Continuing on the front page (72) Inventor Jun Karasawa 33rd Shinisogo-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term in the Toshiba Production Technology Center (reference) 4M109 AA01 BA03 CA04 EB11 5F044 KK01 LL05 LL09 QQ01
Claims (3)
ＩＣチップの電極が接合されている半導体装置におい
て、 前記異方性導電材は、絶縁樹脂の中に前記絶縁樹脂の硬
化反応温度よりも高い融点を有する溶融形導電粒子が分
散されていることを特徴とする半導体装置。1. A semiconductor device in which an electrode of an IC chip is joined to an electrode of a wiring board via an anisotropic conductive material, wherein the anisotropic conductive material is cured by a curing reaction of the insulating resin in the insulating resin. A semiconductor device, wherein molten conductive particles having a melting point higher than a temperature are dispersed.
を封止樹脂で固定するとともに電気的に接合する半導体
装置の製造方法において、 前記封止樹脂が硬化しない温度で前記封止樹脂に分散さ
せた前記溶融形導電粒子を溶融することによって前記配
線基板の電極と前記ＩＣチップとの電極とを電気的に接
続する接続工程と、前記配線基板の電極と前記ＩＣチッ
プとの電極とが接続された後に、前記封止樹脂を前記溶
融形導電粒子が溶融しない温度で硬化させる硬化工程と
を有することを特徴とする半導体装置の製造方法。2. A method for manufacturing a semiconductor device in which an electrode of a wiring board and an electrode of an IC chip are fixed with a sealing resin and electrically connected thereto, wherein the sealing resin is cured at a temperature at which the sealing resin does not cure. A connecting step of electrically connecting the electrodes of the wiring board and the electrodes of the IC chip by melting the dispersed molten conductive particles; and forming a connection between the electrodes of the wiring board and the electrodes of the IC chip. After the connection, a curing step of curing the sealing resin at a temperature at which the molten conductive particles do not melt.
に、前記ＩＣチップの電極と前記配線基板の電極との導
通検査を行なう工程を設けたことを特徴とする請求項２
記載の半導体装置の製造方法。3. The method according to claim 2, further comprising the step of conducting a continuity test between the electrodes of the IC chip and the electrodes of the wiring board before the curing step after the connecting step.
The manufacturing method of the semiconductor device described in the above.
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| JP2000202484A JP2002026070A (en) | 2000-07-04 | 2000-07-04 | Semiconductor device and its manufacturing method |
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|---|---|---|---|
| JP2000202484A JP2002026070A (en) | 2000-07-04 | 2000-07-04 | Semiconductor device and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004070827A1 (en) | 2003-02-05 | 2004-08-19 | Senju Metal Industry Co., Ltd. | Method for interconnecting terminals and method for mounting semiconductor device |
| JP2005089559A (en) * | 2003-09-16 | 2005-04-07 | Denso Corp | Method for connecting members using conductive adhesive |
| WO2006030674A1 (en) * | 2004-09-15 | 2006-03-23 | Matsushita Electric Industrial Co., Ltd. | Flip chip mounting method and flip chip mounting element |
| JP2006147968A (en) * | 2004-11-24 | 2006-06-08 | Matsushita Electric Ind Co Ltd | Method and device for flip chip packaging |
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2000
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