JP2008028135A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, along with its manufacturing method, in which cracking is suppressed on a solder electrode which is used for flip chip mounting. <P>SOLUTION: The semiconductor device 10 mainly comprises a mounting substrate 12, a pad 13 (conductive pattern) formed on the surface of the mounting substrate 12, a semiconductor element 11 which is flip-chip mounted, a bonding electrode 16 formed on the lower surface of the semiconductor element 11, a post 15 formed on the surface of the bonding electrode 16, and a solder electrode 14 which is positioned between the lower surface of the post 15 and the upper surface of the pad 13 to connect them together. The surface of the pad 13 is not coated with a plating film, and the solder electrode 14 directly contacts the pad 13. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a semiconductor element to be flip-chip mounted and a manufacturing method thereof.

  As a method for connecting semiconductor elements represented by LSI, there are a face-up connection method and a face-down connection method (flip chip mounting).

  When the semiconductor elements are connected face up, it is necessary to connect the electrodes formed on the upper surface of the semiconductor element and an external conductive pattern by a connecting means such as a thin metal wire. For this reason, it is necessary to provide a region for connecting the fine metal wires in the peripheral portion of the semiconductor element, which causes a problem that the area required for mounting the semiconductor element increases.

  On the other hand, when flip-chip mounting is performed, bumps disposed on the lower surface of the semiconductor element are used as connection means, so that it is not necessary to provide a connection region around the semiconductor element to be mounted. As a result, the area required for mounting the semiconductor element can be reduced, and high-density mounting is realized (see, for example, Patent Document 1 below).

  With reference to FIG. 9, an example of a method for mounting a semiconductor element employing flip chip mounting will be described.

  Referring to FIG. 9A, first, bumps 102 that function as connecting means are formed on the main surface of a semiconductor element 100 that is an LSI. The semiconductor element 100 includes an electric circuit for realizing a predetermined function using a well-known diffusion technique, and a pad 101 electrically connected to the electric circuit is formed on the surface of the semiconductor element 100. ing. The bumps 102 that function as connection means are formed on the upper surface of the pad 101. The bumps 102 are formed by arranging solder balls made of, for example, gold on the upper surface of the pad 101 using a bonder used for wire bonding.

  Referring to FIG. 9B, next, the semiconductor element 100 is mounted on the mounting substrate 103 with the main surface on which the bumps 102 are formed being the lower surface. On the upper surface of the mounting substrate 103, pads 104 are formed at positions corresponding to the bumps 102 of the semiconductor element 100. After the semiconductor element 100 is placed on the upper surface of the mounting substrate 103, the semiconductor element 100 is pressed from the upper surface in order to connect the bumps 102 of the semiconductor element 100 and the pads 104 of the mounting substrate 103.

FIG. 9C shows a cross section of the semiconductor element 100 mounted by the above process. Here, the semiconductor element 100 is mounted on the mounting substrate 103 by pressing the lower end of the bump 102 onto the upper surface of the pad 104. In order to improve the connection reliability between the two, an underfill may be filled between the semiconductor element 100 and the mounting substrate 103.
JP-A-5-136209

  However, in the semiconductor element mounting method to which the flip chip mounting described above is applied, there is a step of pressing the semiconductor element 100 downward from above in order to press the bump 102 against the surface of the pad 104. In order to suppress defects such as the occurrence of cracks in the semiconductor element 100, it is necessary to press the semiconductor element 100 with an equal pressure, which increases the cost of flip-chip mounting of the semiconductor element 100. In addition, there is a method using a gold ball formed in a substantially spherical shape in place of the bump 102 formed using the wire bonding technique, but even when the gold ball is used, the step of pressing the semiconductor element 100 from above. Therefore, it is difficult to solve the above-mentioned high cost problem.

  As a countermeasure against the above problem, if the bumps 102 are made of solder, the bumps 102 can be melted and flip-chip mounted by heating to about 200 ° C., and the pressing process described above can be eliminated. However, when solder is used as the material of the bump 102, there arises a problem that the bump 102 is cracked.

  FIG. 10 shows an image obtained by photographing a state in which a crack is generated in the bump 102 made of solder. In this figure, the semiconductor element 100, the pad 101, the bump 102, the pad 104, and the mounting substrate 103 are shown. From this image, it can be observed that a crack is generated from the left side of the bump 102 made of solder. When the bumps 102 are cracked in this way, there arises a problem that the pads 101 formed on the semiconductor element 100 and the pads 104 on the mounting substrate 103 are separated.

  The reason why the bump 102 is cracked is as follows. First, the surface (upper surface and side surface) of the pad 104 is covered with an electroless nickel plating film, and the surface of the nickel plating film is further covered with an electroless gold plating film. By doing so, the wettability of the solder of the pad 104 is improved, and the adhesion strength between the pad 104 and the bump 102 made of solder can be improved. However, the nickel plating film and the gold plating film formed by electroless plating are mixed with phosphorus, which is a catalyst, and these films are in a porous state and are easily eluted. Therefore, when the bump 102 made of solder is welded to the pad 104 by the reflow process, an intermetallic compound (alloy) made of nickel contained in the plating film covering the pad 104 and tin contained in the solder is generated. Mechanical strength deteriorates. Furthermore, since the solder constituting the bumps 102 is very small, most of the bumps 102 made of solder are formed of the above-described intermetallic compound, which promotes the generation of cracks. As a result, the bump 102 is cracked as shown in the figure in the reflow process in which the bump 102 is welded or in the use state. Such a problem occurs even when a lead eutectic solder containing lead is adopted as the bump 102, and even when a lead-free solder not containing lead is adopted as the bump 102.

  In particular, when lead-free solder that does not contain lead is used as the material of the bump 102, most of the general lead-free solder is made of tin, so that the generation rate of the above-described intermetallic compound is increased and the bump 102 is generated. The problem of cracking was remarkably occurring.

  Furthermore, if the surface of the pad 104 shown in FIG. 10 is covered with an electrolytic plating film, the above-described problem may be avoided. However, since the pads 104 formed for flip chip mounting are arranged very densely, it is not easy to form a plated wire for performing electrolytic plating on the mounting substrate 103. For this reason, it is difficult to form an electrolytic plating film on the surface of the pad 104.

  Accordingly, a main object of the present invention is to provide a semiconductor device in which cracks are suppressed from occurring in a solder electrode used for flip chip mounting and a method for manufacturing the same.

  The semiconductor device of the present invention has a semiconductor element that has a large number of electrodes on one main surface and is flip-chip mounted, and is provided at a position corresponding to the electrode of the semiconductor element and is electrically connected to the electrode The electrode of the semiconductor element and the conductive pattern are connected via a solder electrode that includes a conductive pattern and is in direct contact with the conductive pattern.

  Furthermore, the semiconductor device of the present invention includes a semiconductor element on which a plurality of electrodes projecting in the thickness direction are provided on one main surface and is flip-chip mounted on the mounting substrate corresponding to the position of the electrode of the semiconductor element. A conductive pattern provided and electrically connected to the electrode, and a filling resin filled between the semiconductor element and the mounting substrate, via a solder electrode that is in direct contact with the conductive pattern The electrode of the semiconductor element and the conductive pattern are connected.

  The method of manufacturing a semiconductor device according to the present invention includes a step of preparing a semiconductor element having an electrode protruding in the thickness direction, and a step of connecting the electrode of the semiconductor element to a conductive pattern by flip chip connection via a solder electrode. And the electrode is electrically connected to the conductive pattern via the solder electrode that is in direct contact with the conductive pattern.

  According to the semiconductor device of the present invention, the electrode of the semiconductor element to be flip-chip mounted and the conductive pattern are electrically connected via the solder electrode that is in direct contact with the conductive pattern. Therefore, unlike the background art, a large amount of intermetallic compounds are not formed inside the solder electrodes. Therefore, the generation of cracks due to the deterioration of the mechanical strength of the solder electrode can be suppressed.

  Furthermore, since the plating film for improving the wettability of the solder electrode is not formed on the surface of the conductive pattern, the spread of the solder electrode in the lateral direction is suppressed. For this reason, even when the bonding electrodes of the semiconductor element are densely arranged, the solder electrode attached to the tip of each bonding electrode does not swell in a barrel shape. Therefore, a sufficient gap is secured between the electrodes, and the filling resin can be easily filled from the gap.

  In the present embodiment, the configuration of the semiconductor device 10 will be described with reference to FIGS.

  1A is a cross-sectional view of the semiconductor device 10, and FIG. 1B is an enlarged cross-sectional view of a part of the semiconductor device 10.

  Referring to FIG. 1A, a semiconductor device 10 of the present embodiment includes a mounting substrate 12, pads 13 (conductive pattern) formed on the surface of the mounting substrate 12, a semiconductor element 11 that is flip-chip mounted, The bonding electrode 16 formed on the lower surface of the semiconductor element 11, the post 15 (electrode) formed on the surface of the bonding electrode 16, and the lower surface of the post 15 and the upper surface of the pad 13 are connected to each other. A solder electrode 14 is mainly provided.

  The semiconductor element 11 is an LSI in which an electric circuit is configured by a known diffusion process so that a predetermined function is realized, and a large number of bonding electrodes 16 are formed on the surface (lower surface). For example, when an ASIC (Application Specific Integrated Circuit) that performs image processing of a digital television is adopted as the semiconductor element 11, there are about 200 to 300 pieces around the periphery of the semiconductor element 11 having a size of about several millimeters square. Bonding electrodes 16 are densely provided. Accordingly, since a large number of bonding electrodes 16 are provided in the periphery of the semiconductor element 11 which is a small LSI chip, the distance between the bonding electrodes 16 is shortened. Specifically, the distance L1 between the bonding electrodes 16 is, for example, about 100 μm to 200 μm (for example, 130 μm). The thickness of the semiconductor element 11 is, for example, about 500 μm to 800 μm.

  The post 15 is a protruding electrode formed on the bonding electrode 16 of the semiconductor element 11 and has a cylindrical or prismatic shape. The post 15 is made of a conductive material such as copper formed by electrolytic plating. Referring to FIG. 1B, the length (L4) that the post 15 protrudes in the thickness direction of the semiconductor element 11 is, for example, about 20 μm to 40 μm. As described above, by providing the post 15 protruding in the thickness direction of the semiconductor element 11, the lower surface of the semiconductor element 11 to be flip-chip mounted and the mounting substrate 12 can be sufficiently separated, and an underfill is provided between the two. A sufficient space for filling 17 (filled resin) can be secured. Furthermore, even if thermal stress occurs due to the difference in thermal expansion coefficient between the semiconductor element 11 and the mounting substrate 12, this thermal stress can be reduced by deformation of the post 15.

  In addition, a plating film made of nickel or the like is formed on the lower surface of the post 15 in order to prevent diffusion of tin constituting the solder electrode 14 into the post 15. This plating film needs to be a plating film formed by an electrolytic plating method. The reason is that when the plating film formed on the lower surface of the post 15 is formed by an electroless plating method, as described above, a large amount of intermetallic compounds of nickel constituting the plating film and tin constituting the solder electrode 14 are obtained. This is because the mechanical strength of the solder electrode 14 deteriorates as a result. On the other hand, since the plated film formed by the electrolytic plating method has a strong crystal structure, the amount of the intermetallic compound generated is small, and as a result, the mechanical strength of the solder electrode 14 is maintained at a predetermined value or more.

  The solder electrode 14 is an electrode made of lead eutectic solder or lead-free solder, and has a function of connecting the post 15 on the semiconductor element 11 side and the pad 13 on the mounting substrate 12 side. In this embodiment, basically, the solder electrode 14 is formed so as to contact the lower surface of the post 15 and the upper surface of the pad 13. By doing in this way, there exists an advantage which can fill the underfill 17 easily by suppressing the breadth of the solder electrode 14 to the horizontal direction. Moreover, the thickness (L5) of the solder electrode 14 is, for example, about 10 μm to 20 μm. Specific examples of the material for the solder electrode 14 include Sn / Pb, Sn / Ag, Sn / Ag / Cu, Sn / Bi, Sn / Cu, Sn / Zn, Sn / Zn / Bi, and the like.

  The mounting substrate 12 is a substrate made of resin, ceramic, metal or the like, and a multilayer or single layer conductive pattern is formed on the surface thereof. Here, many pads 13 made of a conductive pattern are formed on the upper surface of the mounting substrate 12.

  The position of the pad 13 corresponds to the position of the bonding electrode 16 formed on the lower surface of the semiconductor element 11 and is made of a conductive pattern such as copper. The planar shape of the pad 13 is a circle or a rectangle, and its width is, for example, about 40 to 50 μm. It is possible to form gold plating, nickel plating, or the like on the surface of the pad 13, but in this embodiment, the surface of the pad 13 is not covered with a plating film, and a conductive material such as copper, which is the main material, is exposed. Yes. A solder electrode 14 is attached to the upper surface of the pad 13. Here, the thickness (L6) of the pad 13 is, for example, about 10 μm to 20 μm.

  The underfill 17 is filled in a gap formed at least between the lower surface of the semiconductor element 11 and the upper surface of the mounting substrate 12. The underfill 17 is made of an insulating resin material such as an epoxy resin. By filling the gap between the semiconductor element 11 and the mounting substrate 12 with the underfill 17, it is possible to improve the connection reliability between the two against thermal stress.

  In this embodiment, a plating film that improves solder wettability is not formed on the surface of the pad 13. Thereby, deterioration of the mechanical strength of the solder electrode 14 can be prevented. Furthermore, there is an advantage that the lateral extension of the solder electrode 14 can be suppressed.

  As described in the background art, when the surface of the pad 13 is formed by a plating film formed by an electroless plating method, a large amount of intermetallic compounds are generated, and the mechanical strength of the solder electrode 14 is deteriorated. Will occur. In this embodiment, the solder electrode 14 is in direct contact with the upper surface of the pad 13 where the conductive material is exposed. Accordingly, the solder electrode 14 functions as a connection means for the semiconductor element 11 while maintaining the original mechanical strength, and the occurrence of cracks in the solder electrode 14 is suppressed.

  In particular, when lead-free solder is used as the material for the solder electrode 14, the lead-free solder is inferior in mechanical strength as compared with lead eutectic solder, and furthermore, the content of tin is very large, so that the solder electrode 14 has cracks. Prone to occur. In this embodiment, as described above, the plating film that is formed by the electroless plating method and easily generates an intermetallic compound is not formed on the surface of the pad 13. Therefore, even if the solder electrode 14 is welded to the upper surface of the pad 13, a large amount of intermetallic compound is not generated on the solder electrode 14, so that the strength of the solder electrode 14 made of lead-free solder does not deteriorate.

  Further, the configuration of the present embodiment in which the surface of the pad 13 is not covered with a plating film has an advantage that the solder electrode 14 can be prevented from spreading in the lateral direction and the underfill 17 can be easily filled. Specifically, as described above, the upper surface and the side surface of the pad 13 formed on the mounting substrate 12 are not covered with the plating film, so that the solder wettability is not so good. Therefore, when the solder electrode 14 is welded to the upper surface of the pad 13, the solder electrode 14 adheres only to the upper surface of the pad 13, and the solder electrode 14 does not adhere to the side surface of the pad 13. Further, since the side surface of the post 15 is not covered with the plating film, the upper portion of the solder electrode 14 is attached only to the upper surface of the post 15. As a result, the solder electrode 14 does not swell excessively in a barrel shape, and the spread in the lateral direction is suppressed. As a result, referring to FIG. 1A, the gap between the posts 15 is not blocked by the solder electrode 14 and is sufficiently wide. Thus, the underfill 17 can be easily filled between the posts 15 and between the semiconductor element 11 and the mounting substrate 12.

  Referring to FIG. 1B, the length L2 that the solder electrode 14 protrudes laterally from the terminal portion of the pad 13 is, for example, about 1 μm to 5 μm. On the other hand, when the side surface of the pad 13 is covered with the solder electrode 14, the length L3 that the solder electrode 14 protrudes in the lateral direction is predicted to be about 5 μm to 10 μm, for example. If the solder electrode 14 protrudes excessively in the lateral direction in this way, the width of the gap between the posts 15 decreases, and it becomes difficult to fill the underfill 17, and the underfill 17 is difficult to fill between the semiconductor element 11 and the mounting substrate 12. There is a possibility that an unfilled region (void) that is not filled with the fill 17 is formed.

  Further, the side surface of the pad 13 may be covered with the solder electrode 14, but even in this case, only a part of the side surface of the pad 13 is covered with the solder electrode 14.

  FIG. 2 is a diagram illustrating a state of the solder electrode 14 of the present embodiment. In this figure, the semiconductor element 11, the post 15, the solder electrode 14, the pad 13, and the mounting substrate 12 are shown from the top. As is apparent from this photograph, the solder electrode 14 adheres only to the upper surface of the pad 13 and does not cover the side surface of the pad 13. The same applies to the solder electrode 14 and the post 15. As a result, the space between the posts 15 is not blocked by the solder electrode 14.

  Next, the structure of the semiconductor device 10 will be described in detail with reference to FIG. FIG. 3A is a perspective view showing the semiconductor device 10, and FIG. 3B is a typical sectional view thereof.

  With reference to FIG. 3A, a conductive pattern 19 is formed on the upper surface of the mounting substrate 12, and a large number of circuit elements electrically connected to the conductive pattern 19 are mounted on the mounting substrate 12. As circuit elements mounted on the mounting substrate 12, active elements such as LSIs and transistors, and passive elements such as chip capacitors and chip resistors are generally employed. In this figure, the resin-sealed package 18 and the semiconductor element 11 are mounted on the upper surface of the mounting substrate 12. A side electrode 20 electrically connected to the conductive pattern 19 is formed on the side surface of the peripheral portion of the mounting substrate 12. The side electrode 20 functions as an external connection electrode that electrically connects the semiconductor device 10 and the outside. The side electrode 20 and the outside are connected via a conductive adhesive such as solder.

  Referring to FIG. 3B, the mounting substrate 12 has a multilayer wiring structure composed of four layers of stacked wiring. A semiconductor element 11 and a package 18 are mounted on the uppermost wiring layer. The semiconductor element 11 is flip-chip mounted, and the package 18 is surface mounted via a solder electrode or the like. By forming a multilayer wiring layer in this way, a system that realizes a predetermined function by connecting a large number of circuit elements mounted on the mounting substrate 12 to each other can be incorporated into the semiconductor device 10. For example, a system for processing digital television images can be built in the semiconductor device 10.

  Here, a pad is formed by the uppermost wiring layer, and the semiconductor element 11 is flip-chip mounted on this pad. Then, the post 15 of the semiconductor element 11 is connected to a pad on the mounting substrate 12 side via a solder electrode (not shown). An underfill is filled between the semiconductor element 11 and the mounting substrate 12.

  Next, the configuration of the substrate 24 on which the semiconductor device 10 of this embodiment is mounted will be described with reference to FIG. 4A is a diagram illustrating a state in which the semiconductor device 10 is mounted on the substrate 24, and FIG. 4B is a typical cross-sectional view illustrating a state in which the semiconductor device 10 is mounted on the substrate 24. .

  With reference to FIG. 4A, the mounting substrate 12 on which circuit elements such as the semiconductor element 11 are mounted is attached to the upper surface of the substrate 24.

  A first conductive path 23 and a second conductive path 28 are formed on the front and back surfaces of the substrate 24, and a resin material, ceramic, metal, or the like is employed as a base material (see FIG. 4B). The first conductive path 23 and the second conductive path 28 are electrically connected to each other by a through connection portion 29 that penetrates the substrate 24.

  A circuit element 30 electrically connected to the first conductive path 23 is disposed on the upper surface of the substrate 24. As the circuit element 30, the above-described active element and passive element are employed. Further, a package in which these elements are sealed with resin can be adopted as the circuit element 30.

  The storage unit 25 is a part where the substrate 24 is partially hollowed, and has a size capable of storing a package mounted on the lower surface of the mounting substrate 12. Furthermore, the planar size of the storage portion 25 is smaller than that of the mounting substrate 12. In addition, a pad made of the first conductive path 23 is formed on the upper surface of the substrate 24 near the periphery of the storage unit 25. This pad is connected to the side electrode 20 of the mounting substrate 12 via a fixing material 27 such as solder.

  With reference to FIG. 4B, the package 26 fixed to the back surface of the mounting substrate 12 is stored in a storage portion 25 provided on the substrate 24. By doing so, an increase in thickness can be suppressed and a large number of circuit elements can be mounted.

  Further, the mounting density can be improved without increasing the number of layers of the substrate 24 by adhering the mounting substrate 12 on which the wiring layers formed at a fine pitch are laminated to the substrate 24. For example, the pitch of the conductive patterns 19 formed in multiple layers on the mounting substrate 12 is as very narrow as about 60 μm. On the other hand, the pitch of the 1st conductive path 23 formed in the upper surface of the board | substrate 24 is about 200 micrometers-300 micrometers, for example. For this reason, it is very difficult to directly mount the semiconductor element 11 on which several hundreds of electrodes having a pitch of several tens of μm are formed on the substrate 24. Further, if the first conductive paths 23 on the substrate 24 are formed at a fine pitch in order to directly mount the semiconductor element 11 on the substrate 24, the manufacturing cost is increased. As in this embodiment, the mounting substrate 12 on which the fine pitch conductive pattern 19 is formed is applied only to the portion where the semiconductor element 11 is flip-chiped, thereby suppressing an increase in manufacturing cost and a large number of electrodes. It is possible to indirectly mount the semiconductor element 11 in which is formed on the substrate 24.

  Next, with reference to FIGS. 5 to 8, a method of manufacturing the semiconductor device having the above-described configuration will be described.

  FIG. 5 is a cross-sectional view showing a method of forming a post or the like on a semiconductor element.

  Referring to FIG. 5A, first, a predetermined electrical circuit is formed on the surface of a semiconductor wafer (semiconductor substrate) 40 made of a semiconductor material such as silicon by a known diffusion process. Further, a bonding electrode 16 electrically connected to an electric circuit formed on the semiconductor wafer 40 is formed on the surface (here, the lower surface) of the semiconductor wafer 40.

  In this step, the Ti layer 41 and the seed layer 42 are formed over the entire lower surface of the semiconductor wafer 40 on which the bonding electrodes 16 are formed by using a method of depositing a metal such as an electroless plating method. The Ti layer 41 is a layer provided to prevent another layer made of copper from diffusing into the bonding electrode 16 made of, for example, aluminum, and has a thickness of about several μm. The seed layer 42 is a metal film made of copper having a thickness of about several μm, for example, and is formed so as to cover substantially the entire surface of the Ti layer 41. The seed layer 42 functions as an electrode for forming a post or the like by an electrolytic plating method in a later process.

  Next, a plating resist 43 is selectively formed on the surface of the seed layer 42. Specifically, the plating resist 43 is formed so as to cover the seed layer 42 in a region excluding a portion where a post is formed in a later step.

  Referring to FIG. 5B, next, post 15 is formed by performing electroplating using seed layer 42 as a common electrode. The post 15 is provided corresponding to the position of each bonding electrode 16 and is made of a metal whose main material is copper having a thickness of about 20 μm to 30 μm. Thus, since the post 15 is formed by the electrolytic plating method, even if these portions are in contact with the solder electrode, the intermetallic compound is not generated so much. Further, in order to improve the wettability of the solder, a nickel film having a thickness of about several μm may be formed on the lower surface of the post 15 by electrolytic plating.

  Referring to FIG. 5C, next, a solder electrode 14 is formed on the lower surface of the post 15 by an electrolytic plating method. As the material of the solder electrode 14, both lead eutectic solder or lead-free solder can be used. For example, Sn / Pb, Sn / Ag, Sn / Ag / Cu, Sn / Bi, Sn / Cu, Sn / P Zn, Sn / Zn / Bi, etc. can be employed. Since the solder electrode 14 is formed by an electrolytic plating method, a harmful intermetallic compound is hardly generated.

Referring to FIGS. 5D and 5E, after removing the plating resist 43 by peeling,
The Ti layer 41 and the seed layer 42 located between the posts 15 are removed. The Ti layer 41 and the seed layer 42 are partially removed by wet etching using an etching resist (not shown) as a mask so as to cover the post 15 and the solder electrode 14. As a result, the posts 15 are electrically separated.

  After the above process is completed, the semiconductor wafer 40 is separated into each semiconductor element by a one-dot chain line shown in FIG.

  Next, a method for manufacturing a mounting substrate on which the semiconductor element manufactured in the above-described process is mounted will be described with reference to each cross-sectional view of FIG.

  Referring to FIG. 6A, first, conductive films 45 and 46 made of a metal such as copper are laminated on the front and back surfaces of the interlayer insulating film 44. Here, the thickness of the interlayer insulating film 44 is about 60 μm, and a filler or glass cloth is mixed in a thermoplastic resin or a thermosetting resin. The thickness of the conductive films 45 and 46 is, for example, about 10 μm.

  Referring to FIG. 6B, next, the second conductive pattern 47 and the third conductive pattern 48 are formed by selectively etching the conductive films 45 and 46. The second conductive pattern 47 and the third conductive pattern 48 are connected at a predetermined location by a through connection portion 55 that penetrates the interlayer insulating film 44. The through-connecting portion 55 can be formed by removing the conductive film and the interlayer insulating film 44 at predetermined locations to form a through-hole, and then forming a plated film in the through-hole.

  Referring to FIG. 6C, next, a conductive film 51 is laminated through an interlayer insulating film 49 formed so as to cover the second conductive pattern 47. Further, a conductive film 52 is laminated via an interlayer insulating film 50 formed so as to cover the third conductive pattern 48. Further, in a region corresponding to the peripheral portion of the mounting substrate to be formed, a through hole 56 penetrating each conductive film and insulating film is formed by a drill or the like. This through hole 56 becomes the side electrode 20 shown in FIG.

  Referring to FIG. 6D, next, a through connection portion 55 penetrating the interlayer insulating film 49 is formed, and the conductive film 51 and the second conductive pattern 47 are connected at a predetermined location. Further, the conductive film 52 and the third conductive pattern 48 are connected to each other through a through connection portion 55 formed so as to penetrate the interlayer insulating film 50. Further, in the step of forming the through connection portion 55 by plating, the side electrode 20 made of a metal film is also formed on the inner wall of the through hole 56.

  Referring to FIG. 6E, next, the first conductive pattern 53 and the fourth conductive pattern 54 are formed by selectively etching the conductive film 51 and the conductive film 52.

  With reference to FIG. 6F, next, the uppermost first conductive pattern 53 and the lowermost fourth conductive pattern 54 are covered with a resist 57. The first conductive pattern 53 and the fourth conductive pattern 54 that are connected to the circuit element are exposed from the resist 57.

  Through the above steps, a mounting substrate having a four-layer wiring structure formed at a fine pitch is manufactured. Here, the number of layers of the conductive pattern is adjusted according to the required complexity and scale of the circuit, and may be 3 layers or less or 5 layers or more.

  Next, referring to FIG. 7, the semiconductor element 11 is flip-chip mounted on the mounting substrate 12.

  Referring to FIG. 7A, first, the semiconductor element 11 is placed on the upper surface of the mounting substrate 12 with the surface on which the post 15 is formed as the lower surface. A pad 13 made of a conductive pattern formed on the uppermost layer of the mounting substrate 12 is formed on the upper surface of the mounting substrate 12. The position of the pad 13 accurately corresponds to the post 15 of the semiconductor element 11.

  Here, in general, when performing fine solder connection using solder, an electroless plating film made of, for example, nickel or gold is formed on the surface of the pad 13, but in this embodiment, the pad 13 is plated. Not covered by membrane. The conductive material constituting the pad 13 is exposed on the surface of the pad 13. By not forming the electroless plating film on the surface of the pad 13, it is possible to prevent an intermetallic compound from being formed on the solder electrode 14 to be welded to the upper surface of the pad 13 in a later step. As a result, it is possible to prevent the solder electrode 14 from being destroyed due to the generation of a large amount of intermetallic compounds.

  A water-soluble or rosin-based flux 58 is applied to the upper surface of the pad 13. As described above, since the surface of the pad 13 is not covered with the plating film, the surface of the pad 13 may be slightly inferior in solder wettability. Adoption of the flux 58 improves the wettability of the solder of the pad 13 and improves the adhesion strength between the solder electrode 14 and the pad 13. Here, the flux 58 may be prepared by adhering to the lower surface of the solder electrode 14 on the semiconductor element 11 side, or may be prepared by adhering to the pad 13 on the mounting substrate 12 side.

  Furthermore, a metal containing copper may be employed as the material of the solder electrode 14. For example, solder having a composition of Sn-3Ag-0.5Cu can be used as the material of the solder electrode 14. When the solder electrode 14 contains copper, a barrier film containing copper is formed when the solder electrode 14 is melted, and the formation of the intermetallic compound can be suppressed by this barrier film. In particular, in the case of the fine solder electrode 14 used for flip chip mounting as in this embodiment, the strength deterioration of the solder electrode 14 due to the formation of the intermetallic compound is increased, and therefore the solder electrode 14 is made of copper. It is very effective to prevent the generation of cracks by containing the intermetallic compound.

  With reference to FIG. 7B, the external atmosphere is heated to, for example, 200 ° C. to 300 ° C. by the reflow process in a state where the semiconductor element 11 is mounted on the mounting substrate 12. As a result, the solder electrode 14 is melted, and the semiconductor element 11 is flip-chip mounted on the mounting substrate 12.

  As described above, since the amount of harmful intermetallic compounds produced is small in this step, the solder electrode 14 having excellent mechanical strength and high connection reliability against external forces such as thermal stress can be obtained. The details of the solder electrode 14 formed by this process have been described with reference to FIG.

  Further, since the surface of the pad 13 is not covered with the plating film, the solder electrode 14 adheres only to the upper surface of the pad 13. Therefore, the side surface of the solder electrode 14 does not swell excessively in the lateral direction, and the gap between the posts 15 is not blocked by the solder electrode 14. Thus, a sufficient gap between the posts 15 is ensured, and formation of an underfill, which is a later process, is facilitated.

  Next, referring to FIG. 7C, an underfill 17 is filled between the semiconductor element 11 and the mounting substrate 12. The underfill 17 is made of, for example, a resin material such as an epoxy resin, is filled between the semiconductor element 11 and the mounting substrate 12, and further covers the side surface of the semiconductor element 11. In this embodiment, since the pad 13 is not covered with the plating film, the lateral extension of the solder electrode 14 is suppressed, and a sufficient gap between the posts 15 is secured. Therefore, even if the pitch between the posts 15 is as narrow as several tens of μm, the underfill 17 can be easily filled from between the posts 15. For this reason, the space between the semiconductor element 11 and the mounting substrate 12 is filled with the underfill 17, and an unfilled region (void) that is not filled with the underfill 17 is not formed. As a result, the connection reliability between the semiconductor element 11 and the mounting substrate 12 can be improved.

  In this step, in addition to the semiconductor element 11 to be flip-chip mounted, other circuit elements to be mounted are mounted on the mounting substrate 12.

  Referring to FIG. 8, next, the mounting substrate 12 is obtained by cutting the interlayer insulating film and the like laminated at the locations indicated by the dotted lines. Further, since the mounting substrate 12 is separated at the place where the through hole 56 is formed, the side electrode 20 is exposed to the side surface of the mounting substrate 12. This separation can be performed by separation using a router or dicing.

  As shown in FIG. 4, the mounting substrate 12 manufactured by the above-described process is attached to the surface of the substrate 24 via a fixing material such as solder. Here, the circuit elements are mounted only on one side of the mounting board 12, but the circuit elements can also be mounted on both sides of the mounting board 12.

1A is a cross-sectional view of a semiconductor device according to the present invention, and FIG. It is a figure which shows the image which image | photographed the cross section of the semiconductor device of this invention. 1A and 1B are diagrams illustrating a semiconductor device of the present invention, in which FIG. It is a figure which shows the manufacturing method of the semiconductor device of this invention, (A) is a perspective view, (B) is sectional drawing. It is a figure which shows the manufacturing method of the semiconductor device of this invention, and (A)-(E) is sectional drawing. It is a figure which shows the manufacturing method of the semiconductor device of this invention, and (A)-(F) is sectional drawing. It is a figure which shows the manufacturing method of the semiconductor device of this invention, and (A)-(C) is sectional drawing. It is sectional drawing which shows the manufacturing method of the semiconductor device of this invention. It is a figure which shows the manufacturing method of the conventional semiconductor device, (A)-(C) is sectional drawing. It is a figure which shows the image which image | photographed the cross section of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Semiconductor element 12 Mounting board 13 Pad 14 Solder electrode 15 Post 16 Bonding electrode 17 Underfill 18 Package 19 Conductive pattern 20 Side electrode 23 Conductive path 24 Substrate 25 Storage part 26 Package 27 Fixing material 28 Second conductive path 29 Through Connection part 30 Circuit element 40 Semiconductor wafer 41 Ti layer 42 Seed layer 43 Plating resist 44 Interlayer insulating film 45, 46 Conductive film 47 Second conductive pattern 48 Third conductive pattern 49, 50 Interlayer insulating film 51, 52 Conductive film 53 First Conductive pattern 54 Fourth conductive pattern 55 Through-connection portion 56 Through-hole 57 Resist 58 Flux

Claims (11)

A semiconductor element flip-chip mounted with a large number of electrodes on one main surface;
A conductive pattern provided at a position corresponding to the electrode of the semiconductor element and electrically connected to the electrode;
The semiconductor device, wherein the electrode of the semiconductor element and the conductive pattern are connected via a solder electrode that is in direct contact with the conductive pattern. A plurality of electrodes protruding in the thickness direction provided on one principal surface and flip-chip mounted semiconductor elements;
A conductive pattern provided on the mounting substrate corresponding to the position of the electrode of the semiconductor element and electrically connected to the electrode;
Comprising a filling resin filled between the semiconductor element and the mounting substrate;
The semiconductor device, wherein the electrode of the semiconductor element and the conductive pattern are connected via a solder electrode that is in direct contact with the conductive pattern.   The semiconductor device according to claim 1, wherein the solder electrode is in contact with only an upper surface of the conductive pattern.   The semiconductor device according to claim 1, wherein the solder electrode is in contact with a part of the upper surface and the side surface of the conductive pattern.   The semiconductor device according to claim 1, wherein the solder electrode is made of lead-free solder.   3. The semiconductor device according to claim 1, wherein the solder electrode is formed by electrolytic plating. Preparing a semiconductor element comprising an electrode protruding in the thickness direction;
Connecting the electrode of the semiconductor element to a conductive pattern by flip-chip connection via a solder electrode;
A method for manufacturing a semiconductor device, comprising: electrically connecting the electrode and the conductive pattern via the solder electrode that is in direct contact with the conductive pattern. In the step of connecting the electrode to the conductive pattern, the electrode of the semiconductor element is connected to the conductive pattern formed on the mounting substrate,
8. The method of manufacturing a semiconductor device according to claim 7, wherein a filling resin is filled between the semiconductor element and the mounting substrate. The solder electrode is attached only to the upper surface of the conductive pattern to suppress lateral spread of the solder electrode,
9. The method of manufacturing a semiconductor device according to claim 8, wherein the filling resin is filled between the semiconductor element and the mounting substrate through a gap between the electrodes.   The solder electrode formed at the tip of the electrode of the semiconductor element is brought into contact with the conductive pattern through a flux, and then the solder electrode is melted to connect the electrode and the conductive pattern. The method of manufacturing a semiconductor device according to claim 7.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the electrode and the solder electrode are formed by an electrolytic plating method.

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