TWI498982B - Semiconductor device and method of confining conductive bump material during reflow with solder mask patch - Google Patents

Description

Semiconductor device and method for confining conductive bump material during reflow soldering with solder mask patch

This invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods that confine conductive bump material during reflow soldering with solder masks.

Semiconductor devices are commonly found in modern electronic generation. The number and density of electrical components of a semiconductor device can vary. Discrete semiconductor devices typically include a form of electrical components such as light emitting diodes (LEDs), small signal transistors, resistors, capacitors, inductors, and power metal oxide semiconductor field effect transistors (MOSFETs). Integrated semiconductor devices typically include hundreds to millions of electrical components. Examples of integrated semiconductor devices include: microcontrollers, microprocessors, charge coupled devices (CCDs), solar cells, and digital micromirror devices (DMDs).

Semiconductor devices implement a wide range of functions, such as: high speed computing, transmitting and receiving electromagnetic signals, controlling electronics, converting sunlight into electricity, and producing visual projections for television displays. Semiconductor devices can be found in the fields of entertainment, communications, power conversion, networking, computers, and consumer products. Semiconductor devices can also be found in military applications, aerospace, automotive, industrial controllers, and office equipment.

Semiconductor devices use the electrical properties of semiconductor materials. The atomic structure of the semiconductor material allows its conductivity to be manipulated by applying an electric or base current, or via a doping process. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.

Semiconductor devices include active and passive electrical structures. The active structure includes a bipolar transistor and a field effect transistor that controls the flow of current. The transistor can enhance or limit the flow of current by changing the level of doping and applying an electric field or base current. Passive structures include: resistors, capacitors, and inductors that create a relationship between the voltage and current of the various desired electrical functions implemented. These passive and active structures are electrically connected to form a circuit that enables the semiconductor device to perform high speed calculations and other useful functions.

Two complex manufacturing processes are typically used to fabricate semiconductor devices, namely front-end manufacturing processes and back-end manufacturing processes, each of which may involve hundreds of steps. The front end manufacturing process involves forming a plurality of dies on the surface of the semiconductor wafer. Each die is typically identical and includes circuitry formed by electrically connecting active and passive components. The back-end manufacturing process involves singulating the completed wafer into individual dies and packaging the dies to provide structural support from the environment.

One of the goals of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be manufactured more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller grain size can be achieved by improving the front end manufacturing process to result in a die having smaller size and higher density active and passive components. The back end manufacturing process can result in a semiconductor device package with a small footprint by improving electrical interconnections and packaging materials.

1 and 2 illustrate cross-sectional and top views of a portion of a flip-chip semiconductor die 10 and interconnects or bumps 12 that are metallurgically and electrically connected between the bump pads 18, and It is formed on the substrate 30 and formed on the semiconductor die 10 and the traces 20 and 22. Traces 22 are routed on substrate 30 between trace 20 and bumps 12. Traces 20 and 22 are electrical signal conductors with selective bump pads for mating to bumps 12-14. Solder mask 26 covers traces 20 and 22. A solder mask or registration opening (SRO) 28 is formed over the substrate 30 to expose traces 20 and 22. The SRO 28 limits the conductive bump material on the bump pads of the traces 20 and 22 during reflow and prevents the molten bump material from entering the trace, which can result in an electrical short to adjacent structures. The SRO 28 is made larger than the trace or bump pad. The SRO 28 is typically circular and made as small as possible to reduce the spacing between the traces 20 and 22 and increase routing density.

With a typical design rule, the minimum escape spacing of trace 30 is defined as P = (1.1D + W) / 2 + L, where D is the bump base diameter, W is the trace width, and L is the SRO A strip-like spacing from adjacent structures. Use ±30 micron (μm) solder registration design rule, D is 100μm, W is 20μm, L is 30μm, then the minimum separation pitch of traces 30-34 is defined as (1.1*100+20)/2+30=95μm . The SRO 28 around the bump pads limits the separation pitch and routing density of the semiconductor die.

There is currently a need to minimize the separation spacing of traces for higher routing densities.

Accordingly, in one embodiment, the present invention is a method of fabricating a semiconductor device comprising the steps of: providing a semiconductor die having a die bump pad; providing a substrate having traces of integrated bump pads a solder mask patch having a gap disposed between the die bump pads or between the integrated bump pads; depositing the conductive bump material on the integrated bump pads or die bump pads; The die is mounted on the substrate such that the conductive bump material is disposed between the die bump pad and the integrated bump pad; and the conductive bump material is reflowed without a solder mask around the integrated bump pad, and An interconnection is formed between the semiconductor die and the substrate. This solder mask patch confines the conductive bump material to the footprint of the die bump pad or integrated bump pad during reflow.

In another embodiment, the invention is a method of fabricating a semiconductor device comprising the steps of: providing a first semiconductor structure having a first bump pad; providing a second semiconductor structure having a second bump a pad; a solder mask patch is formed between the first bump pads or between the second bump pads; depositing a conductive bump material between the first and second bump pads; The structure is mounted on the second semiconductor structure such that the conductive bump material is disposed between the first bump pad and the second bump pad; and the conductive bump material is reflowed, and the first and second bump pads are There is no solder mask around to form the interconnect. During solder reflow, the solder mask patch confines the conductive bump material to the footprint of the first bump pad or the second bump pad.

In another embodiment, the present invention is a method of fabricating a semiconductor device, comprising the steps of: providing a substrate having traces having integrated bump pads; forming a solder mask patch between the integrated bump pads; A conductive bump material is deposited on the integrated bump pad; and the conductive bump material is reflowed without a solder mask around the integrated bump pad to form an interconnect. This solder mask patch confines the conductive bump material to the footprint of the integrated bump pad during reflow.

In another embodiment, the invention is a semiconductor device comprising: a semiconductor die having a first bump pad and a substrate, the substrate having a second bump pad. A solder mask patch is formed between the first bump pads or between the second bump pads. An interconnect is formed between the first and second bump pads by reflowing the conductive bump material without a solder mask around the second bump pads. The solder mask patch confines the conductive bump material to the first bump pad and the second bump pad.

The invention is described in the following one or more embodiments with reference to the accompanying drawings, in which The present invention has been described in terms of the best mode for achieving the objectives of the present invention, and it is understood by those skilled in the art that it is intended to include various alternatives, modifications, and equivalents. The scope of the invention and its equivalents are defined by the spirit and scope of the invention, and are supported by the following disclosure and drawings.

Two complex manufacturing processes are typically used to fabricate semiconductor devices: front-end manufacturing processes and back-end manufacturing processes. The front end manufacturing process involves forming a plurality of dies on the surface of the semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components are, for example, transistors and diodes that have the ability to control the flow of current. Passive electrical components are, for example, capacitors, inductors, resistors, and transformers that create a relationship between the voltage and current at which the desired circuit function is implemented.

These passive and active components are formed on the surface of the semiconductor wafer by a series of process steps. These steps include: doping, deposition, lithography, etching, and planarization. Doping is introduced into the semiconductor material by, for example, ion implantation or thermal diffusion techniques. This doping process can change the conductivity of the semiconductor material in the active device, convert the semiconductor material into an insulator, an electrical conductor, or dynamically change the conductivity of the semiconductor material in response to an electric field or base current. The transistor includes a region of varying pattern and doping level that is configured as desired such that the transistor can enhance or limit the flow of current when an electric or base current is applied.

Active and passive components can be formed from layers of material having different electrical properties. These layers can be formed by a variety of deposition techniques, the technology being determined in part by the type of material being deposited. For example, thin film deposition may involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolyte plating, and electrodeless plating processes. The layers are typically patterned to form: active components, passive components, or portions of electrical connections between components.

These layers can be patterned using lithography, which involves depositing a light sensitive material such as a photoresist on the patterned layer. Use light to move the pattern from the reticle to the photoresist. A portion of the photoresist pattern that is illuminated by the light is removed using a solvent to expose portions of the patterned lower layer. The remaining portion of the photoresist is removed to leave a patterned layer. Alternatively, some type of material may be patterned using, for example, electrodeless and electrolyte plating techniques by depositing material directly into regions or holes formed by previous deposition/etching processes.

Depositing the film material onto an existing pattern enlarges the underlying pattern and produces a non-uniform flat surface. A uniform flat surface is often required to produce active and passive components that are smaller in size and more densely packaged. Planarization can be used to remove material from the wafer surface to create a uniform flat surface. Flattening involves polishing the surface of the wafer with a polishing pad. Abrasive materials and corrosive chemicals are added to the wafer surface during polishing. The combination of the mechanical action of the grinding and the corrosive action of the chemical removes any irregularities on the surface of the wafer to create a uniform flat surface.

The back-end manufacturing process refers to cutting or singulation of the completed wafer into individual dies, and then using these die packages for structural support and environmental isolation. To singulate the grain, the wafer is scribed and separated along a non-functional area of the wafer called a saw or scribe. The wafer is singularized using a laser cutting tool or a saw blade. After singulation, individual dies are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor die are then attached to the contact pads in the package. This electrical connection can be made of solder bumps, stud bumps, conductive paste or wiring. A sealant or other molding material is deposited on the package to provide physical support and electrical isolation. This completed package is then inserted into an electrical system and the semiconductor device functionality is made available to other system components.

3 illustrates an electronic device 50 having a wafer carrier substrate or printed circuit board (PCB) 52 having a plurality of semiconductor packages mounted on a surface thereof. Depending on the application, the electronic device 50 can have a type of semiconductor package or a plurality of types of semiconductor packages. For purposes of illustration, different types of semiconductor packages are shown in FIG.

The electronic device 50 can be a stand-alone system that uses a semiconductor package to implement one or more electrical functions. Alternatively, electronic device 50 can be a secondary component of a larger system. For example, the electronic device 50 is a graphics card, a network interface card, or other signal processing card that can be inserted into a computer. Semiconductor packages may include microprocessors, memories, special purpose integrated circuits (ASICs), logic circuits, analog circuits, radio frequency (RF) circuits, discrete devices, or other semiconductor die or electrical components.

In FIG. 3, PCB 52 provides a general substrate for mounting mechanical and electrical interconnections of semiconductor packages on the PCB. Conductive signal traces 54 are formed on or in the surface of PCB 52 using evaporation, electrolyte plating, electroless plating, screen printing, or other suitable metal deposition process.

Signal traces 54 provide electrical communication between the various semiconductor packages, mounting components, and other external system components. Trace 54 also provides power and ground connections to the various semiconductor packages.

In some embodiments, the semiconductor device has two package levels. The first quasi-package is a technique for mechanically and electrically attaching a semiconductor die to an intermediate carrier. The second level of packaging is about mechanically and electrically attaching the intermediate carrier to the PCB. In other embodiments, the semiconductor device has only a first level of package and the die is mechanically and electrically mounted directly to the PCB.

For illustrative purposes, several types of first level packages, including a wiring package 56 and a flip chip 58, are shown on the PCB 52. In addition, several types of second level packages are shown on the PCB 52, including: a ball grid array (BGA) 60, a bump wafer carrier (BCC) 62, a dual inner package (DIP) 64, and a planar grid array ( LGA) 66, multi-chip module (MCM) 68, quad flat no-sleeve package (QFN) 70, and quad flat pack 72. Depending on system requirements, any combination of semiconductor packages can be configured in any combination of the first and second level of packaged patterns to be coupled to PCB 52 along with other electronic components. In some embodiments, electronic device 50 includes a single attached semiconductor package, while other embodiments require multiple interconnect packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functions, less expensive components and rationalized processes can be used to fabricate electronic devices. The resulting device is less likely to fail and is less expensive to manufacture, resulting in lower costs for the consumer.

Figures 4a-4d show a typical semiconductor package. Figure 4a illustrates further details of the DIP 64 mounted on the PCB 52. The semiconductor die 74 includes an active region including an analog or digital circuit that functions as an active device, a passive component, a conductive layer, and a dielectric layer formed in the die, and electrically interconnected according to the electrical design of the die. even. For example, the circuit can include: one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed in the active region of the semiconductor die 74. The contact pad 76 is one or more layers of conductive materials, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au) or silver (Ag), and is electrically connected to Circuit elements in semiconductor die 74. The semiconductor die 74 is mounted to an intermediate carrier 78 during assembly of the DIP 64 using a gold-germanium eutectic layer or an adhesive material such as a thermal epoxy. The package includes an insulating encapsulation material such as a polymer or ceramic. Conductor 80 and wiring 82 provide electrical interconnection between semiconductor die 74 and PCB 52. The encapsulant 84 is deposited on the package to protect the environment by preventing moisture and particles from entering the package and contaminating the die 74 or wiring 82.

Figure 4b illustrates further details of the BCC 62 mounted on the PCB 52. The semiconductor die 88 is mounted on the carrier 90 using an underfill or epoxy bonding material 92. Wiring 94 provides a first level of package interconnection between contact pads 96 and 98. A molding compound or encapsulant 100 is deposited over the semiconductor die 88 and the wiring 94 to provide physical and electrical isolation for the device. The contact pads 102 are formed on the surface of the PCB 52 using a suitable metal deposition process such as an electrolyte plating or an electrodeless plating process to prevent oxidation. Contact pad 102 is electrically coupled to one or more conductive signal traces 54 in PCB 52. A bump 104 is formed between the contact pad 98 of the BCC 62 and the contact pad 102 of the PCB 52.

In FIG. 4c, the semiconductor die 58 is face down and mounted to the intermediate carrier 106 in a flip chip pattern first level package. The active region 108 of the semiconductor die 58 includes an analog or digital circuit that is implemented as an active device, a passive component, a conductive layer, and a dielectric layer formed according to the die electrical design. For example, the circuit can include: one or more transistors, diodes, inductors, capacitors, resistors, and other circuit components in the active region 108. Semiconductor die 58 is electrically and mechanically coupled to carrier 106 via bumps 110.

The bumps 112 are used to electrically and mechanically connect the BGA 60 to the PCB 52 in a BGA type second level package. Semiconductor die 58 is electrically coupled to conductive signal traces 54 in PCB 52 via bumps 110, signal lines 114, and bumps 112. A molding compound or encapsulant 116 is deposited over the semiconductor die 58 and the carrier 106 to provide physical and electrical isolation for the device. The flip chip semiconductor device provides a short conductive path from the active device on the semiconductor die 58 to the conductive traces on the PCB 52 to reduce signal transmission distance, reduce capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die 58 can be electrically and mechanically directly connected to the PCB 52 using a flip chip type first level package without the intermediate carrier 106.

In another embodiment, the active region 108 of the semiconductor die 58 is mounted directly down to the PCB 115, i.e., without an intermediate carrier, as shown in Figure 4d. A bump pad 111 is formed on the active region 108 using evaporation, electrolyte plating, electroless plating, screen printing, or other suitable metal deposition process. The bump pads 111 are connected to the active and passive circuits by conductive tracks in the active region 108. The bump pad 111 may be aluminum (Al), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or copper (Cu). Conductive bump material is deposited on bump pads 111 or conductive tracks 118 in PCB 115 using evaporation, electrolyte plating, electroless plating, ball drop or screen printing processes. The bump material may be aluminum (Al), tin (Sn), nickel (Ni), gold (Au), silver (Ag), lead (Pb), copper (Cu), bismuth (Bi), solder, and combinations thereof. And a selective flux material. For example, the bump material can be eutectic Sn/Pb, high lead solder, or lead free solder. The bump material is bonded between the die bump pads 111 on the PCB 115 and the conductive tracks 118 using a suitable attach or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a sphere or bump 117. The flip-chip semiconductor device provides a short conductive path from the active components on the semiconductor die 58 to the conductive traces 118 on the PCB 115 to reduce signal transfer, reduce capacitance, and achieve overall better circuit performance.

FIG. 5 illustrates a cross-sectional view of a portion of a flip-chip semiconductor die 120 having bump pads 122. Traces 130 and 132 are formed on substrate 136. As shown in Figure 6a, traces 130 and 132 are straight electrical conductors with integrated bump pads 138. This integrated bump pad 138 is collinear with traces 130 and 132. Alternatively, traces 130 and 132 may have a circular integrated bump pad 139, as shown in Figure 6b, or a rectangular integrated bump pad 140, as shown in Figure 6c. This integrated bump pad is typically placed in an array to achieve maximum interconnect density and capacity.

In FIG. 7, a solder mask 142 is deposited over one of the traces 130 and 132. However, the solder mask 142 is not formed on the integrated bump pad 138. Therefore, there is no SRO for each bump pad on the substrate, as found in the prior art of Figure 2. In the array of integrated bump pads 138, i.e., between adjacent bump pads, a solder mask patch 144 that is not wet is formed over the substrate 136. A solder mask patch may also be formed on the semiconductor die 10 in an array of die bump pads 122. More generally, in any configuration, the solder mask patch is formed very close to the integrated bump pads to avoid outflow to the less wet regions. FIG. 8 shows the bumps 150 and 152 formed on the integrated bump pads 138 and is limited by the solder mask patch 144.

The conductive bump material can be deposited on the die bump pads 122 or the integrated bump pads 138 using evaporation, electrolyte plating, electroless plating, ball drop or screen printing processes. The bump material may be aluminum (Al), tin (Sn), nickel (Ni), gold (Au), silver (Ag), lead (Pb), bismuth (Bi), copper (Cu), solder, and combinations thereof. And a selective flux solution. For example, the bump material can be eutectic Sn/Pb, high lead solder, or lead free solder. The bump material is bonded to the integrated bump pad 138 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spheres or bumps 150 and 152. In some applications, the bumps 150 and 152 are reflowed a second time to improve electrical contact to the die bump pads 122 and the integrated bump pads 138. The bumps can also be squeeze bonded to the die bump pads 122 and the integrated bump pads 138. Bumps 150 and 152 represent a form of interconnect structure that can be formed on integrated bump pads 138. This interconnect structure can also use stud bumps, microbumps, or other electrical interconnects.

In high routing density applications, it is desirable to minimize the separation spacing. To reduce the spacing between traces 130 and 132, the bump material is reflowed without a solder mask around the integrated bump pads 138. The reduction in the spacing between the traces 130 and 132 can be achieved by removing the solder mask used to limit solder reflow and the associated SRO around the integrated bump pads, ie, without a solder mask. The bump material is reflowed. Solder mask 142 may be formed on portions of traces 130 and 132 and substrate 136 away from integrated bump pads 138, as shown in FIG. However, the solder mask 142 may not be formed on the integrated bump pad 138. That is, this portion of the traces 130 and 132 that are designed to mate with the bump material does not form an SRO in the solder mask 142.

In addition, a solder mask patch 144 is formed over the substrate 136 in an array of integrated bump pads 138. This solder mask patch 144 is a non-wettable material. This solder mask patch 144 may be the same material as the solder mask 142 and coated during the same processing step; or may be a different material than the solder mask 142, but coated during different processing steps. The solder mask patch 144 can be formed by selective oxidation, electroplating, or other processing of portions of the traces or pads in the array of integrated bump pads 138. The solder mask patch 144 limits solder flow to the integrated bump pads 138 and prevents conductive bump material from leaking into adjacent structures.

When the bump material is reflowed with the solder mask patch 144 disposed in the gap of the integrated bump pad 138, the wetting and surface tension cause the bump material to be confined and retained: the die bump pad 122, integration The bump pads 138, and the spaces directly adjacent portions of the substrate 136 of the traces 130 and 132, are substantially in the footprint of the integrated bump pads 138.

To achieve the desired limiting properties, the bump material can be immersed in the flux solution to selectively cause the bump material to be placed on the die bump pad 122 or the integrated bump pad 138. The area of contact of the block material is more wet than the area around traces 130 and 132. Due to the wettable nature of the flux solution, the molten bump material remains substantially confined to the area defined by the bump pads. This bump material does not flow to the less wettable area. Here, the bump material does not form a thin oxide layer or other insulating layer on the region where the region is less wet. Therefore, no solder mask 142 is required around the die bump pad 122 or the integrated bump pad 138.

Since the SRO is not formed around the die bump pad 122 or the integrated bump pad 138, the traces 130 and 132 can be formed at a finer pitch, that is, the traces 130 and 132 can be placed closer to the adjacent structure without Contact and form an electrical short. Assuming the same solder registration design rule, the distance between traces 130 and 132 is given as P = (1.1D + W) / 2, D is the bottom diameter of bumps 150 - 152, and W is the trace The width of 130 and 132. In one embodiment, given a bump diameter of 100 μm and a trace width of 20 μm, the minimum separation spacing of the traces 130 and 132 is 65 μm. As is found in the prior art, this bump formation eliminates the need for ligament spacing of the solder mask material between adjacent openings to the minimum soluble SRO.

In another embodiment, a composite interconnect is formed between the die bump pads and the integrated bump pads to achieve the desired bump material. In Figures 9a-9b, the composite bump 160 has a non-fusible portion 162 and a fusible portion 164. The non-fusible portion 162 forms part of the larger composite bump 160 than the fusible portion 164. This non-fusible portion 162 is secured to the contact pads or interconnect locations 166 of the semiconductor die 168. The fusible portion 164 is disposed on the wire or trace 170 on the substrate 172 of Figure 9a and is in physical contact with the wire 170 for reflow. As shown in Figure 9b, the fusible portion 164 collapses around the wire 170 during reflow due to heat or applied pressure. This non-meltable portion 162 does not melt or deform during reflow and maintains its original form and shape. The size of the non-fusible portion 162 can be designed to provide a separation distance between the semiconductor die 168 and the substrate 172. A coating such as a copper organic solderable preservative (OSP) can be applied to the substrate 172. A molded bottom material 174 is deposited between the semiconductor die 168 and the substrate 172 to fill the gap between the die and the substrate.

The non-fusible portion 162 and the fusible portion 164 of the composite bump 160 are made of different bump materials. The non-meltable portion 162 can be gold, copper, nickel, high lead solder or lead tin alloy. The fusible portion 164 can be tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or other tin alloy with silver, copper, or lead.

The height or volume of the fusible bump material relative to the non-fusible base material is selected to ensure that it is limited by surface tension. During reflow, the fusible substrate material is confined around the non-fusible substrate material due to solder mask patching. The fusible bump material around the non-meltable substrate also maintains the die placement during reflow. Typically, the height of the composite interconnect is less than or equal to the diameter of the bump. In some cases, the height of the composite interconnect is greater than the diameter of the interconnect. In one embodiment, given that the bump base has a diameter of 100 μm, the non-meltable substrate has a height of about 45 μm, and the fusible cover has a height of about 35 μm. This molten bump material remains substantially confined in the area defined by the bump pads due to the solder mask patch and because of the volume of bump material that is deposited to form the composite bumps. The composite bump includes: a non-meltable base and a fusible cover, and the composite bump is selected such that the surface tension generated is sufficient to substantially retain the bump material in the occupied space of the bump pad and prevent it from flowing out to the desired Necessary area. Therefore, a solder mask patch having an array of bump pads is formed in a gap to reduce the trace pitch and increase the routing density.

During the reflow process, a large number (e.g., thousands) of composite bumps 160 on the semiconductor die 168 are attached to interconnect locations on the trace 170 of the substrate 172. Some of the tabs 160 may not be properly attached to the substrate 172, particularly if the die 168 is warped. Recall that the composite bump 160 is larger than the trace 170, with the appropriate force applied, the meltable portion 164 around the trace 170 deforms or protrudes, and the composite bump 160 is mechanically locked to the substrate 172. This mechanical interlock is due to the fact that the fusible portion 164 is softer than the trace 170. During reflow, this mechanical interlock between the composite bump 160 and the substrate 172 holds the bump to the substrate, i.e., the bump does not lose contact with the substrate. Therefore, the composite bump 160 is paired with the substrate 172 to reduce the bump connection failure.

In another embodiment, the composite interconnect between the die bump pads and the integrated bump pads is tapered. As shown in Figures 10a-10d, the composite bump 180 has a non-fusible portion 182 and a fusible portion 184. The non-fusible portion 182 forms part of the larger composite bump 180 than the fusible portion 184. This non-fusible portion 182 is secured to the contact pads or interconnect locations 186 of the semiconductor die 188. The fusible portion 184 is disposed on a wire or trace 190 on the substrate 192 and is in physical contact with the wire 190 for reflow. The composite bump 180 is tapered toward the trace 190, i.e., the composite bump has a domed shape that is longer along the length of the trace 190 and narrower across the trace 190. The tapered portion of the composite bump 180 is created along the length of the trace 190. The tapered portion that is collinearly narrowed with the trace 190 is shown in Figure 10a. Figure 10b is perpendicular to Figure 10a and shows the longer portion of the domed composite bump 180. As shown in Figures 10c and 10d, the fusible portion 184 collapses around the wire 190 during reflow due to heat or pressure. This non-meltable portion 182 does not melt or deform during reflow and maintains its form and shape. The size of the non-fusible portion 182 can be designed to provide a separation distance between the semiconductor die 188 and the substrate 192. A coating such as a copper organic solderable preservative (OSP) can be applied to the substrate 192. A molded underlayer material 194 is deposited between the semiconductor die 188 and the substrate 192 to fill the gap between the die and the substrate.

The non-fusible portion 182 and the fusible portion 184 of the composite bump 180 are made of different bump materials. The non-meltable portion 182 can be gold, copper, nickel, high lead solder, or lead-tin alloy. The fusible portion 184 can be tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or other tin alloy with silver, copper, or lead.

During the reflow process, a large number (e.g., thousands) of composite bumps 180 on the semiconductor die 188 are attached to the interconnect locations on the traces 190 of the substrate 192. Some of the bumps 180 may not be properly attached to the substrate 192, particularly if the die 188 is warped. Recall that the composite bump 180 is larger than the trace 190, with the appropriate force applied, the fusible portion 184 around the trace 190 is deformed or protruded, and the composite bump 180 is mechanically locked to the substrate 192. This mechanical interlock is due to the fact that the fusible portion 184 is softer than the trace 190. During reflow, this mechanical interlock between the composite bump 180 and the substrate 192 maintains the bump to the substrate, i.e., the bump does not lose contact with the substrate. Therefore, the composite bump 180 is paired with the substrate 192 to reduce the bump connection failure.

Any stress generated by the interconnection between the die and the substrate may cause damage or failure of the die. This grain contains a low dielectric constant (k) material that is susceptible to damage from stresses generated by heat. This sharpened composite bump 180 can reduce the interconnect stress on the semiconductor die 188 and result in less damage to low dielectric constant (k) materials, as well as lower die failure rates.

Having described one or more embodiments of the present invention in detail, it will be understood by those skilled in the art that the present invention may be modified and modified without departing from the scope of the invention as set forth in the appended claims.

10. . . Semiconductor grain

12. . . Bump

18. . . Bump pad

20. . . Trace

26. . . Solder mask

28. . . Registration opening

30. . . Substrate

50. . . Electrical device

52. . . Printed circuit board (PCB)

54. . . Signal trace

56. . . Wiring package

58. . . Flip chip

60. . . Ball grid array (BGA)

62. . . Projected wafer carrier (BCC)

64. . . Dual internal package (DIP)

66. . . Flat grid array (LGA)

68. . . Multi-chip module (MCM)

70. . . Quad flat no-pin package (QFN)

72. . . Small square flat seal

74. . . Semiconductor grain

76. . . Contact pad

78. . . Intermediate carrier

80. . . wire

82. . . wiring

84. . . Plastic closures

88. . . Semiconductor grain

90. . . Carrier

92. . . Underfill

94. . . wiring

96. . . Contact pad

98. . . Contact pad

100. . . Molded compound

102. . . Contact pad

104. . . Bump

106. . . Intermediate carrier

108. . . Active area

110. . . Bump

111. . . Bump pad

112. . . Bump

114. . . Signal line

115. . . Printed circuit board (PCB)

117. . . Sphere

118. . . Conductive trace

120. . . Semiconductor grain

122. . . Bump pad

130. . . Trace

132. . . Trace

136. . . Substrate

138. . . Bump pad

139. . . Bump pad

140. . . Bump pad

142. . . Solder mask

144. . . Solder mask patch

150. . . Bump

152. . . Bump

160. . . Composite bump

162. . . Non-meltable part

164. . . Fusible part

166. . . Contact pad

168. . . Semiconductor grain

170. . . wire

172. . . Substrate

174. . . Molded base material

180. . . Composite bump

182. . . Non-meltable part

184. . . Fusible part

186. . . Contact pad

188. . . Semiconductor grain

190. . . Trace

192. . . Substrate

194. . . Molded base material

Figure 1 illustrates a cross-sectional view of a conventional interconnection formed between a semiconductor die and a trace on a substrate; Figure 2 illustrates a top view of a conventional interconnect formed on a trace via a solder mask opening; Figure 3 illustrates a printing a circuit board (PCB) having a different form of package mounted to its surface; Figures 4a-4d illustrate further details of a typical semiconductor package mounted to the PCB; Figure 5 illustrates the formation of a semiconductor die and trace formed on the substrate Interconnects; Figures 6a-6c illustrate integrated bump pads formed along traces; Figure 7 illustrates the formation of solder mask fills in the gaps in the array of integrated bump pads on the substrate; Figure 8 illustrates integration during reflow a bump formed on the bump pad having a bump material limited by a solder mask patch; Figures 9a-9b illustrate a composite interconnect having a non-meltable substrate and a fusible cover; and Figures 10a-10d illustrate non-melting The substrate is interconnected with a tapered composite of the fusible cover.

130. . . Trace

132. . . Trace

136. . . Substrate

138. . . Bump pad

142. . . Solder mask

144. . . Solder mask patch

Claims (15)

A method of fabricating a semiconductor device, comprising: providing a semiconductor die comprising an array of die bump pads; providing a substrate comprising a plurality of traces having integrated bump pads to form an array of integrated bump pads Forming a plurality of mask patches in the array of the die bump pads or the array of the integrated bump pads; depositing on the integrated bump pads or the die bump pads a conductive bump material; the semiconductor die is mounted on the substrate such that the conductive bump material is disposed between the die bump pads or the integrated bump pads; and the conductive bump material is Reflow, but without a mask around the integrated bump pads to form an interconnection between the semiconductor die and the substrate, wherein the mask fills limit the conductive bump material during reflow In the footprint of the die bump pads or the integrated bump pads. The method of claim 1, wherein the mask patch comprises a non-wettable material. The method of claim 1, wherein the interconnect comprises a non-fusible substrate and a fusible cover. The method of claim 1, wherein the volume of the conductive bump material between the die bump pads and the integrated bump pads is selected such that a surface tension is maintained during reflow. The conductive bump material is substantially limited to the use of the die bump pads or the integrated bump pads In space. The method of claim 1, wherein the minimum separation spacing of the trace is given by (1.1D+W)/2, where D is the diameter of the interconnect and W is the width of the trace. A method of fabricating a semiconductor device, comprising: providing a substrate comprising a plurality of traces having integrated bump pads; forming a plurality of mask patches between the integrated bump pads; depositing conductive bump material The integrated bump pads; and reflowing the conductive bump material, but without a mask around the integrated bump pads to form an interconnect, wherein the mask fills during reflow The conductive bump material is confined in the footprint of the integrated bump pads. The method of claim 6, wherein the mask patch comprises a non-wettable material. The method of claim 6, further comprising: immersing the conductive bump material in a flux solution to increase the humidity. The method of claim 6, wherein the interconnect comprises a non-fusible substrate and a fusible cover. The method of claim 6, wherein the volume of the conductive bump material deposited on the integrated bump pads is selected such that a surface tension substantially limits the conductive bump material to the Wait for the integration of the bump pad in the occupied space. The method of claim 6, wherein the height of the interconnect is equal to or less than the diameter of the interconnect. A semiconductor device comprising: a semiconductor die comprising a plurality of first bump pads; a substrate comprising a plurality of traces comprising a second bump pad; a plurality of mask patches being formed between the second bump pads; And maintaining an interconnection between the one of the plurality of first bump pads and the second bump pads by a surface tension. The semiconductor device of claim 12, wherein the mask patch comprises a non-wettable material. The semiconductor device of claim 12, wherein the interconnect comprises a non-meltable substrate and a fusible cover. The semiconductor device of claim 12, wherein the masks are interstitially formed in the array of the second bump pads.