201133664 六、發明說明： 【發明所屬之技術領域】 本發明一般有關於半導體裝置’以及更特別是有關於 在以焊料遮罩補綴的回焊期間，局限導電凸塊材料的半導 體裝置和方法。 【先前技術】 在現代電子產生中通常可以發現半導體裝置。半導體 裝置電性組件之數目與密度可以改變。離散半導體裳置通 常包括一種形式電性組件，例如：發光二極體（led)、小产 號電晶體'電阻器、電容器'電感器以及功率金屬氧化物 半導體場效應電晶體（MOSFET)。積體半導體裝置典型地包 括數百個至數百萬個電性組件。積體半導體裝置之例包 括：微控制器、微處理器、電荷耦合裝置（CCD)、太陽能電 池以及數位微鏡裝置（DMD) » 半導體裝置實施廣大範圍之功能，例如：高速計算、 發射與接收電磁信號、控制電子裝置、將陽光轉變成電力、 以及產生用於電視顯示之視覺投影。在娛樂、通訊、電力 轉換、網路、電腦、以及消費者產品之領域令可以發現半 導體裝置。在軍事庫用•允 、左由 ^ m航空' &車、工業控制器以及辦 么室設備中亦可以發現半導體裝置。 半導體裝置使用半導體材料之電氣性質。半導體材料 =結構允許其導電率藉由施加電場或基極電流、或經 雜過程而操控。掺雜會將雜質導入於半導體材料中， 4 201133664 以操縱且控制半導體裝置之導電率。 半導體裝置包括主動與被動電性結構。主動結構包括 雙載子電晶體與場效應電晶體，其控制電流之流動。藉由 改變掺雜以及施加電場或基極電流之位準，電晶體可以增 強或限制電流之流動。被動結構包括：電阻器、電容器以0 及電感器，在所實施各種所需電性功能之電塵與電流之間 產生關係。將此等被動與主動結構電性連接以形成電路， 其使得半㈣裝置能夠實施高料算與其他有用功能。 通常使用兩個複雜製造過程以製造半導體裝置，即前 端製造過程與後端製造過程，其各可能涉及數百個步驟。 前端製造過程涉及在半導體晶圓表面上形成複數個晶粒 (die)。各晶粒典型地相同，且包含藉由將主動與被動組件 電性連接所形成之電路。後端製造過程涉及將所完成晶圓 單-化成個別晶粒’且將此等晶粒封裝以提供結構支持盘 環境隔離。 ^ 半導體製造之-目標為生產較小的半導體裝置。較小 的裝置典型地消耗較少功率，具有較高性能表現，且可以 更有效率地製造。此外，較小半導體裝置具有較小佔用空 間(foot—)，此對於較小終端產品為令人所欲。可以藉由 改善前端製造過程以達成較小晶粒尺寸，以導致具有較小 尺寸且較面密度主動與被動組件之晶粒。後端製造過程可 以藉由改善電性互連與封裝材料，以導致具有較小佔用* 間之半導體裝置封裝。 1 圖1與圖2說明覆晶形式半導體晶粒丨〇與互連或凸塊 201133664 12之一部份之橫截面圖與頂視圖，其冶金地且電性地連接 介於凸塊墊18之間，而形成於基板30上且形成於半導體 晶粒Η以及跡線2〇與22上。跡線22路由在基板 介於跡線2〇與凸塊12之間。跡線20與22為電氣信號導 體，具有選擇性之凸塊墊，用於匹配至凸塊12_丨4。焊料遮 罩26覆蓋跡線20與22。焊料遮罩或配準開口（sr〇)28形 成於基板30上，以曝露跡線2〇與22。SR〇 28在回焊期間 限制在跡線20與22之凸塊墊上之導電凸塊材料，且防止 熔化之凸塊材料進入至跡線上，這會造成對於相鄰結構之 電性短路。將SRO 28製得較跡線或凸塊墊為大。SR〇 28 典型地為圓形且被製得儘可能地小，以減少跡線2〇與22 之間距且增加路由密度。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to semiconductor devices and, more particularly, to semiconductor devices and methods for confining conductive bump materials during reflow soldering with solder masks. [Prior Art] A semiconductor device can usually be found in modern electronic generation. The number and density of electrical components of a semiconductor device can vary. Discrete semiconductor devices typically include a form of electrical component such as a light emitting diode (LED), a small transistor 'resistor', a capacitor' inductor, and a power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically include hundreds to millions of electrical components. Examples of integrated semiconductor devices include: microcontrollers, microprocessors, charge coupled devices (CCDs), solar cells, and digital micromirror devices (DMDs). Semiconductor devices implement a wide range of functions, such as high-speed computing, transmission and reception. Electromagnetic signals, control electronics, convert sunlight into electricity, and produce visual projections for television displays. Semiconductor devices can be found in the fields of entertainment, communications, power conversion, networking, computers, and consumer products. Semiconductor devices can also be found in military libraries, including, and by left, from the 'm aviation' & car, industrial controllers, and office equipment. Semiconductor devices use the electrical properties of semiconductor materials. Semiconductor Material = Structure allows its conductivity to be manipulated by applying an electric or base current, or a complex process. Doping introduces impurities into the semiconductor material, 4 201133664 to manipulate and control the conductivity of the semiconductor device. Semiconductor devices include active and passive electrical structures. The active structure includes a bipolar transistor and a field effect transistor that controls the flow of current. The transistor can enhance or limit the flow of current by changing the level of doping and applying an electric field or base current. Passive structures include: resistors, capacitors with 0s and inductors that create a relationship between the electrical dust and current required to perform the various electrical functions required. These passive and active structures are electrically connected to form a circuit that enables the half (four) device to perform high computational and other useful functions. Two complex manufacturing processes are typically used to fabricate semiconductor devices, namely front-end manufacturing processes and back-end manufacturing processes, each of which may involve hundreds of steps. The front end manufacturing process involves forming a plurality of dies on the surface of the semiconductor wafer. Each die is typically identical and includes circuitry formed by electrically connecting active and passive components. The back-end manufacturing process involves singulating the completed wafers into individual dies and packaging the dies to provide structural support for disk environmental isolation. ^ Semiconductor Manufacturing - The goal is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be manufactured more efficiently. In addition, smaller semiconductor devices have less footprint (foot-), which is desirable for smaller end products. It is possible to achieve a smaller grain size by improving the front end manufacturing process to result in a die having a smaller size and a face density active and passive component. The back end manufacturing process can result in a semiconductor device package with less footprint by improving the electrical interconnect and packaging materials. 1 and FIG. 2 illustrate cross-sectional and top views of a portion of a flip-chip semiconductor die and interconnect or bump 201133664 12 that are metallurgically and electrically connected between bump pads 18 Formed on the substrate 30 and formed on the semiconductor die and the traces 2 and 22. Trace 22 is routed between the substrate 2〇 and the bump 12. Traces 20 and 22 are electrical signal conductors with selective bump pads for mating to bumps 12_丨4. Solder mask 26 covers traces 20 and 22. A solder mask or registration opening (sr〇) 28 is formed over the substrate 30 to expose traces 2 and 22. SR 〇 28 limits the conductive bump material on the bump pads of traces 20 and 22 during reflow and prevents molten bump material from entering the trace, which can cause electrical shorts to adjacent structures. The SRO 28 is made larger than the trace or bump pad. The SR〇 28 is typically circular and made as small as possible to reduce the spacing between the traces 2〇 and 22 and increase the routing density.
以典型地設計規則，跡線30之最小分隔（escape)間距界 定為P= (1，1D + W)/2 + L，其中，D為凸塊基底直徑，冒為 跡線寬度，以及L為SRO 與相鄰結構間之帶狀間隔。使用±30微米（/Czm)之焊料登記 設計規則，D為100 " m，W為20 " m , L為3〇 μ m，則跡 線30-34之最小分隔間距界定為（1 i*i〇〇 + 2〇)/2 + 3〇=95# m。在凸塊墊周圍之SRO 28限制半導體晶粒之分隔間距與 路由密度。 【發明内容】 目洳存在一種需求，欲將用於較高路由密度之跡線之 分隔間距最小化。 6 201133664 因此，在一實施例中，本發明為一種製造半導體裝置 -之方法，其包括以下步驟：提供-半導體晶粒，其具有晶 粒凸塊墊；提供一基板，其所具有整合凸塊墊的跡線；形 成一焊料遮罩補綴，其間隙地設置介於晶粒凸塊塾之間或 整合凸塊墊之間；將導電凸塊材料沉積在整合凸塊墊或晶 粒凸塊墊上，將半導體晶粒安裝於基板上，以致於導電凸 塊材料設置在晶粒凸塊墊與整合凸塊墊之間；以及將導電 凸塊材料回焊，而在整合凸塊塾周圍沒有焊料遮罩，而在 半導體晶粒與基板之間形成互連。在回焊期間，此焊料遮 罩補綴將導電凸塊材料限制在晶粒凸塊塾或整合凸塊塾之 佔用空間中。 在另-實施例中，本發明為—種製造半導體裝置之方 法，其包括以下步驟：提供—笙 ^ ,L ^ 第—半導體結構，其具有第 一凸塊墊；提供一第二半導體塞 ^ ^ 卞守體結構’其具有第二凸塊墊； 在此等第一凸塊墊之間或此箅筮_ 寻第一凸塊墊之間形成焊料遮 罩補綴；將導電凸塊材料沉藉尤贫 .^ 寸儿檟在第一與第二凸塊墊之間； 將第一半導體結構安裝於第二丰道_牌处槐L t 布一千導體結構上，以致於導電 凸塊材料設置在第一凸塊塾盘第-几％ '、弟一凸塊墊之間；以及將導 電凸塊材料回焊，而在第一盥篦-i m m _ 〜弟一凸塊墊周圍沒有焊料遮 罩，以形成互連。在回焊期間，&的， 纤j間’此焊料遮罩補綴將導電凸 塊材料限制在第一凸塊墊或第-几地# '昂一凸塊墊之佔用空間中。 在另一實施例中，本發明& 知月為一種製造半導體裝置之方 法，其包括以下步驟：提供—其^ 基板’其所具有跡線具有整With a typical design rule, the minimum escape spacing of trace 30 is defined as P = (1, 1D + W)/2 + L, where D is the bump base diameter, which is the trace width, and L is The band spacing between the SRO and the adjacent structure. Use ±30 micron (/Czm) solder registration design rules, D is 100 " m, W is 20 " m , L is 3〇μ m, then the minimum separation spacing of traces 30-34 is defined as (1 i *i〇〇+ 2〇)/2 + 3〇=95# m. The SRO 28 around the bump pads limits the separation pitch and routing density of the semiconductor grains. SUMMARY OF THE INVENTION There is a need to minimize the separation spacing of traces for higher routing densities. 6 201133664 Accordingly, in one embodiment, the present invention is a method of fabricating a semiconductor device comprising the steps of: providing a semiconductor die having a die bump pad; providing a substrate having integrated bumps a trace of the pad; forming a solder mask patch with a gap between the die bumps or between the integrated bump pads; depositing the conductive bump material on the integrated bump pad or die bump pad Mounting the semiconductor die on the substrate such that the conductive bump material is disposed between the die bump pad and the integrated bump pad; and reflowing the conductive bump material without solder covering around the integrated bump The cover forms an interconnection between the semiconductor die and the substrate. This solder mask patch confines the conductive bump material to the footprint of the die bumps or integrated bumps during reflow. In another embodiment, the invention is a method of fabricating a semiconductor device, comprising the steps of: providing a 笙^, L^-th semiconductor structure having a first bump pad; providing a second semiconductor plug ^ 卞 体 体 ' ' Having a second bump pad; forming a solder mask patch between the first bump pads or the first bump pad; ^ 槚 之间 between the first and second bump pads; the first semiconductor structure is mounted on the second Fengdao _ brand 槐 L t cloth one thousand conductor structure, so that the conductive bump material is set in the a bump of the first -% of the disc, between the bump pads; and the conductive bump material is reflowed, and there is no solder mask around the first 盥篦-imm _ Form an interconnection. During solder reflow, the solder mask patch of & is limited to the conductive bump material in the footprint of the first bump pad or the first bump pad. In another embodiment, the present invention is a method of fabricating a semiconductor device comprising the steps of: providing a substrate having a trace
合凸塊墊；在整合凸塊墊之間开彡士、p ^ A 间形成焊料遮罩補綴；將導電 7 201133664 凸塊材枓 >儿積在整合凸塊 μβ ^ . Α 展堂上，以及將導電凸塊材料回 烊，而在整合凸塊墊周圍 ^ .θ .〇 0a 有焊枓遮罩，以形成互連。在 回知期間，此焊料遮軍補 „ ^ ^、‘双將導電凸塊材料限制在整合凸 塊墊之佔用空間中。 一二另Β實施例中’本發明為一種半導體裝置，其包括: :一體晶粒，其具有第一凸塊墊與基板，此基板具有有 , 遲罩補、.双形成於此等第一凸塊墊之間 或此等第二凸塊墊之間。鈐 錯由將導電凸塊材料回焊、在第 二凸塊墊周圍沒有焊料遮罩，而在第一與第二凸塊墊之間 形成互連。此焊料遮罩補㈣導電凸塊材料限制在第一凸 塊墊與第二凸塊墊之中。 【實施方式] 本毛月在以下一或更多實施例中參考所附圖式說明， -中相同號碼代表相同或類似元件。雖然、，本發明是以 達成本發明目的之最佳模式說明，然而，$習此技術人士 瞭解，其用意為包含各種錢、修正、以及等同，而此等 替代i#正、f同是包含於由所附中請專利範圍與其等同 物所界定本發明精神與範圍+，且由以下揭示内容與圖式 所支持。 通常使用兩個複雜製造過程以製造半導體裝置：前端 裝迨過私與後端製造過程。前端製造過程涉及在半導體晶 圓表面上形成複數個晶粒（die)。在晶圓上之各晶粒包含主 動與被動電性組件，其電性連接以形成功能性電路。主動 8 201133664 電：組件例如為電晶體與二極體，其具有能力以控制電流 之桃動:破動電性組件例如為電容器、電感器、電阻器以 /土器其在實施所須電路功能之電壓與電流之間產生 關係。 曰匕等被動與主動組件藉由一系列製程步驟形成於半導 體曰曰圓之表面上。此等步驟包括：掺雜、沉積、微影術、 2刻以及平坦化。掺雜藉由例如離子植入或熱擴散技術， 將雜質導入於半導體材料中。此掺雜過程可以改變在主動 牛：之半導體材料之導電率，將半導體材料轉換成絕緣 :導電體，或動態地改變半導體材料導電率，以響應於 七或土極電肌。電晶體包括改變型式與換雜程度之區 1其如同所需地配置，以使得在施加電場或基極電流時， 電晶體可以增強或限制f流之流動。 主動與被動組件可以由具有不同電氣性質之材料層所 :成。此等層可以藉由各種沉積技術所形成，此 由所__之型式所決L，薄膜沉積可以涉及： 化予礼相’儿積（CVD)、物理氣相沉積（pvD)、電解質電錢以 及無電極電鍍過程。通常將各層圖案化以形成：主動組件、 被動組件或組件間電性連接之部份。 料例nr用心術將此等層圖案化，其涉及將光敏感材 冗積在被圖案化之層上。使用光線將圖案由光 罩移轉至光阻。使用溶㈣受光線照射之光阻圖案= 衹圖案化下層之部份。將光阻之剩餘部 除’以留下圖案化層。以替代方式，可以使用例如無;： 201133664 與電解質電鍍技術’藉由將材料直接沉積於由先前沉積/餘 刻過程所形成區域或洞孔中，將一些型式材料圖案化。 將薄膜材料沉積於現有圖案上，會擴大下面圖案，且 產生不均句之平坦表面。通常需要均勻平坦表面，以產生 較小尺寸且更密集地封裝之主動與被動組件。可以使用平 坦化將材料從晶圓表面去除’以產生均勻平坦表面。平土曰 化涉及以拋光墊將晶圓表面拋光。在拋光期間，將研磨材 料與腐钮性化學物質添加至晶圓表面。此研磨之機械作用 與化學物質之腐蝕作用之組合，將晶圓表面任何不規則地 形去除’以產生均勻平坦表面。 後端製造過程是指將所完成晶圓切割或單一化成為^ 別晶粒，以及然後將此等晶粒封裝用於結構支持與環境段 離。為了將此晶粒單一化’將晶圓沿著稱為鋸道或劃線^ 晶圓無功能區域劃線且分開。使用雷射切割工具或鋸刀步 晶圓單-化。在單一化之後，將個別晶粒安裝至封裝基板、 此基板包括接腳或接觸塾，用於與其他系統組件互連。费 後’將此半導體晶粒上所形成之接觸塾連接至此封裝中之 接觸墊。此電性連接可以焊料凸塊、柱凸塊、導電聚或接 線製成。將封膠或其他模製材料沉積在封裝上，以提供實 體支持與電性隔離。然[將此所完成封裝插入於電性系 統中，域得此半導體裝置功能可供其他系統組件使用。 ，3說明具有晶片載體基板或印刷電路板(pcB) 之 4置50 &基板或電路板具有複數個安裴於其表面上 之半導體封褒。取決於應用，此電子農置Μ可以具有一種 10 201133664 型式半導體封裝或多種型式半導體封裝。用於說明目的， 圖3中顯示不同型式半導體封裝。 電子4置50可以為獨立式（stand al〇ne)系統其使用 半導體封裝以實施一或更多個電性功能。以替代方式，電 子裝置5〇可以為一較大系統之次組件。例如，電子裝置5〇 為可以插入於電腦中之圖形卡、網路介面卡或其他：號處 理卡。半導體封裝可以包括微處理器、記憶體、特殊用途 積體電路(ASIC)、邏輯電路、類比電路、射頻(rf)電路、離 散裝置或其他半導體晶粒或電性組件。 在圖3中，PCB 52提供一般基板，用於安裝在於pcB 上半導體封裝之機械支持與電性互連。使用蒸錢、電解質 電链、無電極電錢、絲網印刷或其他適當金屬沉積過程， 在PCB 52之表面上或層中形成導電信號跡線。 信號跡線54提供在各半導體封裝、安裝組件以及其他 外部系統組件之問$雷、奎 電ϋ連通。跡線5 4亦將功率與接地連 接提供給各半導體封裝。 —些實施例中，半導體裝置具有 -位準封裝為—種技術，用於將半導體晶粒機械地且電 ill:一中間載體。第二位準封裝是關於將中間載體 ==性地裝附於PCB。在其他實施例中，半導體裝 第一位準封裳’而將晶粒機械地且電性地直接安 至 P C B 〇 封裝 為J說明目的而顯示，在PCB 52上數種型式第一位準 ’’、包括接線封裝56與覆晶58。此外，顯示在PCB 52 201133664 上數，型式第二位準封裝，其包括：球格栅陣mBGA)60、 凸塊晶片載體（BCC)62、雙内線封裝（DIP)64、平面格拇陣列 LGA)66、多晶片模組（MCM)68、四方形扁平無接腳封裝 (QFN)7G以及四方形爲平封裝72 ^取決於二a bump pad; a solder mask patch is formed between the integrated bump pads to open a gentleman and p ^ A; and the conductive 7 201133664 bump material 枓 is accumulated on the integrated bump μβ ^ . Α exhibition hall, and The conductive bump material is returned, and a solder mask is formed around the integrated bump pad to form an interconnect. During the retracement, the solder shields the conductive bump material in the occupied space of the integrated bump pad. In the embodiment, the present invention is a semiconductor device including: An integrated die having a first bump pad and a substrate, the substrate having a late cover fill, a double formed between the first bump pads or the like, or between the second bump pads. An interconnection is formed between the first and second bump pads by reflowing the conductive bump material without a solder mask around the second bump pad. The solder mask complement (four) conductive bump material is limited to A bump pad and a second bump pad. [Embodiment] The present invention is described in the following one or more embodiments with reference to the accompanying drawings, wherein the same reference numerals represent the same or similar elements. The invention is described in terms of the best mode for achieving the objects of the present invention. However, it is understood by those skilled in the art that it is intended to include various kinds of money, amendments, and equivalents, and such alternatives i#正,f are included in the accompanying The scope and scope of the invention defined by the scope of the patent and its equivalents It is supported by the following disclosure and drawings. Two complex manufacturing processes are commonly used to fabricate semiconductor devices: front-end mounting and back-end manufacturing processes. The front-end manufacturing process involves forming a plurality of grains on the surface of a semiconductor wafer ( Each of the dies on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active 8 201133664 Electrical: Components such as transistors and diodes have the ability to control current Peach: Breaking electrical components such as capacitors, inductors, resistors, etc., have a relationship between the voltage and current required to perform the required circuit functions. 被动Phase and active components through a series of process steps Formed on the surface of the semiconductor dome. These steps include: doping, deposition, lithography, 2 engraving, and planarization. Doping is introduced into the semiconductor material by, for example, ion implantation or thermal diffusion techniques. This doping process can change the conductivity of the active semiconductor material, convert the semiconductor material into insulation: electrical conductors, or dynamically change the semiconductor The bulk material is electrically conductive in response to the seven or earthy electromyography. The transistor includes a zone 1 of varying degrees and degrees of modification, which is configured as desired such that when an electric field or base current is applied, the transistor can be enhanced or Limiting the flow of f-flow. Active and passive components can be made of layers of materials with different electrical properties: these layers can be formed by various deposition techniques, which are determined by the type of __, thin film deposition can involve : Incorporating ritual 'CVD, physical vapor deposition (pvD), electrolyte money, and electrodeless plating. Patterns are typically patterned to form: active components, passive components, or electrical connections between components The sample nr is used to pattern these layers, which involves the redundancy of the light-sensitive material on the patterned layer. The light is used to transfer the pattern from the mask to the photoresist. Photoresist pattern = only part of the lower layer is patterned. The remainder of the photoresist is divided to leave a patterned layer. Alternatively, some type of material may be patterned using, for example, no; 201133664 and electrolyte plating techniques by depositing material directly into regions or holes formed by previous deposition/residual processes. Depositing the film material onto an existing pattern enlarges the underlying pattern and produces a flat surface with unevenness. A uniform flat surface is often required to produce active and passive components that are smaller in size and more densely packaged. The flattening can be used to remove material from the wafer surface to create a uniform flat surface. Flat soiling involves polishing the surface of the wafer with a polishing pad. The abrasive material and the squeezing chemicals are added to the wafer surface during polishing. The combination of the mechanical action of the grinding and the corrosive action of the chemical removes any irregularities on the wafer surface to create a uniform flat surface. The back-end manufacturing process refers to cutting or singulation of the completed wafer into a die, and then using the die package for structural support and environmental segmentation. In order to singulate the grains, the wafers are scribed and separated along a non-functional area called a saw or a scribe line. Use a laser cutting tool or a saw blade to process wafers. After singulation, the individual dies are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. The contact 形成 formed on the semiconductor die is attached to the contact pads in the package. This electrical connection can be made of solder bumps, stud bumps, conductive poly or wires. A sealant or other molding material is deposited on the package to provide physical support and electrical isolation. [This insertion of the completed package into an electrical system allows the semiconductor device to be used by other system components. 3 illustrates a semiconductor package having a wafer carrier substrate or a printed circuit board (PCB) having a plurality of semiconductor packages mounted on the surface thereof. Depending on the application, the electronic farm can have a 10 201133664 type semiconductor package or a variety of type semiconductor packages. For illustrative purposes, different types of semiconductor packages are shown in FIG. The electronic device 50 can be a stand-alone system that uses a semiconductor package to implement one or more electrical functions. Alternatively, the electronic device 5A can be a secondary component of a larger system. For example, the electronic device 5 is a graphics card, a network interface card, or other processing card that can be inserted into a computer. Semiconductor packages may include microprocessors, memories, special purpose integrated circuits (ASICs), logic circuits, analog circuits, radio frequency (RF) circuits, discrete devices, or other semiconductor dies or electrical components. In Figure 3, PCB 52 provides a general substrate for mounting mechanical and electrical interconnections of the semiconductor package on the pcB. Conductive signal traces are formed on or in the surface of the PCB 52 using steaming, electrolyte chains, electrodeless electricity, screen printing, or other suitable metal deposition processes. Signal traces 54 provide for the connection of various semiconductor packages, mounting components, and other external system components. Trace 54 also provides power and ground connections to each semiconductor package. In some embodiments, the semiconductor device has a level-aligned technique for mechanically and electrically singulating the semiconductor die: an intermediate carrier. The second level of packaging is about attaching the intermediate carrier to the PCB. In other embodiments, the semiconductor is mounted on the first level and the die is mechanically and electrically directly attached to the PCB. The package is shown for the purpose of J, and the first level of the pattern is on the PCB 52. ', including wiring package 56 and flip chip 58. In addition, shown on PCB 52 201133664, the type of second level package includes: ball grid array mBGA) 60, bump wafer carrier (BCC) 62, dual inner package (DIP) 64, planar lattice array LGA 66, multi-chip module (MCM) 68, quad flat no-sleeve package (QFN) 7G and quad flat package 72 ^ depends on two
將半導體封据 J U 扁之任何組合、以第一與第二位準封裝型式之 任何組合而組態，而將其與其他電子组件一起連接至pa I2。在一些實施例中’電子裝置5〇包括單一裝附半導體封 褒，而其他實施例需要多個互連封裝。藉由將一或更多個 :導體封裝组合於單一基板上，製造商可以將預製組件合 於電子裝置與系統中。因為半導體封裝包括複雜功能， 可以使用較便宜組件與合理化製程以製造電子裝置。此所 產生之裝置較不可能故障且製造較便宜，導致對於消費者 較低成本。 圖4a_4d顯不典範半導體封裝。圖4a說明安裝於PCB ?上DIP 64之進-步細節。半導體晶粒74包括：—主動 區域’其所包含類比或數位電路執行作為主動元件、被動 "導電層以及形成於晶粒中之介電層，且根據晶粒之 電，設計而電性互連。例如，電路可以包括：一或更多個 體—極體、電感器、電容器、電阻器以及形成於半 導體晶粒74主動區域中之其他電路元件。接觸墊％為一 或更夕層導電材料，例如紹⑽、銅（Cu)、錫（如）、錄⑼）、 ()或銀（Α§)，且電性連接至形成於半導體晶粒74中之 元件在DIP 64組裝期間，使用金-石夕共晶層或黏著材 料例如熱環氧樹脂，將半導體…4安裝至一中間載體 12 201133664 78 °封裝體包括絕緣封裝 8。與接線㈡提供半導體晶二:=“⑽。導線 封膠84沉積在封裝上，其藉由防止 @之電t生互連。 污染晶粒74戈接線82 濕軋與粒子進入封裝且 次接線82而作環境保護。 圖仆說明安裝在PCB 52上bc 用底部填料或環氧樹脂黏著材料92，將半之導== 在載體90上。接狳十導體日日粒88女裝 封艺互連從 ㈣墊96與98間之第一位準 =裝互連。將模製複合物或封膝⑽沉積在半導體 使八上屬以提供用於此裝置之實體支持與電性隔離。 以防止：：過程例如電解質電鍍或無電極電鍍過程 接觸塾⑽形成一之表面上。將接 …在BCC62連接至咖52中—或更多個導電信號跡線 成凸塊：之接觸塾一 52之接觸塾1〇2之間形 在圖4c中，將半導體晶粒58面向下、以 位準封裝安裝至中間載體106。半導體曰位5…：第 千等篮日日拉58之主動區域 …已括類比或數位電路，其執行作為根據晶粒電性設計所 形成之主動元件、被動元件、導電層、以及介電層。例如， 電路可以包括：-或更多個電晶體、二極體、電感器、電 容器、電阻器以及在主動…〇"之其他電路元件。半 導體晶58經由凸塊11G而電性地且機械地連接至載體 使用凸塊112，將 電性地且機械地連接至 BGA 60以BGA型式第二位準封裝 PCB 52。經由凸塊110、信號線114 13 201133664 以及Λ塊112，將半導體晶粒58電性地連接至在pcb 52 中之導電信號跡線54 »將模製複合物或封膠丨16沉積在半 導體晶粒58與載體106上，以提供用於此裝置之實體支持 與電性隔離。此覆晶半導體裝置提供從在半導體晶粒5 8上 主動元件至在PCB 52上導電執之短的導電路徑，以便縮短 信號傳送距離、降低電容 '以及改善整個電路之性能表現。 在另一實施例中，可以使用覆晶型式第一位準封裝而無需 中間載體106，將半導體晶粒58電性地且機械地直接連接 至 PCB 52。 在另一實施例中，將半導體晶粒58之主動區域1〇8面 向下直接安裝至PCB 1 15，即不具中間載體，如同於圖切 中所顯示。使用蒸鍍、電解質電鍍、無電極電鍍、絲網印 刷或其他適當金屬沉積過程，在主動區域1 〇8上形成凸塊 墊111。凸塊墊111藉由在主動區域108中之導電執而連接 至主動與被動電路。凸塊墊lu可以為鋁（A1)、錫（Sn)、鎳 (N〇、金（Au)、銀（Ag)或鋼（Cup使用蒸鍍、電解質電鍍、 無電極電冑、球滴或絲網印刷過程，將導電凸塊材料沉積 在PCB U5中之凸塊塾⑴或導電軌m上。此凸塊材料 可以為鋁（A1)、錫（Sn)、鎳（Ni)、金（Au)、銀（Ag)、鉛、 銅（Cu)、鉍（Bl)、焊料以及其組合，而具有選擇性的助焊劑 材料。例如’此ώ塊材料可以為共晶Sn/pb、高鉛焊料、或 無鉛焊料。使用適當裝附或接合過程’將凸塊材料接合至 PCB 1 15上晶粒凸塊墊丨丨丨與導電執丨18之間。在一實施例 中，藉由將材料加熱至其炫點以上而使得凸塊材料回焊， 201133664 以形成球體或凸塊丨1 7 ^此覆晶式半導體裝置提供從半導體 ' 晶粒58上主動元件、至PCB 115上導電軌118之短的導電 路徑，以減少信號傳送、降低電容且達成整體較佳電路性 能表現。 圖5說明具有凸塊墊丨22之覆晶式半導體晶粒12〇之 一部份之橫截面圖。跡線130與丨32形成於基板136上。 如同於圖6a中顯示’跡線130與132為具有整合凸塊墊Π8 之直的電性導體。此整合凸塊墊13 8與跡線13 0與1 3 2共 線。以替代方式，跡線130與132可以具有圓形整合凸塊 塾139’如同於圖6b中顯示’或矩形整合凸塊墊ι4〇，如 同於圖6c中顯示。此整合凸塊墊典型地配置於陣列中，以 達成最大互連密度與容量。 在圖7中’將焊料遮罩142沉積在跡線1 30與1 32之 一部份上。然而，焊料遮罩142並未形成於整合凸塊墊138 上。因此，在基板上並沒有用於各凸塊墊之SR〇，如同在 圖2習知技術中所發現者。在整合凸塊墊138之陣列中、 即在相鄰凸塊墊之間，在基板136上間隙地形成不會濕的 焊料遮罩補綴144。亦可在晶粒凸塊墊122之陣列中在半導 體晶粒10上間隙地形成焊料遮罩補綴。更一般而言，在任 何配置中，此焊料遮罩補綴是非常靠近整合凸塊墊而形 成，以避免流出至較不溼區域。圖8顯示於整合凸塊墊138 上所形成之凸塊150與152,且由悍料遮罩補綴144所限制。 彳以使用蒸鍍、電解質電鍍、無電極電鍍、球滴或絲 網印刷過程’將導電凸塊材料沉積在晶粒凸塊墊122或整 15 201133664 合凸塊墊138上。此凸塊材料可以為鋁（Αι)、錫（Sn)、鎳 (Ni)、金（Au)、銀（Ag)、鉛（Pb)、鉍（Bi)、銅（Cu)、焊料以及 其組合，而具有選擇性的助焊劑溶液。例如，此凸塊材料 可以為共sa Sn/Pb、向鉛焊料、或無鉛焊料。使用適當裝附 或接合過程，將凸塊材料接合至整合凸塊墊丨38。在一實施 例中，藉由將材料加熱至其熔點以上而使得凸塊材料回 焊，以形成球體或凸塊150與152。在一些應用中，此凸塊 150與152第二次回焊，以改善至晶粒凸塊墊122與整合凸 塊墊1 38之電性接觸。凸塊亦可以被壓擠接合至晶粒凸塊 墊122與整合凸塊墊138。凸塊15〇與152代表可以形成於 整合凸塊墊138上之一種形式互連結構。此互連結構亦可 使用柱凸塊、微凸塊、或其他電性互連。 在高路由（routing)密度應用中，令人想要將分隔間距最 小化。為了減少在跡線130與132之間距，將凸塊材料回 焊.，而在整合凸塊墊138周圍並無焊料遮罩。此跡線13〇 與1 3 2之間之間隔間距之減少、可以藉由去除用於限制焊 料回焊之焊料遮罩、以及在整合凸塊塾周圍相關之S而 達成’即藉由沒有焊料遮罩，而使得凸塊材料回焊。焊料 遮罩142可以形成於跡線丨3〇與132以及基板136之一部 份上而背向整合凸塊墊丨3 8，如同於圖7中所示。然而，焊 料遮罩142可以不形成於整合凸塊墊138上。這即是，此 被設計與凸塊材料配對之跡線130與132之一部份，在焊 料遮罩142中並未形成SR0。 此外’在整合凸塊墊1 38之陣列中在基板1 36上間隙 16 201133664 地形成焊料遮罩補綴144。此焊料遮罩補辍i44為不可濕材 料。此焊料遮罩補綴144可以為與焊料遮罩⑷相同材料， 且在相同處理步驟期間塗佈；或可以為與烊料遮罩142不 同材料，而在不同處理步驟期間塗佈。焊料遮罩補綴144 可=藉由將整合凸塊塾138《陣列中跡線或塾之部份選擇 性氧化、電鍍或其他處理而形成。焊料遮罩補缀⑷限制 焊料流至整合凸塊墊138，且防止導電凸塊材㈣漏至相鄰 結構。 當凸塊材料以在整合凸塊墊138陣列中間隙地設置之 焊料遮罩補綴H4回焊時，此濕潤與表面張力造成此凸塊 材料被限制與保留於：晶粒凸塊墊122、整合凸塊墊138、 以及直接相鄰於跡線130與132之基板136之部份之間之 二間中’且實質地在整合凸塊墊1 3 8之佔用空間中。 為達成所想要之限制性質，可以在將凸塊材料置於晶 粒凸塊墊122或整合凸塊墊1 38上之前，將凸塊材料浸入 於助焊劑溶液中，以選擇性地使得由凸塊材料所接觸區域 較跡線130與132周圍區域更濕。由於此助焊劑溶液之可 濕|±負’此炼化之凸塊材料保持實質上限制於由凸塊墊所 界定之區域中。此凸塊材料並不會流至較不可濕區域。在 此凸塊材料並不會使得區域較不濕之區域上形成薄氧化層 或其他絕緣層。因此，在晶粒凸塊墊丨22或整合凸塊墊丨38 之周圍並無需焊料遮罩142。 由於在晶粒凸塊墊122或整合凸塊墊138之周圍並未 形成SRO ’可以更精細間距形成跡線1 3〇與1 32，即可以將 17 201133664 跡線1 30與1 32設置更靠近相鄰結構，而不會接觸且形成 電性短路。假设相同焊料配準（registrati〇n)設計規則，則跡 線130與132間之間距給定為p^ .iD + w^，D為凸塊 150-152之底部直徑，且W為跡線13〇與132之寬度。在一 實施例中，給定100々m之凸塊直徑與2〇# m之跡線寬度， 則此跡線1 30與1 32之最小分隔間距為65 # 如同於習知 技術中所發現’此凸塊形成使得無需在相鄰開口於最小可 溶解SRO之間設置焊料遮罩材料之帶狀（Hgament)間隔。 在另一實施例中，在晶粒凸塊墊與整合凸塊墊之間形 成複合互連，以達成所想要凸塊材料之限制。在圖9a 9b 中，此複合凸塊160具有不可熔部份ι62與可熔部份ι64。 此不可熔部份1 62構成較可熔部份i 64為大之複合凸塊i 6〇 之部份。將此不可熔部份162固定至半導體晶粒丨68之接 觸墊或互連位置166。此可熔部份164設置在圖9a中基板 Π2上之導線或跡線17〇上，且與導線n〇實體接觸用於回 焊。如同於圖9b中所示，此可熔部份164由於熱或所施加 壓力而在回焊時在導線170周圍崩潰。此不可熔部份162 在回焊期間並不會熔化或變形，且保持其原來形式與形 狀。可以設計此不可熔部份丨62之尺寸，以提供半導體晶 粒1 68與基板172間之分隔距離。可以將一塗料例如銅有 機可焊保存劑（0SP)塗佈至基板172。將一模製底部材料174 沉積在半導體晶粒168與基板172之間，以填滿在晶粒與 基板間之間隙。 複合凸塊160之不可熔部份162與可熔部份164是由 18 201133664 不同凸塊材料所製成。不可炫部份162可以為金、銅、錄、 高船焊料或錯錫合金。可熔部份164可為錫、無錯合金、 錫銀合金、錫銀銅合金、錫銀銦合金、共晶焊料，或具有 銀、銅、或鉛之其他錫合金。 八 選擇此可熔突塊材料相對於不可熔基底材料之高度或 體積，以確保藉由表面張力之限制。纟回嬋期間，由於焊 料遮罩補綴’將可祕底材料限制在不可熔基底材料之周 圍。在回焊期間，此不可炼基底周圍之可炫凸塊材料亦維 持晶粒設置。通常，此複合互連之高度小於或等於凸塊之 直徑。在-些情形中，此複合互連之高度大於此互連之直 徑。在-實施例中，給定此凸塊基底直徑為㈣心，此不 可熔基底之南度大約45//m，以及此可熔蓋之高度大約為 35 " m。由於焊料遮罩補綴、且因為此被沉積以形成複合凸 塊之凸塊材料之體積，此熔化之凸塊材料實質上保持限制 在由凸塊墊所界定之區域中。此複合凸塊包括：不可熔基 底與可熔蓋，選擇此複合凸塊，以致於所產生之表面張力 足以將凸塊材料實質上保持在凸塊墊之佔用空間中且防 止其流出至不想要之相鄰區域。因此，間隙地形成具有凸 塊塾陣列之焊料遮罩補綴，以減少跡線間距且增加路由密 度。 在回焊過程期間，將大數目（例如數千）在半導體晶粒 168上之複合凸塊160裝附於：基板172之跡線170上之互 連位置。一些突塊1 60可能無法適當地連接至基板1 72，特 別是如果晶粒1 68翹曲的話。回憶起此複合凸塊1 60大於 19 201133664 跡線1 70，以所施加適當之力，此在跡線丨7〇周圍之可熔部 份164變形或突出’且將複合凸塊16〇機械地鎖定至基板 1 72。此機械互鎖是由於可熔部份164較跡線17〇為軟之性 質所形成。在回焊期間’此在複合凸塊丨6〇與基板丨72間 之機械互鎖，將凸塊保持至基板，即此凸塊與基板並不會 失去接觸。因此，將複合凸塊160與基板172配對，以減 少凸塊連接故障。 在另一實施例中’此在晶粒凸塊墊與整合凸塊墊之間 之複合互連是漸漸變尖的。如同於圖丨〇a_丨〇(1中所示，此複 合凸塊1 80具有不可熔部份1 82與可熔部份丨84。此不可炼 部份182構成較可熔部份184為大之複合凸塊丨8〇之部份。 將此不可熔部份182固定至半導體晶粒188之接觸墊或互 連位置186。此可熔部份184設置在基板192上之導線或跡 線190上’且與導線1 90實體接觸用於回焊。此複合凸塊 180延著跡線190漸漸變尖，即此複合凸塊具有一鍥形形 狀，其沿著跡線190之長度較長，且跨跡線19〇較窄。此 複合凸塊180之漸漸變尖部份是沿著跡線19()之長度產 生。圖10a中顯示與跡線190共線變窄之漸尖部份。圖i〇b 垂直於圖10a，顯示此鍥形複合凸塊1 80之較長部份。如同 於圖10c與l〇d中所示，此可熔部份184由於熱或施加壓 力’而在回焊時在導線190周圍崩潰。此不可熔部份ι82 在回焊期間並不會熔化或變形，且保持其形式與形狀。可 以設計此不可熔部份182之尺寸，以提供半導體晶粒I” 與基板192間之分隔距離。可以將一塗料例如銅有機可焊 20 201133664 保存劑（OSP)塗佈至基板192。將一模製底層材料194沉積 在半導體晶粒188與基板192之間，以填滿在晶粒與基板 間之間隙。 複合凸塊180之不可熔部份182與可熔部份184是由 不同凸塊材料所製成。不可熔部份182可以為金、銅、鎳、 高鉛焊料、或鉛錫合金。可熔部份丨84可為錫、無鉛合金、 錫銀合金、錫銀鋼合金、錫銀銦合金、共晶焊料，或具有 銀、銅、或鉛之其他錫合金。 在回焊過程期間，將大數目（例如數千）在半導體晶粒 188上之複合凸塊丨8〇裝附於：基板192之跡線19〇上之互 連位置。一些突塊丨8〇可能無法適當地連接至基板192，特 別是如果晶粒188翹曲的話《回憶起此複合凸塊18〇大於 跡線190,以所施加適當之力，此在跡線19〇周圍之可熔部 伤184隻形或犬出，且將複合凸塊18〇機械地鎖定至基板 M2。此機械互鎖是由於可熔部份184較跡線為軟之性 質所形成。在回焊期間，此在複合凸塊180與基板192間 機械互鎖將凸塊保持至基板，即此凸塊與基板並不會 失去接觸。因此’將複合凸塊180與基板192配對，以減 少凸塊連接故障。 藉由Sa粒與基板間互連所產生任何應力，會造成晶粒 損壞或故障。此晶粒包含低介電常數（k)材料，其容易受 來自熱所產生應力之損壞。此變尖之複合凸塊1 80可以 :低在半導體晶/粒188上之互連壓力，且導致對於低介電 吊數⑻材料較少損壞，以及晶粒較低故障率。 21 201133664 以上已經詳細說明本發明之一或更多個實施例， 此技術人士瞭解’可以對於此等實施例作修正與調整 不會偏離以下申請專利範圍中所設定本發明之範圍。 【圖式簡單說明】 導體晶粒與跡線之間所形成傳 圖1說明在一基板上半 統互連之橫截面圖； 圖2說明經由焊料遮罩開口在跡線上所形成傳統 之頂視圖； 至其表面 圖3說明一種印刷電路板（pCB)，其具有安裝 之不同形式封裝； 細節； 圖4a-4d說明安裝至pCB之典範半導體封|之進—步 互連； 圖5說明形成於基板上半導體晶粒與跡線間所形成 之 圖6a-6c說明沿著跡線所形成整合凸塊墊； 圖7說明於基板上整纟凸塊墊之陣列中所間隙地形 焊料遮罩補綴； 圖8說明在回焊期間在整合凸塊墊上所形成之凸塊， 其具有由焊料遮罩補綴所限制之凸塊材料； 及 圖9a-9b說明具有不可熔基底與可熔蓋之複合互連；以 互連 圖10a-10b說明具有不可熔基底與可熔蓋之尖細複合 22 201133664 【主要元件符號說明】 10 半導體晶粒 12 凸塊 18 凸塊墊 20 跡線 26 焊料遮罩 28 登記開口 30 基板 50 電性裝置 52 印刷電路板（PCB) 54 信號跡線 56 接線封裝 58 覆晶 60 球格柵陣列（BGA) 62 突起晶片載體（BCC) 64 雙内線封裝（DIP) 66 平面格栅陣列（LGA) 68 多晶片模組（MCM) 70 四方形扁平無接腳封裝（QFN) 72 小型方塊平面封 74 半導體晶粒 76 接觸墊 78 中間載體 23 201133664 80 導線 82 接線 84 封膠 88 半導體晶粒 90 載體 92 底部填料 94 接線 96 接觸墊 98 接觸墊 100 模製複合物 102 接觸墊 104 凸塊 106 中間載體 108 主動區域 1 10 凸塊 111 凸塊墊 112 凸塊 114 信號線 1 15 印刷電路板（PCB) 117 球體 118 導電跡線 120 半導體晶粒 122 凸塊墊 130 跡線 24 201133664 132 跡線 136 基板 138 凸塊墊 139 凸塊墊 140 凸塊墊 142 焊料遮罩 144 焊料遮罩補綴 150 凸塊 152 凸塊 160 複合凸塊 162 .不可熔部份 164 可熔部份 166 接觸墊 168 半導體晶粒 170 導線 172 基板 174 模製底層材料 180 複合凸塊 182 不可熔部份 184 可熔部份 186 接觸墊 188 半導體晶粒 190 跡線 192 基板 25 201133664 製底層材料 194 模 26Any combination of semiconductor packages is configured in any combination of the first and second level of packaging, and is coupled to pa I2 along with other electronic components. In some embodiments, the 'electronic device 5' includes a single attached semiconductor package, while other embodiments require multiple interconnect packages. By combining one or more: conductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functions, less expensive components and rationalized processes can be used to fabricate electronic devices. The resulting device is less likely to fail and is less expensive to manufacture, resulting in lower costs for the consumer. Figures 4a-4d show a typical semiconductor package. Figure 4a illustrates the step-by-step details of the DIP 64 mounted on the PCB. The semiconductor die 74 includes: an active region 'which contains an analog or digital circuit that functions as an active device, a passive "conductive layer, and a dielectric layer formed in the die, and is electrically designed according to the power of the die. even. For example, the circuit can include: one or more body-poles, inductors, capacitors, resistors, and other circuit components formed in the active region of the semiconductor die 74. The contact pad % is a layer or a layer of conductive material, such as sho (10), copper (Cu), tin (such as), recorded (9), () or silver (Α §), and is electrically connected to the semiconductor die 74. The components in the DIP 64 assembly are mounted to an intermediate carrier 12 using a gold-stone eutectic layer or an adhesive material such as a thermal epoxy resin. The 201133664 78 ° package includes an insulating package 8. And wiring (2) to provide semiconductor crystal two: = "(10). Wire encapsulation 84 is deposited on the package, which prevents the interconnection of @电电电. Contaminated grain 74 Ge wiring 82 wet rolling with particles into the package and secondary wiring 82 For environmental protection, the servant instructions are installed on the PCB 52. The bc is filled with an underfill or epoxy resin, and the semi-conductor == on the carrier 90. The ten conductors are connected to the sun. The first level between the (four) pads 96 and 98 is interconnected. The molded compound or the knee seal (10) is deposited on the semiconductor to make the octopus to provide physical support and electrical isolation for the device. The process, such as an electrolyte plating or electroless plating process, contacts the crucible (10) on a surface that is connected to the BCC 62 to the coffee 52 - or more conductive signal traces into bumps: the contact of the contact 52 1〇2 is formed in Fig. 4c, the semiconductor die 58 is face down, and is mounted to the intermediate carrier 106 in a level package. The semiconductor clamp 5...: the active region of the first thousand baskets of the day pull 58... Or a digital circuit, which is implemented as a master formed according to the electrical design of the die a moving element, a passive element, a conductive layer, and a dielectric layer. For example, the circuit may include: - or more transistors, diodes, inductors, capacitors, resistors, and other circuit components in the active ... The semiconductor crystal 58 is electrically and mechanically connected to the carrier using bumps 112 via the bumps 11G, electrically and mechanically connected to the BGA 60 to the BGA type second level package PCB 52. Via the bumps 110, Signal lines 114 13 201133664 and block 112 electrically connect semiconductor die 58 to conductive signal traces 54 in pcb 52 » deposit molding compound or sealant 16 on semiconductor die 58 and carrier 106 In order to provide physical support and electrical isolation for the device. The flip chip semiconductor device provides a short conductive path from the active device on the semiconductor die 58 to the conductive on the PCB 52 to shorten the signal transmission distance. Reducing the capacitance' and improving the performance of the entire circuit. In another embodiment, the flip chip type first level package can be used to electrically and mechanically straighten the semiconductor die 58 without the intermediate carrier 106. Connected to the PCB 52. In another embodiment, the active region 1A8 of the semiconductor die 58 is mounted directly down to the PCB 1 15, ie without an intermediate carrier, as shown in the figure. Using evaporation, electrolyte plating A bump pad 111 is formed on the active region 1 〇 8 by electroless plating, screen printing or other suitable metal deposition process. The bump pad 111 is connected to the active and passive circuits by conduction in the active region 108. The bump pad lu may be aluminum (A1), tin (Sn), nickel (N 〇, gold (Au), silver (Ag) or steel (Cup uses evaporation, electrolyte plating, electrodeless electrode, ball drop or wire) In the screen printing process, a conductive bump material is deposited on the bump 塾 (1) or the conductive track m in the PCB U5. The bump material may be aluminum (A1), tin (Sn), nickel (Ni), gold (Au), silver (Ag), lead, copper (Cu), bismuth (Bl), solder, and combinations thereof, and Selective flux material. For example, the material of the block may be eutectic Sn/pb, high lead solder, or lead-free solder. The bump material is bonded to the between the die bump pads on the PCB 1 15 and the conductive stub 18 using a suitable attach or bonding process. In one embodiment, the bump material is reflowed by heating the material above its dazzle, 201133664 to form a sphere or bump 丨 1 7 ^ This flip-chip semiconductor device provides active from the semiconductor 'die 58 The short conductive path of the component to the conductive traces 118 on the PCB 115 reduces signal transmission, reduces capacitance, and achieves overall better circuit performance. Figure 5 illustrates a cross-sectional view of a portion of a flip-chip semiconductor die 12 having bump pads 22. Traces 130 and turns 32 are formed on substrate 136. As shown in Figure 6a, traces 130 and 132 are straight electrical conductors with integrated bump pads 8. This integrated bump pad 13 8 is collinear with traces 13 0 and 1 3 2 . Alternatively, traces 130 and 132 may have a circular integrated bump 塾 139' as shown in Figure 6b or a rectangular integrated bump pad ι4, as shown in Figure 6c. This integrated bump pad is typically placed in an array to achieve maximum interconnect density and capacity. A solder mask 142 is deposited on a portion of traces 1 30 and 1 32 in FIG. However, the solder mask 142 is not formed on the integrated bump pad 138. Therefore, there is no SR〇 for each bump pad on the substrate, as found in the prior art of Fig. 2. In the array of integrated bump pads 138, i.e., between adjacent bump pads, a solder mask patch 144 that is not wet is formed over the substrate 136. A solder mask patch may also be formed on the semiconductor die 10 in an array of die bump pads 122. More generally, in any configuration, the solder mask patch is formed very close to the integrated bump pads to avoid escaping to the less wet regions. FIG. 8 shows the bumps 150 and 152 formed on the integrated bump pads 138 and is limited by the dip mask patch 144. The conductive bump material is deposited on the die bump pad 122 or the bump bump pad 138 using an evaporation, electrolyte plating, electroless plating, ball drop or screen printing process. The bump material may be aluminum (ITO), tin (Sn), nickel (Ni), gold (Au), silver (Ag), lead (Pb), bismuth (Bi), copper (Cu), solder, and combinations thereof. And a selective flux solution. For example, the bump material can be a common sa Sn/Pb, a lead solder, or a lead-free solder. The bump material is bonded to the integrated bump pads 38 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spheres or bumps 150 and 152. In some applications, the bumps 150 and 152 are reflowed a second time to improve electrical contact to the die bump pads 122 and the integrated bump pads 138. The bumps can also be press bonded to the die bump pads 122 and the integrated bump pads 138. Bumps 15A and 152 represent a form of interconnect structure that can be formed on integrated bump pads 138. This interconnect structure can also use stud bumps, microbumps, or other electrical interconnects. In high routing density applications, it is desirable to minimize the separation spacing. In order to reduce the distance between the traces 130 and 132, the bump material is reflowed without a solder mask around the integrated bump pad 138. The reduction in the spacing between the traces 13〇 and 1 3 2 can be achieved by removing the solder mask used to limit solder reflow and the associated S around the bumps, ie by no solder The mask is used to re-weld the bump material. Solder mask 142 may be formed on traces 〇3 and 132 and one portion of substrate 136 and away from integrated bump pads 3 8, as shown in FIG. However, the solder mask 142 may not be formed on the integrated bump pad 138. That is, one portion of the traces 130 and 132 that are designed to mate with the bump material does not form SR0 in the solder mask 142. In addition, a solder mask patch 144 is formed on the substrate 136 with a gap 16 201133664 in an array of integrated bump pads 138. This solder mask complement i44 is a non-wettable material. This solder mask patch 144 may be the same material as the solder mask (4) and coated during the same processing step; or may be of the same material as the mask 142, but coated during different processing steps. The solder mask patch 144 can be formed by selective etching, plating, or other processing of the integrated bumps 138 "parts of the traces or turns in the array. The solder mask patch (4) limits the solder flow to the integrated bump pads 138 and prevents the conductive bumps (4) from leaking into adjacent structures. When the bump material is reflowed with the solder mask patch H4 disposed in the array of integrated bump pads 138, the wet and surface tension causes the bump material to be confined and retained: the die bump pad 122, integrated The bump pads 138, and the portions between the portions of the substrate 136 that are directly adjacent to the traces 130 and 132 are substantially in the occupied space of the integrated bump pads 138. To achieve the desired limiting properties, the bump material can be immersed in the flux solution prior to placing the bump material on the die bump pad 122 or the integrated bump pad 138 to selectively cause The area of contact of the bump material is more wet than the area around traces 130 and 132. Since the flux solution is wettable|±negative, the refining bump material remains substantially confined to the area defined by the bump pads. This bump material does not flow to the less wettable area. The bump material does not form a thin oxide layer or other insulating layer on the less wet areas. Therefore, no solder mask 142 is required around the die bump pads 22 or the integrated bump pads 38. Since the SRO' is not formed around the die bump pad 122 or the integrated bump pad 138, the traces 1 3 〇 and 1 32 can be formed at a finer pitch, that is, the 17 201133664 traces 1 30 and 1 32 can be set closer. Adjacent structures without contact and forming an electrical short. Assuming the same solder registration design rule, the distance between traces 130 and 132 is given as p^.iD + w^, D is the bottom diameter of bumps 150-152, and W is trace 13 〇 with the width of 132. In one embodiment, given a bump diameter of 100 々 m and a trace width of 2 〇 # m, the minimum separation spacing of this trace 1 30 and 1 32 is 65 # as found in the prior art. This bump formation eliminates the need to provide a hgament spacing of solder mask material between adjacent openings to the minimum soluble SRO. In another embodiment, a composite interconnect is formed between the die bump pads and the integrated bump pads to achieve the desired bump material. In Fig. 9a 9b, the composite bump 160 has a non-meltable portion ι62 and a fusible portion ι64. The non-meltable portion 1 62 forms part of the larger composite bump i 6 较 than the fusible portion i 64 . This non-fusible portion 162 is secured to the contact pads or interconnect locations 166 of the semiconductor die 72. The fusible portion 164 is disposed on the conductor or trace 17 of the substrate Π 2 in Figure 9a and is in physical contact with the conductor n〇 for reflow. As shown in Figure 9b, the fusible portion 164 collapses around the wire 170 during reflow due to heat or applied pressure. This non-meltable portion 162 does not melt or deform during reflow, and retains its original form and shape. The size of the non-meltable portion 丨62 can be designed to provide a separation distance between the semiconductor crystal 168 and the substrate 172. A coating such as a copper organic weldable preservative (0SP) can be applied to the substrate 172. A molded bottom material 174 is deposited between the semiconductor die 168 and the substrate 172 to fill the gap between the die and the substrate. The non-fusible portion 162 and the fusible portion 164 of the composite bump 160 are made of 18 201133664 different bump materials. The non-dazzable portion 162 can be gold, copper, recorded, high ship solder or staggered tin alloy. The fusible portion 164 can be tin, an error-free alloy, a tin-silver alloy, a tin-silver-copper alloy, a tin-silver-indium alloy, a eutectic solder, or other tin alloys having silver, copper, or lead. 8. Select the height or volume of the fusible bump material relative to the non-meltable base material to ensure that it is limited by surface tension. During the retracement period, the sessile material is confined around the non-meltable base material due to the solder mask patch. During the reflow process, the dazzling bump material around the non-refinable substrate also maintains the die arrangement. Typically, the height of the composite interconnect is less than or equal to the diameter of the bump. In some cases, the height of the composite interconnect is greater than the diameter of the interconnect. In an embodiment, the bump base is given a (four) core diameter, the south of the non-fusible substrate is about 45//m, and the height of the fusible cover is about 35 " m. This molten bump material remains substantially confined in the area defined by the bump pads due to the solder mask patch and because of the volume of bump material that is deposited to form the composite bumps. The composite bump includes: a non-meltable substrate and a fusible cover, the composite bump being selected such that the surface tension generated is sufficient to substantially retain the bump material in the footprint of the bump pad and prevent it from flowing out to unwanted Adjacent area. Therefore, a solder mask patch having an array of bumps is formed in a gap to reduce the trace pitch and increase the routing density. During the reflow process, a large number (e.g., thousands) of composite bumps 160 on the semiconductor die 168 are attached to interconnected locations on the trace 170 of the substrate 172. Some of the bumps 1 60 may not be properly connected to the substrate 1 72, particularly if the die 1 68 is warped. Recall that the composite bump 1 60 is greater than 19 201133664 trace 1 70, with the appropriate force applied, the fusible portion 164 around the trace 丨 7 变形 deforms or protrudes 'and the composite bump 16 is mechanically Locked to the substrate 1 72. This mechanical interlock is due to the fact that the fusible portion 164 is softer than the trace 17 turns. During the reflow process, the mechanical interlock between the composite bumps 〇6〇 and the substrate 丨72 maintains the bumps to the substrate, i.e., the bumps do not lose contact with the substrate. Therefore, the composite bump 160 is paired with the substrate 172 to reduce the bump connection failure. In another embodiment, the composite interconnect between the die bump pads and the integrated bump pads is tapered. As shown in Fig. a_丨〇 (1), the composite bump 180 has a non-meltable portion 182 and a fusible portion 丨 84. The non-refinable portion 182 constitutes a more fusible portion 184. A portion of the large composite bump 丨 8 。. The non-fusible portion 182 is secured to the contact pad or interconnect location 186 of the semiconductor die 188. The fusible portion 184 is disposed on the substrate 192. 190 is 'and is in physical contact with the wire 1 90 for reflow. The composite bump 180 is tapered over the trace 190, i.e., the composite bump has a domed shape that is longer along the length of the trace 190 And across the trace 19 〇 is narrower. The tapered portion of the composite bump 180 is generated along the length of the trace 19 (). Figure 10a shows the tapered portion that is narrowed with the trace 190. Figure i〇b is perpendicular to Figure 10a and shows the longer portion of the domed composite bump 180. As shown in Figures 10c and 10d, the fusible portion 184 is due to heat or pressure. It collapses around the wire 190 during reflow. This non-meltable part ι82 does not melt or deform during reflow and maintains its form and shape. This non-meltable can be designed The portion 182 is sized to provide a separation distance between the semiconductor die I" and the substrate 192. A coating such as copper organic solderable 20 201133664 preservative (OSP) can be applied to the substrate 192. A molded underlayer material 194 is deposited Between the semiconductor die 188 and the substrate 192, a gap between the die and the substrate is filled. The non-meltable portion 182 and the fusible portion 184 of the composite bump 180 are made of different bump materials. The molten portion 182 may be gold, copper, nickel, high-lead solder, or a lead-tin alloy. The fusible portion 丨84 may be tin, lead-free alloy, tin-silver alloy, tin-silver steel alloy, tin-silver-indium alloy, eutectic. Solder, or other tin alloy with silver, copper, or lead. During the reflow process, a large number (eg, thousands) of composite bumps 8 on the semiconductor die 188 are attached to: traces of the substrate 192 The interconnection position on the line 19〇. Some of the bumps 8〇 may not be properly connected to the substrate 192, especially if the die 188 is warped, recalling that the composite bump 18 turns larger than the trace 190 to be applied With proper force, this is 184 in the fusible part around the trace 19〇 Shape or canine out, and mechanically lock the composite bump 18〇 to the substrate M2. This mechanical interlock is formed because the fusible portion 184 is softer than the trace. During reflow, this is in the composite bump The mechanical interlock between the 180 and the substrate 192 holds the bump to the substrate, that is, the bump does not lose contact with the substrate. Therefore, the composite bump 180 is paired with the substrate 192 to reduce the bump connection failure. Any stress generated by interconnection with the substrate can cause grain damage or failure. This die contains a low dielectric constant (k) material that is susceptible to damage from heat generated stress. 80 can: low interconnect pressure on the semiconductor crystal/particle 188 and result in less damage to the low dielectric count (8) material and lower die failure rate. 21 201133664 One or more embodiments of the present invention have been described in detail above, and it is understood by those skilled in the art that the present invention may be modified and modified without departing from the scope of the invention as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a cross-sectional view of a semiconductor interconnect on a substrate; Figure 2 illustrates a conventional top view formed on a trace via a solder mask opening. Figure 3 shows a printed circuit board (pCB) with different forms of mounting; details; Figures 4a-4d illustrate the step-by-step interconnection of a typical semiconductor package mounted to pCB; Figure 5 illustrates the formation Figures 6a-6c formed between the semiconductor die and the traces on the substrate illustrate integrated bump pads formed along the traces; Figure 7 illustrates the interstitial solder mask fills in the array of trim bump pads on the substrate; Figure 8 illustrates bumps formed on the integrated bump pads during solder reflow having bump material constrained by solder mask patches; and Figures 9a-9b illustrate composite interconnects with a fusible substrate and a fusible cover A tapered composite having a non-meltable base and a fusible cover is illustrated in the interconnection diagrams 10a-10b. 201133664 [Major component symbol description] 10 Semiconductor die 12 Bump 18 Bump pad 20 Trace 26 Solder mask 28 Registration opening 30 substrate 50 Device 52 Printed Circuit Board (PCB) 54 Signal Trace 56 Wiring Package 58 Flip Chip 60 Ball Grid Array (BGA) 62 Projected Wafer Carrier (BCC) 64 Dual Internal Package (DIP) 66 Planar Grid Array (LGA) 68 Multi-Chip Module (MCM) 70 Quad Flat No-Terminal Package (QFN) 72 Small Square Plane Seal 74 Semiconductor Die 76 Contact Pad 78 Intermediate Carrier 23 201133664 80 Wire 82 Wiring 84 Sealant 88 Semiconductor Die 90 Carrier 92 Bottom Filler 94 Wiring 96 Contact Pad 98 Contact Pad 100 Molded Composite 102 Contact Pad 104 Bump 106 Intermediate Carrier 108 Active Area 1 10 Bump 111 Bump Pad 112 Bump 114 Signal Line 1 15 Printed Circuit Board (PCB) 117 Sphere 118 Conductor trace 120 Semiconductor die 122 Bump pad 130 Trace 24 201133664 132 Trace 136 Substrate 138 Bump pad 139 Bump pad 140 Bump pad 142 Solder mask 144 Solder mask patch 150 Bump 152 Bump 160 Composite bump 162. Non-meltable portion 164 Fusible portion 166 Contact pad 168 Semiconductor die 170 Wire 172 Substrate 174 Molded underlying material 180 Composite bump 182 No Melting fusible portion 184 contacts pad portion 186 of the semiconductor die 188 substrate 190 trace 192 25 201 133 664 194 mold base material 26 made of