TWI567864B - 在基板上形成高繞線密度互連位置的半導體裝置及方法 - Google Patents
在基板上形成高繞線密度互連位置的半導體裝置及方法 Download PDFInfo
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- TWI567864B TWI567864B TW100102451A TW100102451A TWI567864B TW I567864 B TWI567864 B TW I567864B TW 100102451 A TW100102451 A TW 100102451A TW 100102451 A TW100102451 A TW 100102451A TW I567864 B TWI567864 B TW I567864B
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Description
本申請案是2010年4月9日申請的美國專利申請案號12/757,889的一部分接續案,並且根據美國專利法第120條主張前述專利申請案的優先權。
本發明係有關於半導體裝置,並且尤其係有關於一種在基板上形成高繞線密度互連位置的半導體裝置及方法。
半導體裝置常見於現代的電子產品中。半導體裝置在電性構件的數目及密度上有所不同。離散的半導體裝置一般包含一種類型的電氣構件,例如,發光二極體(LED)、小信號的電晶體、電阻器、電容器、電感器、以及功率金屬氧化物半導體場效電晶體(MOSFET)。積體化半導體裝置通常包含數百個到數百萬個電性構件。積體化半導體裝置的例子包含微控制器、微處理器、電荷耦合裝置(CCD)、太陽能電池以及數位微鏡裝置(DMD)。
半導體裝置可執行廣大範圍的功能,例如:信號處理、高速的計算、傳送及接收電磁信號、控制電子裝置、轉換太陽光成為電力以及產生用於電視顯示器之可見的投影。半導體裝置可見於娛樂、通訊、電力轉換、網路、電腦以及消費性產品的領域中。半導體裝置亦可見於軍事應用、航空、汽車、工業用控制器以及辦公室設備。
半導體裝置係利用半導體材料的電氣特性。半導體材料的原子結構係容許其導電度可藉由一電場或基極電流的施加或是透過摻雜的製程來操控。摻雜係將雜質引入半導體材料中以操控及控制半導體裝置的導電度。
一半導體裝置係包含主動及被動的電氣結構。包含雙載子及場效電晶體的主動結構係控制電流的流動。藉由改變摻雜的程度以及一電場或基極電流施加的位準,電晶體不是提升就是限制電流的流動。包含電阻器、電容器及電感器的被動結構係產生執行各種電氣功能所必要的一種電壓及電流間之關係。被動及主動結構係電連接以形成電路,此係使得半導體裝置能夠執行高速的計算以及其它有用的功能。
半導體裝置一般是利用兩種複雜的製程,亦即,前端製造及後端製造來製成,每一種都牽涉到可能有數百道的步驟。前端製造係牽涉到在一半導體晶圓的表面上複數個晶粒的形成。每個晶粒通常是相同的並且包含由電連接主動及被動構件所形成的電路。後端製造係牽涉到從晶圓成品單切(singulating)個別的晶粒及封裝該晶粒以提供結構的支撐及環境的隔離。
半導體製造的一項目標是生產出更小的半導體裝置。越小的裝置通常消耗更低的電力,具有更高的效能,並且可更有效率地被生產出。此外,越小的半導體裝置具有更小的覆蓋區(footprint),此係為更小的最終產品所期望的。更小的晶粒尺寸可藉由在前端製程中以更小及更高密度的主動及被動構件來產生晶粒的改良而達成。後端製程可藉由在電氣互連及封裝材料上的改良以產生更小的覆蓋區之半導體裝置封裝。
在習知的覆晶類型封裝中,一半導體晶粒係以該晶粒的主動側面對一封裝基板來安裝到該基板。半導體晶粒中的電路與基板中的電路之互連傳統是藉由凸塊來完成,該些凸塊係附接到該晶粒上之一陣列的互連墊,並且連結到該基板上之一對應互補的陣列的互連墊,經常被稱為基板上的抓取(capture)墊。
積體電路上的電子特徵之平面密度已巨幅增長,並且具有更大密度的電路特徵之半導體晶粒亦可能有更大密度的用於和封裝基板互連的位置。
該封裝係連接至例如是印刷電路板或主機板之下面的電路,此係藉由在該封裝及下面的電路間之第二層級的互連來達成。該第二層級的互連具有比覆晶的互連大的間距,因此基板上的繞線傳統上是成扇形展開。重大的技術進步已使得微細線路與空間之構造成為可能。在該傳統的配置中,相鄰的墊間之空間係限制可自陣列中較內側之抓取墊逸散(escape)的線路之數目。在半導體晶粒下方的抓取墊及封裝的外部接腳之間扇形展開的繞線傳統上係被形成在該封裝基板內的多個金屬層上。對於複雜的互連陣列而言,可能需要具有多層的基板以達成在該晶粒墊及該封裝之第二層級的互連之間的繞線。
多層的基板係昂貴的,並且在習知的覆晶建構中,光是基板通常就佔去超過一半的封裝成本。多層基板的高成本一直都是限制覆晶技術在主流產品中繁衍的一項因數。在傳統的覆晶構造中,該逸散的繞線圖案通常會帶來額外的電性寄生現象,因為該繞線包含在信號傳送路徑中短的路線之無屏蔽的佈線以及佈線層間的貫孔(via)。電性寄生現象可能嚴重地限制封裝的效能。
可藉由利用一熔化製程以將例如是焊料凸塊的凸塊接合到對應的抓取墊的配接表面之上來達成覆晶互連,此被稱為抓取墊上凸塊(BOC)互連。在BOC設計中有兩個特點是顯然的:第一,需要相對大的抓取墊來和半導體晶粒上的凸塊配接,以及第二,需要通常為焊料遮罩的一種絕緣材料以限制焊料在互連製程期間的流動。該焊料遮罩開口係界定熔化的焊料在抓取墊的輪廓,亦即為焊料遮罩界定的、或者該焊料輪廓可以不是由該遮罩開口所界定,亦即非焊料遮罩界定的。在後者的情形中,該焊料遮罩開口顯著大於抓取墊。因為用於界定焊料遮罩開口的技術對於一焊料遮罩界定的凸塊配置會具有寬的容限範圍,所以抓取墊必須是大的,通常是遠大於遮罩開口的設計尺寸,以確保該遮罩開口將會位在該墊的配接表面上。抓取墊的寬度或直徑可差不多為線路寬度的兩倍到四倍。較大的抓取墊寬度會導致頂端基板層上之繞線空間大量的損失。尤其,逸散的繞線間距遠大於基板技術所能提供的最細線路間距。大量的墊必須藉由通常是在晶粒的覆蓋區下方且從所論及的墊發散出之短的短線段(stub)及貫孔而被繞線在下方的基板層上。
在習知的焊料遮罩界定的BOC互連之一典型的例子中,抓取墊具有約140μm的直徑,並且焊料遮罩開口具有約90μm的直徑,並且繞線線路的寬大約是25-30μm。用於凸塊至晶粒墊的安裝之配接表面(亦即,在凸塊及晶粒墊間的介面處)的直徑係藉由該焊料遮罩開口界定為具有約90μm的直徑。
習知的BOC互連佈局的一些例子係以一覆晶封裝的部份10及20被展示在圖1及2中。圖1中的部分截面圖係以一平行於封裝基板表面的平面,沿著圖2中的線1-1’所取得的。圖2中的部分截面圖係以一垂直於封裝基板表面的平面,沿著圖1中的線2-2’所取得的。一些特點係被展示為如同透明一般,但是圖1中許多的特點係被展示為部份被覆蓋的特點所遮蔽。
封裝基板的晶粒附接表面係包含一形成在基板12之上的一介電層上之金屬或層。該金屬層係被圖案化以形成線路或導線13及抓取墊14。一絕緣層或焊料遮罩16係覆蓋基板12的晶粒附接表面。該焊料遮罩16通常是由一種可光界定的材料所製成,該可光界定的材料係藉由光阻而被圖案化以使得抓取墊14的配接表面露出。附接至半導體晶粒18的主動側上的墊之互連凸塊15係接合到基板12上之對應的抓取墊14,以在該晶粒上的電路以及該基板上的導線之間形成合適的電互連。在回焊後的焊料冷卻以建立該電連接之後,一底膠填充(underfill)材料17係被引入在半導體晶粒18及基板12之間的空間,以機械地穩定該互連並且保護在該晶粒及基板之間的特點。
圖1係展示基板12之上方的金屬層中的信號逸散線路13,該些信號逸散線路13係從其個別的抓取墊14繞線橫跨由虛線11所指出的晶粒邊緣位置而離開晶粒覆蓋區。該些信號線路13可具有約112微米(μm)的逸散間距PE。一種30μm/30μm設計規則典型是用於例如是圖1所示的配置中的線路13。線路13標稱為30μm寬,並且緊密靠在一起時的間距可為30μm。抓取墊14通常是線路寬度的三倍大,並且抓取墊具有90μm的標稱寬度或直徑。在該焊料遮罩中的開口係大於墊,其具有135μm的標稱寬度或直徑。
圖1及2係展示一非焊料遮罩界定的焊料輪廓。當在該晶粒上的凸塊之可熔的材料熔化時,該熔化的焊料傾向至潤濕導線及抓取墊的金屬,並且該焊料傾向於流出到任何未遮蔽之鄰接的金屬表面之上。該焊料傾向於沿著鄰接的導線13流動,而在此該焊料流動係受到在圖1中的位置19處之焊料遮罩的限制。在該墊的非焊料遮罩界定的焊料輪廓在圖2中是明顯的,其中凸塊15的部份29係被展示為已經流動到抓取墊14的側邊之上並且向下流到基板12的介電層的表面。該非焊料遮罩界定的輪廓並不限制焊料在該表面之上及向下到該抓取墊的側邊之上的流動,除非在該墊之處有實質過量的焊料,否則焊料的流動受到基板12的介電質表面通常可不被該熔化的焊料潤濕的實情所限制。圖1所示的配置中之抓取墊密度的下限是由製造可靠的窄遮罩結構的遮罩形成技術之能力以及在相鄰的遮罩開口間設置遮罩結構的需求和其它因素來決定。逸散密度的下限是額外由逸散導線從位在較中心的抓取墊繞線在位於較周邊的抓取墊之間的需求和其它因素來決定。
圖3係以類似於圖2的截面圖展示一焊料遮罩界定的焊料輪廓。半導體晶粒38係被展示藉由凸塊35黏著到抓取墊34的配接表面之上,該抓取墊34是和線路或導線33一起藉由圖案化基板32的一介電層的晶粒附接側上的一金屬層來加以形成的。在該回焊的焊料冷卻以建立電連接之後,一底膠填充材料37係被引入在晶粒38及基板32之間的空間以機械地穩定該互連並且保護在該晶粒及基板之間的特點。抓取墊34係比在圖1及2的例子寬,並且焊料遮罩開口係小於抓取墊,因而焊料遮罩材料係覆蓋每個抓取墊的配接表面的側邊及部份(如同位置39所示)以及導線33。當凸塊35被帶往和個別的抓取墊34的配接表面接觸並且接著被熔化時,其中焊料遮罩材料36係限制該熔化的焊料的流動,因而該焊料輪廓的形狀是由抓取墊34之上的遮罩開口的形狀及尺寸所界定。
對於在不影響到電功能或製造可靠度下最小化一基板上的互連位置以增加繞線密度係存在著需求。於是,在一實施例中,本發明是一種製造半導體裝置之方法,其係包括以下步驟:提供半導體晶粒,其係具有形成在該半導體晶粒的表面上的接觸墊之上的複數個凸塊;提供基板;在該基板之上形成具有互連位置的複數個導電線路,該些互連位置具有寬度大於該些凸塊及接觸墊之間的接觸介面的寬度的20%且小於該接觸介面的寬度的80%;將該些凸塊連結至該些互連位置以使得該些凸塊覆蓋該些互連位置的一頂表面及側表面;以及在該半導體晶粒及基板間之該些凸塊的周圍沉積封裝材料。
在另一實施例中,本發明是一種製造半導體裝置之方法,其係包括以下步驟:提供具有複數個接觸墊的半導體;提供基板;在該基板之上形成具有互連位置的複數個導電線路;在該半導體晶粒上的該些接觸墊以及該基板上的該些互連位置之間形成複數個互連結構,以使得該些互連結構覆蓋該些互連位置的頂表面及側表面;以及在該半導體晶粒及基板之間沉積封裝材料。
在另一實施例中,本發明是一種製造半導體裝置之方法,其係包括以下步驟:提供半導體晶粒;提供基板;在該基板之上形成具有互連位置的複數個導電線路;以及形成複數個互連結構以將該半導體晶粒連結到該基板上的該些互連位置。該些導電線路具有藉由可被設置在該基板上之相鄰導電線路間的最小間隔以及該些互連位置的寬度所決定的間距,其係提供繞線密度等於該導電線路的間距。
在另一實施例中,本發明是一種半導體裝置,其係包括具有複數個接觸墊的半導體晶粒。具有互連位置的複數個導電線路係被形成在基板之上。複數個互連結構係被形成在該半導體晶粒上的該些接觸墊以及該基板上的該些互連位置之間。該些互連結構係覆蓋該些互連位置的頂表面及側表面,並且該互連位置的寬度係大於在該互連結構及接觸墊之間的接觸介面的寬度的20%,並且小於該接觸介面的寬度的80%。封裝材料係沉積在該半導體晶粒及基板之間。
本發明在以下參考圖式的說明中係以一或多個實施例加以描述,其中相同元件符號代表相同或類似元件。儘管本發明是依據達成本發明目的之最佳模式描述,但熟習此項技術者將瞭解本發明欲涵蓋如隨附申請專利範圍所界定之可內含於本發明之精神及範疇內的替代物、修改及等效物以及如以下揭示內容及圖式所支持之其等效物。
半導體裝置一般是使用兩個複雜的製程來製造:前端製造與後端製造。前端製造係牽涉到在半導體晶圓表面上形成多個晶粒。該晶圓上之各晶粒含有主動及被動電性構件,其係電連接以形成功能電路。諸如電晶體及二極體之主動電性構件係具有控制電流流動之能力。諸如電容器、電感器、電阻器及變壓器之被動電性構件係產生執行電路功能所必要的一種電壓及電流間之關係。
被動及主動構件藉由一系列製程步驟形成於半導體晶圓表面上,包括摻雜、沉積、微影、蝕刻及平坦化。摻雜係藉由諸如離子植入或熱擴散之技術將雜質引入半導體材料中。摻雜製程改變主動裝置中半導體材料之導電度,從而將該半導體材料轉變成絕緣體、導體,或是響應於電場或基極電流而動態地改變該半導體材料之導電度。電晶體含有摻雜類型及程度不同之區域,其視需要來加以配置以使該電晶體能夠在施加電場或基極電流時促進或限制電流流動。
主動及被動構件係由具有不同電特性之材料層形成。該等層可藉由多種沉積技術形成,該些沉積技術部分是由所沉積之材料類型決定的。舉例而言,薄膜沉積可包括化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解的電鍍及無電的電鍍製程。每個層一般是經圖案化以形成主動構件、被動構件或各構件間電連接的部分。
該些層可使用微影進行圖案化,其牽涉到使光敏材料(例如光阻)沉積於待圖案化的層之上。使用光以將圖案自光罩轉印於光阻上。使用一溶劑移除光阻圖案曝光之部分,露出待圖案化之下層部分。移除該光阻之其餘部分,留下一經圖案化的層。或者,某些類型的材料係使用諸如無電的電鍍及電解的電鍍之技術藉由使材料直接沉積於由先前沉積/蝕刻製程所形成的區域或空隙中而加以圖案化。
在現有圖案之上沉積一材料薄膜可能會放大下面的圖案且產生非均勻平坦的表面。生產較小且較密集封裝之主動及被動構件需要均勻平坦的表面。可使用平坦化以自晶圓表面移除材料且產生均勻平坦的表面。平坦化係牽涉到用拋光墊拋光晶圓的表面。在拋光期間將研磨材料及腐蝕性化學品添加至晶圓的表面。研磨劑的機械作用與化學品的腐蝕作用組合可移除任何不規則的表面構形,從而產生均勻平坦的表面。
後端製造係指將晶圓成品切割或單切成個別晶粒且接著封裝該晶粒以提供結構的支撐及環境的隔離。為了單切晶粒,沿著晶圓非功能區(稱為切割道或劃線)將晶圓劃痕並切斷。使用雷射切割工具或鋸條單切晶圓。在單切之後,將個別晶粒安裝於一封裝基板上,該封裝基板包括接腳或接觸墊以供與其他系統構件互連。接著使半導體晶粒上所形成之接觸墊連接至封裝內之接觸墊。該電連接可由焊料凸塊、柱形凸塊、導電膏或焊線(wirebond)形成。使一封裝材料或其它模製材料沉積於封裝之上以提供物理支撐及電隔離。接著將成品封裝插入一電系統中,且使半導體裝置之功能可供其他系統構件利用。
圖4係描繪具有多個安裝於其表面上之半導體封裝的晶片載體基板或印刷電路板(PCB)52之電子裝置50。視應用而定,電子裝置50可具有一種類型之半導體封裝或多種類型之半導體封裝。不同類型之半導體封裝係為了說明之目的而展示於圖4中。
電子裝置50可以是一使用該些半導體封裝以執行一或多種電功能之獨立的系統。或者,電子裝置50可以是一較大系統之子構件。舉例而言,電子裝置50可以是行動電話、個人數位助理(PDA)、數位視訊攝影機(DVC)、或是其它電子通訊裝置的一部份。或者是,電子裝置50可以是一可插入電腦中之顯示卡、網路介面卡或其他信號處理卡。該半導體封裝可包括微處理器、記憶體、特殊應用積體電路(ASIC)、邏輯電路、類比電路、RF電路、離散裝置或其他半導體晶粒或電性構件。小型化及重量減輕是這些產品能夠被市場接受所不可少的。在半導體裝置間的距離必須縮短以達到更高的密度。
在圖4中,PCB 52係提供一般的基板以供安裝在該PCB上之半導體封裝的結構支撐及電氣互連。導電的信號線路54係利用蒸鍍、電解的電鍍、無電的電鍍、網版印刷、或其它適合的金屬沉積製程而被形成在PCB 52的一表面之上或是在層內。信號線路54提供在半導體封裝、安裝的構件、以及其它外部的系統構件的每一個之間的電通訊。線路54亦提供電源及接地連接給每個半導體封裝。
在某些實施例中,一半導體裝置具有兩個封裝層級。第一層級的封裝是一種用於將半導體晶粒機械及電氣地附接至一中間載體的技術。第二層級的封裝係牽涉到將該中間載體機械及電氣地附接至PCB。在其它實施例中,一半導體裝置可以只有該第一層級的封裝,其中晶粒是直接機械及電氣地安裝到PCB上。
為了說明之目的,包含打線接合封裝56及覆晶58之數種類型的第一層級的封裝係被展示在PCB 52上。此外,包含球狀柵格陣列(BGA)60、凸塊晶片載體(BCC)62、雙排型封裝(DIP)64、平台柵格陣列(LGA)66、多晶片模組(MCM)68、四邊扁平無引腳封裝(QFN)70及四邊扁平封裝72之數種類型的第二層級的封裝係被展示安裝在PCB 52上。視系統需求而定,以第一及第二層級的封裝類型的任意組合來組態的半導體封裝的任何組合及其它電子構件可連接至PCB 52。在某些實施例中,電子裝置50包含單一附接的半導體封裝,而其它實施例需要多個互連的封裝。藉由在單一基板之上組合一或多個半導體封裝,製造商可將預製的構件納入電子裝置及系統中。由於半導體封裝包括複雜的功能,因此可使用較便宜構件及流線化製程來製造電子裝置。所產生的裝置不太可能發生故障且製造費用較低,從而降低消費者成本。
圖5a-5c係展示範例的半導體封裝。圖5a係描繪安裝在PCB 52上的DIP 64之進一步的細節。半導體晶粒74係包括一含有類比或數位電路的主動區域,該些類比或數位電路係被實施為形成在晶粒內之主動裝置、被動裝置、導電層及介電層並且根據該晶粒的電設計而電互連。例如,該電路可包含形成在半導體晶粒74的主動區域內之一或多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。接觸墊76是一或多層的導電材料,例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag),並且電連接至形成在半導體晶粒74內之電路元件。在DIP 64的組裝期間,半導體晶粒74係利用一金矽共晶層或例如是熱環氧樹脂的黏著劑材料而被安裝至一中間載體78。封裝主體係包含一種例如是聚合物或陶瓷的絕緣封裝材料。導線80及焊線82係在半導體晶粒74及PCB 52之間提供電互連。封裝材料84係為了環境保護而沉積在該封裝之上以防止濕氣及微粒進入該封裝且污染晶粒74或焊線82。
圖5b係描繪安裝在PCB 52上之BCC 62的進一步細節。半導體晶粒88係利用一種底膠填充或是環氧樹脂黏著材料92而被安裝在載體90之上。焊線94係在接觸墊96及98之間提供第一層級的封裝互連。模製化合物或封裝材料100係沉積在半導體晶粒88及焊線94之上以提供物理支撐及電氣隔離給該裝置。接觸墊102係利用一例如是電解的電鍍或無電的電鍍之合適的金屬沉積製程而被形成在PCB 52的一表面之上以避免氧化。接觸墊102係電連接至PCB 52中的一或多個導電信號線路54。凸塊104係形成在BCC 62的接觸墊98以及PCB 52的接觸墊102之間。
在圖5c中,半導體晶粒58係以覆晶型第一層級的封裝方式面向下安裝到中間載體106。半導體晶粒58的主動區域108係包含類比或數位電路,該些類比或數位電路係被實施為根據該晶粒的電設計所形成的主動裝置、被動裝置、導電層及介電層。例如,該電路可包含一或多個電晶體、二極體、電感器、電容器、電阻器以及主動區域108內之其它電路元件。半導體晶粒58係透過凸塊110電氣及機械地連接至載體106。
BGA 60係以BGA型第二層級的封裝方式利用凸塊112電氣及機械地連接至PCB 52。半導體晶粒58係透過凸塊110、信號線114及凸塊112電連接至PCB 52中的導電信號線路54。一種模製化合物或封裝材料116係沉積在半導體晶粒58及載體106之上以提供物理支撐及電氣隔離給該裝置。該覆晶半導體裝置係提供從半導體晶粒58上的主動裝置到PCB 52上的導電跡線之短的導電路徑,以便縮短信號傳播距離、降低電容以及改善整體電路效能。在另一實施例中,半導體晶粒58可在無中間載體106的情況下,利用覆晶型第一層級的封裝直接機械及電連接至PCB 52。
在覆晶類型的半導體晶粒中,互連是藉由將互連凸塊直接連接到窄的互連墊之上來完成,而不是到習知的抓取墊之上。該窄墊的寬度係根據待連接到該窄墊之上的互連凸塊的基底直徑來加以選出。尤其,該窄墊的寬度係小於該互連凸塊的基底直徑,例如是在約20%至約80%的範圍中。現有的覆晶互連係在基板上提供較有效率的線路繞線。信號繞線可完全被形成在基板的單一金屬層中,以降低基板中的層數目。在單一層中形成該信號線路係允許基板必須符合的貫孔、線及間隔的設計規則中的某些設計放鬆。基板的簡化係大為降低覆晶封裝的整體成本。窄墊上的凸塊(BONP)架構亦有助於從基板設計消除像是貫孔及短線段的特點並且使得用於信號傳送之微帶控制的阻抗電氣環境成為可能,藉此改進效能。
該覆晶互連係使得凸塊附接至半導體晶粒上的互連墊並且配接到基板上之對應的窄互連墊之上。一覆晶封裝係包含一具有附接至在一主動表面中的互連墊凸塊之半導體晶粒以及一在一晶粒附接表面中具有窄互連墊的基板,其中該些凸塊係配接到該些窄墊之上。該BONP互連可在未使用製程中的再熔化階段期間限制熔化的焊料之焊料遮罩下被形成,此係容許有較細的互連幾何。
圖6及8係以分別沿著圖7及9中的線6-6’及8-8’之平行於基板表面的平面取出之概略的部分截面圖來分別展示BONP覆晶互連的一部份。一些特點係被展示為如同透明一般。互連係藉由將凸塊配接到基板上的個別窄互連墊之上而被達成。在此實施例中,限制熔化的流動之功能係在組裝製程的過程中沒有焊料遮罩下被達成,即如以下所述者。圖7係展示如同圖6中的封裝以沿著圖6的線7-7’之垂直於封裝基板表面的平面所取之部分截面圖。圖9係展示如同圖8中的封裝以沿著圖8的線9-9’之垂直於封裝基板表面的平面所取之部分截面圖。
用於BONP基板之逸散的繞線圖案係被展示在圖6及8中。在圖6中,繞線圖案係被配置以用於半導體晶粒,用於互連球的晶粒附接墊係以一靠近晶粒周邊的列被形成在半導體晶粒上。凸塊120係配接到逸散線路122上、在一靠近晶粒覆蓋區的邊緣(由虛線124所指出)之列中對應的窄互連墊之上。在圖8中,繞線圖案係被配置以用於一半導體晶粒,其上的晶粒附接墊係在一靠近晶粒周邊之平行列的陣列中。凸塊126係配接到逸散線路128上、在一靠近晶粒覆蓋區的邊緣(由虛線130所指出)之互補陣列中對應的窄互連墊之上。
在圖6及8中,利用BONP互連可達到的繞線密度可等於基板技術所能提供之最細的線路間距。在一實施例中,在該線路上之互連位置的寬度可以是多達該線路的寬度之1.2倍。該些導電線路具有一藉由可被設置在基板上之相鄰導電線路間的最小間隔以及該互連位置的寬度所決定的間距,其係提供一等於該些導電線路的間距之繞線密度。繞線密度係顯著高於如同圖1-3中所述之習知的BOC配置所達到的繞線密度。習知的抓取墊的寬度通常是線路或導線寬度的兩倍到四倍。
如同圖6及8所描繪的,該BONP互連可提供一顯著較高的信號線路逸散的繞線密度。在圖6中,凸塊120係以細間距被設置,該細間距可等於基板的最細的線路間距。該配置對於組裝製程係造成挑戰,因為凸塊及連結的間距必須是非常細的。在圖8中,凸塊126係被配置在一區域陣列上,此係提供較大的空間給較大的凸塊及連結間距並且減輕組裝製程技術上的挑戰。即使在陣列的實施例中,基板上的繞線線路仍然是具有和周邊列的配置相同的有效間距,此係在沒有犧牲細的逸散繞線間距的優點下減輕細間距的凸塊及連結的負擔。
圖6及7係展示藉由圖案化基板介電層132的一晶粒附接表面上的一金屬層所形成的線路或導線122及窄互連墊131。該窄墊131可被形成為線路122在互連位置處的擴大。一互連墊的寬度Wp是橫跨該線路在互連位置處之擴大的部份的標稱或設計尺寸。基板上的窄互連墊之寬度是根據待連接到該基板的半導體晶粒上的凸塊之凸塊基底寬度或基底直徑來加以建立的。該凸塊基底寬度Wb是凸塊120及晶粒墊133之間大致圓形的接觸介面的標稱或設計直徑。該凸塊以一平行於該凸塊-墊介面的平面來取出的直徑可以大於Wb,即如在圖7及9中所繪者。該互連墊寬度Wp是小於該凸塊基底寬度Wb,例如,Wp可以是小至Wb的20%。在其它實施例中,Wp是在Wb的約20%至約80%的範圍中、或是Wp小於Wb且大於Wb的約25%、或是Wp小於Wb的約60%。
半導體晶粒134的電互連係藉由將凸塊120接合到導線122上的窄互連墊131之上而做成。一窄互連墊係具有一標稱或設計寬度為大約該標稱或線路設計規則寬度的120%,並且窄導線上凸塊的(BONL)互連係包含連接至線路之擴大的部份的凸塊,該擴大的部份係大於該標稱或線路設計規則寬度的約120%且小於該凸塊基底直徑。由凸塊連結到小於該標稱或線路設計規則寬度的約120%的導線之部份所做成的互連係被稱為導線上凸塊(BOL)的互連。
圖8及9係展示藉由圖案化基板介電層137的一晶粒附接表面上的一金屬層所形成的信號逸散線路或導線128以及窄互連墊136。該信號逸散線路128係被繞線橫跨由虛線130指示的晶粒邊緣位置並且遠離該晶粒覆蓋區。該窄墊136可被形成為線路128在互連位置處的擴大。一互連墊的寬度Wp是橫跨該線路在互連位置處之擴大的部份的標稱或設計尺寸。基板上的窄互連墊之寬度是根據待連接到該基板的晶粒上的凸塊之凸塊基底寬度或基底直徑來加以建立的。該凸塊基底寬度Wb是凸塊126及晶粒墊138之間大致圓形的接觸介面的標稱或設計直徑。該互連墊寬度Wp是小於該凸塊基底寬度Wb,並且Wp可以是小至Wb的20%。在其它實施例中,Wp是在Wb的約20%至約80%的範圍中、或是Wp小於Wb且大於Wb的約25%、或是Wp小於Wb的約60%。
半導體晶粒140的電互連係藉由將凸塊126接合到導線128上的窄互連墊126之上而做成。從接近晶粒覆蓋區內部的列中的互連位置穿過晶粒邊緣位置的某些逸散線路142係在較周邊列的互連位置上的凸塊126之間通過。在如圖6-9的實施例中,不需要任何抓取墊及焊料遮罩。
圖10及11係以一平行於基板表面的平面所取的概略截面圖展示BOL覆晶互連的兩個例子。一些特點係被展示為如同透明一般。在此實施例中,一焊料遮罩係被設置,其可具有一在約80μm至90μm的範圍中之標稱遮罩開口直徑。焊料遮罩材料可以此種間距來加以解析,並且尤其基板可用具有90μm開口且具有25μm左右的對準容限的焊料遮罩而相當廉價地做成。在某些實施例中,依據標準設計規則所製成的積層基板(例如四個金屬層的積層)係被使用。線路可為大約90μm的間距,並且窄墊係以一個270μm的區域陣列被配置,此係提供大約90μm之橫跨由虛線146所指出的晶粒覆蓋區的邊緣之有效的逸散間距。
在圖10中,該互連係藉由將凸塊直接配接到被圖案化在基板149的晶粒附接表面上的一介電層上之窄導線或線路148上的窄互連墊147之上而達成。焊料遮罩150係用以限制焊料在遮罩開口151的界限內之流動,此係防止焊料從互連位置沿著該焊料可濕的導線流開。此外,該焊料遮罩可限制熔化的焊料在導線之間流動,此可在組裝製程的過程中被達成。
在圖11中,線路152上的窄墊154係在基板153的晶粒附接表面的一介電層上被圖案化。焊料膏係被設置在導線152上的互連位置154,以提供一用於互連的可熔介質。焊料遮罩156中的開口155係用以界定該膏。該膏係被分配、回焊、並且若必要的話被壓印(coined),以提供均勻的表面來接合該凸塊。該焊料膏可利用如上參考圖10所述的基板,在組裝的過程中施加。或者是,一基板可在組裝前先被設置經適當圖案化的膏。其它用以選擇性地施加焊料至互連位置的方式亦可被利用在在該窄墊上焊料中,其包含無電的電鍍以及電鍍技術。該窄墊上焊料的配置係提供額外的焊料量用於互連,並且於是可提供較高的產品良率,而且亦可以提供較高的晶粒間隙。一種毛細管底膠填充可被利用。
於是,在某些實施例中,該窄墊上焊料的配置係被採用於將具有高熔化溫度的凸塊(例如,用於和陶瓷基板的互連之高鉛的焊料)之半導體晶粒互連到一有機基板之上。該焊料膏可選擇成具有足夠低的熔化溫度,使得該有機基板在回焊期間不會受損。為了在此種實施例中形成該互連,該高熔化溫度的互連凸塊係和窄墊上焊料的位置接觸,並且再熔化係將該窄墊上焊料熔融到該凸塊。在使用不可分解的凸塊及窄墊上焊料的製程之情形中,不需要任何預先施加的黏著劑,因為焊料的位移或流動係受限於只有小量的焊料存在於每個互連的實情。該不可分解的凸塊係避免組裝的倒塌。在其它實施例中,該窄墊上焊料的配置係被採用於具有共晶焊料凸塊的半導體晶粒的互連。
該覆晶互連的形成可藉由提供一具有在晶粒附接表面中形成的窄互連墊之基板以及一具有在主動表面中附接至互連墊的凸塊之半導體晶粒、支撐該基板及晶粒、在該基板上分配一個量的可固化黏著劑以覆蓋該些窄互連墊或是在該晶粒的主動側上分配該可固化黏著劑、以該晶粒的主動側朝向該基板的晶粒附接表面來設置該晶粒、對準該晶粒及基板且朝向彼此地移動使得該些凸塊接觸該基板上之對應的窄互連墊、施加一力以將該些凸塊壓到該些配接的窄墊之上且足以從該凸塊及配接的窄墊間位移該黏著劑。該黏著劑係部分地固化。該焊料係被熔化且接著再度凝固以在該凸塊及窄墊間形成冶金的互連。
一用於達成BONP互連的實施例係被展示在圖12a-12c中。在圖12a中,基板112具有在晶粒附接表面159上的至少一介電層且具有一金屬層。該金屬層係被圖案化以在該晶粒附接表面上提供電路,特別是具有用於互連的位置之線路或導線上的窄互連墊160。基板158係被支撐在一載體或台162上,其中和晶粒附接表面159相反的基板表面係面對該支台。一個量的封裝樹脂163係被分配在基板158的晶粒附接表面159之上,以覆蓋導線上的窄互連墊160。半導體164在主動側167上具有附接至晶粒墊的凸塊166。凸塊166包含一可熔的材料,該可熔的材料係接觸該些窄墊的配接表面。一包含夾頭169的取放型工具168係藉由夾頭和晶粒背面170的接觸來拾取半導體晶粒164。半導體晶粒164係利用取放型工具168,以晶粒的主動側167朝向基板158的晶粒附接表面而被設置成面對基板158。半導體晶粒164及基板158係被對準,並且將其中一個朝向另一個移動,即如箭頭M所示,因而凸塊166接觸到基板上的線路或導線之對應的窄互連墊160。如同在圖12b中所示,一力F係被施加以將凸塊166壓到在導線上的窄墊160處的配接表面171之上。該力必須足以位移來自在凸塊166及窄互連墊160處的配接表面171之間的黏著劑163。凸塊166可藉由該力F來加以變形,衝破在凸塊的接觸表面上及/或窄墊160的配接表面171上的氧化膜。凸塊166的變形可使得該凸塊之可熔的材料壓到窄墊160的頂端及邊緣之上。黏著劑163係藉由加熱到一選定的溫度而部分地固化。在此階段,黏著劑163只須要部分地固化,換言之,只須要到一程度是接著足以避免熔化的焊料沿著該黏著劑及導電線路之間的介面流動即可。凸塊166之可熔的材料係被熔化且接著再度凝固,此係形成該凸塊166及窄墊160間的冶金互連。如同大致在圖12c中的172處所示,黏著劑163係完全被固化以完成晶粒安裝且穩固在配接表面171處之電互連。因此,電互連係以一種如圖8的配置形成在凸塊166及導線上之對應的窄互連墊160之間。其它導線173係在其它位置的窄互連墊上互連,此可見於其它截面圖中。黏著劑163的固化可在熔化該焊料之前、同時、或是之後完成。通常,黏著劑163是一種可熱固化的黏著劑,並且在製程中的任何階段固化的程度係藉由調節溫度來加以控制。該些構件可藉由升高該取放型工具168上的夾頭169的溫度、或是藉由升高該基板支台的溫度來加熱及固化。
該製程係更詳細展示在圖13a-13d中。在圖13a中,基板176係在晶粒附接表面上設置有導電線路以及在該線路上的互連位置處的窄互連墊178,並且該些線路係以黏著劑179來覆蓋。半導體晶粒180係相關於基板176來設置以使得該晶粒的主動側面對基板的晶粒附接側,並且藉由箭頭A來對準,使得晶粒上的凸塊182和窄墊178上之對應的配接表面對準。半導體晶粒180及基板176係朝向彼此移動,使得凸塊182接觸到窄墊178上之個別的配接表面。在圖13b中,一力係被施加以移動凸塊182及窄墊178來彼此抵靠、位移黏著劑179、以及將該凸塊變形到該窄墊的配接表面183及邊緣之上。凸塊182在窄墊178上的變形係衝破在該凸塊的接觸表面以及該窄墊的配接表面183之上的氧化膜,因而建立良好的電連接。凸塊在窄墊的邊緣之上的變形係有助於建立一種良好的暫時機械連接。線路184的窄互連墊係在圖13b的平面外。如同在圖13c中所示,熱係被施加以部分地固化黏著劑179。額外的熱係被施加以升高凸塊182的溫度到足以使得該凸塊之可熔的材料熔化且完成黏著劑179的固化,即如同在圖13d中所示者。因此,冶金的互連係在凸塊182及窄互連墊178之間的配接表面183處形成。該固化的黏著劑179係穩固晶粒的安裝。
在一替代實施例中,該黏著劑可預施加到晶粒表面或至少是晶粒表面上的凸塊,而不是基板。該黏著劑可以集中在一貯存器中,並且該晶粒的主動側可浸在該池中並且移開,因而一個量的黏著劑係載於凸塊上。該晶粒係利用一取放型工具而被設置成面對一被支撐的基板,其中該晶粒的主動側係朝向該基板的晶粒附接表面。該晶粒及基板係被對準並且朝向彼此移動,使得該凸塊接觸基板上之對應的線路或導線。此種方法係被描述在美國專利號6,780,682中,其係在此納入作為參考。施力、固化及熔化的步驟係如上述地被實行。
或者是,該覆晶互連的形成係藉由提供一具有在晶粒附接表面中形成的窄互連墊之基板、提供一在該些窄墊上具有開口的焊料遮罩以及一具有在主動表面中附接至互連墊的凸塊之半導體晶粒、支撐該基板及晶粒、以該晶粒的主動側朝向該基板的晶粒附接表面來設置該晶粒、對準該晶粒及基板且朝向彼此地移動使得該些凸塊接觸該基板上之對應的窄墊、以及熔化且接著再度凝固以在該凸塊及窄墊間形成該互連。
在另一實施例中,該覆晶互連的形成係藉由提供一具有在晶粒附接表面中形成的窄互連墊之基板、提供一在該些窄墊上具有開口的焊料遮罩、在該些窄墊上沉積焊料膏、附接一在主動表面中具有凸塊的半導體晶粒至互連墊、支撐該基板及晶粒、以該晶粒的主動側朝向該基板的晶粒附接表面來設置該晶粒、對準該晶粒及基板且朝向彼此地移動使得該些凸塊接觸該基板上之對應的窄墊上之焊料膏、以及熔化且接著再度凝固該焊料膏以在該凸塊及窄墊間形成冶金的互連。
一用於上述製程的力及溫度的時程係被展示在圖14中。時間係在水平軸上從左到右的進行。一力輪廓200係被展示為一粗實線,並且一溫度輪廓210係被展示為一虛線。該溫度輪廓係以80-90℃的範圍中的溫度開始。該力輪廓係以實質為零的力開始。如下所論述,開始於最初的時間ti,該力係在202從Fi快速地增高到一位移/變形力Fd,並且在204保持在該力一段時間。該力Fd係足以將黏著劑從該凸塊及該窄互連墊的配接表面之間位移開。該力Fd係足以變形該凸塊之可熔的部份到該配接表面之上,衝破該氧化膜,以及形成良好的金屬到金屬的冶金接觸。在某些實施例中,該凸塊流到該窄墊的邊緣之上以建立凸塊及窄墊的機械地緊密連接,此被稱為蠕動(creep)變形。總需要的力大小係依據凸塊材料及尺寸以及凸塊數目而定,並且可在不需要過度的實驗即可決定之。
當該力增高時,該溫度亦在212從一最初的溫度Ti快速地升高到一膠體溫度Tg。該膠體溫度Tg是一足以部分固化黏著劑成為膠體狀態的溫度。該力及溫度的斜坡上升係被設定成使得有一短的延遲時間tdef(在Fd到達後且在Tg到達前),其延遲長度是足夠讓該升高的力在黏著劑部分固化開始前先位移黏著劑並且變形凸塊。該組裝在204及214被保持在該位移/變形壓力Fd及膠體溫度Tg一段足以達成黏著劑的部分固化之時間tgel。該黏著劑應該變成足夠穩固的,其可以接著在焊料再熔化階段期間維持良好的凸塊輪廓,換言之,其為足夠穩固的,以避免該凸塊之熔化的可熔材料之不希望有的位移或是該熔化的可熔材料沿著窄墊及導線的流動。
一旦黏著劑已經部分固化到一足夠的程度時,該壓力可在206快速斜坡下降到實質沒有力,亦即只有該些構件的重量而已。該溫度係接著在216進一步快速地升高到一足以再熔化凸塊之可熔的部份的溫度Tm。該組裝在218被保持在該再熔化溫度Tm一段至少足以完全在該窄墊之上形成焊料再熔化並且以實質(儘管不必要是完全地)固化該黏著劑的時間tmelt/cure。該溫度係在220斜坡下降到該最初的溫度Ti並且最終下降到環境溫度。圖14中繪出的製程可在5-10秒的時間期間進行完其過程。
圖14中的黏著劑可以是一種非流動性底膠填充材料。在某些覆晶互連的方式中,冶金互連是先被形成,接著一底膠填充材料係流入在晶粒及基板之間的空間中。該非流動性底膠填充材料是在半導體晶粒及基板被放在一起前先被施加,並且該非流動性底膠填充材料係藉由凸塊接近到窄墊之上並且藉由晶粒及基板的相對表面而被位移。用於該非流動性底膠填充材料的黏著劑是一種快速膠化的黏著劑,亦即,一種在該膠體溫度下於1-2秒的數量級之時間期間中充分膠化的材料。典型的用於該非流動性底膠填充黏著劑的材料係包含非導電膏。
例如是複合的凸塊之替代性的凸塊結構亦可被利用在BONP互連中。複合的凸塊具有兩個由不同凸塊材料製成的凸塊部份,其包含一個可在回焊條件下分解的部份、以及一個在回焊條件下實質不可分解的部份。該不可分解的部份係附接到晶粒上的互連位置。典型用於該不可分解的部份之材料係包含各種具有高鉛含量或Au的焊料。該可分解的部份係接合到該不可分解的部份,並且達成和窄互連墊連接的是該可分解的部份。典型用於該複合的凸塊之可分解的部份之材料係包含共晶焊料。
圖15係展示採用一種複合的凸塊之BONP互連。半導體晶粒222在晶粒的主動側上設置帶有複合的凸塊224之晶粒墊,該複合的凸塊224包含不可分解的部份226以及可分解的部份228。該可分解的部份228可以是共晶焊料或是一種相對低溫熔化的焊料。該可分解的部份228係接觸形成在基板232上的窄墊230的配接表面,並且在凸塊之可熔的部份變形在窄墊之上是所要的情形中,凸塊之可分解的部份在所採用的力之條件下是可變形的。該不可分解的部份226在處理期間當該晶粒在壓力下被移動抵靠基板時並不變形,並且在該製程的回焊階段期間並不熔化。於是,該不可分解的部份226的尺寸可定為在半導體晶粒222的主動表面及基板232的晶粒附接表面之間提供一間隙距離。
圖15中的互連亦可藉由使具有高Pb或Au之非複合的不可分解的凸塊與設置在配接表面上之具有可熔的材料(例如,共晶焊料或相對低溫熔化的焊料或焊料膏)的窄互連墊接觸來加以形成。或者是,該窄互連墊可用可熔的材料而被設置在配接表面上,並且該凸塊可以是複合的凸塊,且亦被設置一可分解或可熔的部份。在該窄互連墊是用可熔的材料被設置在配接表面上的情形中,一焊料遮罩可在該製程中被利用,接著是毛細管底膠填充。
圖6-11所示的實施例中的凸塊可以是如圖15中所述之複合的凸塊、或是利用如上所述的窄墊上焊料的方法中具有高Pb或Au之不可分解的凸塊。
隨著形成線路的技術之進步,可靠地形成具有小於約25μm的標稱或設計規則寬度之線路是可能的。縮小的線路寬度可提供增高的繞線密度。可靠的機械連接及良好的電互連可藉由形成窄互連墊、藉由擴大該導線到一在尺寸上相關於凸塊基底直徑且限制在小於該凸塊基底直徑的程度而做成。
該窄互連墊可用各種形狀來加以形成。某些此類的形狀可以是較易於製造的,而某些則可提供其它的製程優點。該窄墊可以是大致矩形的(不是正方形,就是細長的),即如同圖16a中的線路242末端上的窄墊240以及圖16b中的線路246末端上的窄墊244所示、或是大致圓的(不是圓形,就是橢圓的),即如同圖16c中的線路250末端上的窄墊248以及圖16d中的線路254末端上的窄墊252所示。其它形狀亦可被利用,例如圖16e中的線路258末端上之半圓的末端部份256所示,該末端部份256係在縱長方向上藉由一正方形或矩形部份257所隔開。該窄墊可被形成為該導線或線路中的一對稱或不對稱的擴大,其在圖17a中被展示為線路262末端上的大致矩形墊260以及圖17b中線路266末端上的窄墊264。再者,該窄墊不必位於或靠近該導線或線路的末端,而是可被形成在任何被指定互連的點,即如同在圖17c中沿著線路270形成的大致矩形墊268所示。形成長度大於寬度的墊係因為表平面加上側邊露出的部份而增大該窄墊之可濕的配接表面,並且可以改善互連的機械強度。在該墊是長度大於寬度的情形中,焊料遮罩開口或凸塊的失準容限係增大,尤其在該墊是在線路末端的情形中,細長的墊可降低焊料遮罩開口或凸塊會被設置偏離該墊的末端之可能性。
圖18a-18b係展示一具有大致矩形(不是正方形,就是細長的)焊料遮罩開口的實施例。一特定的寬度之正方形或矩形係具有比沿著短軸有相同寬度或直徑的圓形或橢圓大的面積。在圖18a中,正方形遮罩開口272具有一容納較大量的焊料膏或其它可熔的材料之容量,並且在例如是焊料膏之可熔的材料在與凸塊配接前先被施加到線路274上所形成的窄墊273上的配接表面的情形中可提供一優點。圖18b係展示線路278上所形成的窄墊276之上的矩形遮罩開口275,其具有類似的容量以容納較大量的焊料膏或其它可熔的材料。再者,將可熔的材料印到正方形或矩形遮罩開口中比起印到圓形或橢圓的遮罩開口中可能是較容易的,因為在印製製程中有較大的失準容限。給定遮罩開口的寬度限制下,正方形或矩形遮罩開口係提供較大的開放區域以用於在互連製程期間安裝大凸塊在墊273或276上。
有關焊料遮罩282中之圓形遮罩開口280的各種窄墊配置係被展示在圖19中。在每個例子中的遮罩開口係具有約90μm的寬度或直徑Wm。一BOL配置係被展示在284處,其中導線或線路286具有約30μm的標稱設計寬度WL。一具有矩形形狀的窄墊係被展示在288處,其中導線或線路290具有約30μm的標稱設計寬度WL’。該矩形窄墊288具有約45μm的寬度WP。一具有橢圓形形狀的窄墊係被展示在292處,其形成在較寬的導線或線路294處,具有約50μm的標稱設計寬度WL”。窄墊292的橢圓形部份具有約55μm的寬度WP’。一具有以橢圓形形狀擴大的矩形形狀的窄墊係被展示在296處。形成窄墊296之較窄的導線或線路298具有約30μm的標稱設計寬度WL’’’。窄墊296的矩形部份具有約45μm的寬度WP”,並且該橢圓形擴大的部份具有約50μm的寬度WPE。
有關導線或線路300或窄墊304的各種焊料遮罩開口配置係被展示在圖20中。在這些例子中,在互連位置處的導線或窄墊具有約40μm的寬度WL。在第一例子中,一圓形的焊料遮罩開口302具有約90μm的寬度或直徑Wm,其係露出一互連位置部份304。在第二例子中,一矩形焊料遮罩開口306具有橫跨該導線或窄墊的約80μm之寬度Wm'以及約120μm的長度Lm',其係露出一互連位置部份308。在第三例子中,一橢圓的焊料遮罩開口310具有橫跨該導線或窄墊的約80μm之寬度Wm"以及約120μm的長度Lm",其係露出一互連位置部份312。儘管該圓形的開口具有較大的直徑,該矩形開口306及橢圓形開口310都露出比該圓形的焊料遮罩開口302大的導線或墊312的長度或區域,此係提供較大的區域以用於在互連製程期間焊料回焊,因而可產生較強健的互連。由該矩形開口306所露出的區域係稍大於由具有相同寬度及長度之橢圓的開口310所露出的區域。再者,若該橢圓的開口有稍微的失準,該區域將會縮小,但不會因為該矩形開口稍微的失準而縮小。然而,因為在焊料遮罩介電質中圖案化開口的製程中的解析度限制,設計的矩形開口實際上可能多少有些圓的角落。
晶粒上的凸塊基底直徑可以是大約90μm,並且該窄互連墊係在基板上被形成到一範圍約25μm(線路寬度是小於約25μm的情形)至約50μm的寬度。相較於具有習知的抓取墊(具有通常是大到線路寬度的兩倍到四倍之相當大的直徑)之基板而言,該窄互連墊係在繞線密度上提供顯著的改善。
圖6-20中所示的BOL、BONL及BONP互連結構可藉由數種方法的任一種來產生,而無論有無焊料遮罩。一般而言,互連凸塊係黏貼到晶粒的主動側上的互連墊之上。基板之上方的晶粒附接表面係具有一上方的金屬層,該金屬層被圖案化以提供線路以及在適於和該特定晶粒上的凸塊配置互連的互連位置處的窄墊。一封裝樹脂黏著劑係被採用以在互連製程的熔化階段期間限制焊料流動。該BOL、BONL及BONP互連可提供顯著較高的信號線路逸散的繞線密度。該些導電線路具有一藉由可被設置在基板上之相鄰導電線路間的最小間隔以及該互連位置的寬度所決定的間距,其係提供一等於該些導電線路的間距之繞線密度。
圖21-26係描述其它具有各種互連結構的實施例,該些互連結構可和如圖6-20中所述的BOL、BONL或BONP互連結合而被利用。圖21a係展示一具有一種例如是矽、鍺、砷化鎵、磷化銦或碳化矽的主體基板材料322以供結構支撐的半導體晶圓320。複數個半導體晶粒或構件324係形成在晶圓320上且藉由如上所述的切割道326分開。
圖21b係展示半導體晶圓320的一部份的橫截面圖。每個半導體晶粒324具有一背表面328以及包含類比或數位電路的主動表面330,該類比或數位電路被實施為形成在該晶粒內且根據該晶粒的電設計及功能電互連的主動裝置、被動裝置、導電層以及介電層。該電路可包含一或多個電晶體、二極體以及其它形成在主動表面330內之電路元件以實施類比電路或數位電路,例如數位信號處理器(DSP)、ASIC、記憶體或是其它信號處理電路。半導體晶粒324亦可包含整合被動裝置(IPD),例如電感器、電容器及電阻器,以供RF信號處理使用。在一實施例中,半導體晶粒324是一覆晶類型的半導體晶粒。
一導電層332係利用PVD、CVD、電解的電鍍、無電的電鍍製程、或是其它合適的金屬沉積製程而形成在主動表面330之上。導電層332可以是Al、Cu、Sn、Ni、Au、Ag、或是其它合適的導電材料的一或多層。導電層332係運作為電連接至主動表面330上的電路之接觸墊。
圖21c係展示具有一形成在接觸墊332之上的互連結構的半導體晶圓320的一部份。一導電凸塊材料334係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落(ball drop)、或是網版印刷製程而沉積在接觸墊332之上。凸塊材料334可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其組合,其具有一選配的助熔(flux)溶劑。凸塊材料334可以是共晶Sn/Pb、高鉛的焊料或是無鉛的焊料。凸塊材料334是大致順應的(compliant)並且在相當於約200克的垂直荷重的力下進行大於約25μm的塑性變形。凸塊材料334係利用一合適的附著或連結製程連結到接觸墊332。例如,凸塊材料334可以壓縮連結到接觸墊332。凸塊材料334亦可藉由加熱該材料超過其熔點來進行回焊以形成球或凸塊336,即如同在圖21d中所示者。在某些應用中,凸塊336係進行二次回焊以改善至接觸墊332的電連接。凸塊336係代表一種可形成在接觸墊332之上的互連結構類型。該互連結構亦可以使用柱形凸塊、微凸塊或是其它電互連。
圖21e係展示互連結構的另一實施例,其係以複合的凸塊338形成在接觸墊332之上,該凸塊338包含一不可熔或不可分解的部份340以及可熔或可分解的部份342。該可熔或可分解的特質以及不可熔或不可分解的特質係針對凸塊338關於回焊條件所界定的。該不可熔的部份340可以是Au、Cu、Ni、高鉛的焊料、或是鉛錫合金。該可熔的部份342可以是Sn、無鉛的合金、Sn-Ag合金、Sn-Ag-Cu合金、Sn-Ag-銦(In)合金、共晶焊料、錫和Ag、Cu或Pb的合金、或是其它相對低溫熔化的焊料。在一實施例中,給定一接觸墊332 100μm的寬度或直徑,該不可熔的部份340高度大約是45μm並且可熔的部份342高度大約是35μm。
圖21f係展示互連結構的另一實施例,其係形成在接觸墊332之上而成為導電柱346之上的凸塊344。凸塊344是可熔或可分解的,並且導電柱346是不可熔或不可分解的。該可熔或可分解的特質以及不可熔或不可分解的特質係相關於回焊條件加以界定。凸塊344可以是Sn、無鉛的合金、Sn-Ag合金、Sn-Ag-Cu合金、Sn-Ag-In合金、共晶焊料、錫和Ag、Cu或Pb的合金、或是其它相對低溫熔化的焊料。導電柱346可以是Au、Cu、Ni、高鉛的焊料、或是鉛錫合金。在一實施例中,導電柱346是一Cu柱,並且凸塊344是一焊料蓋。給定一接觸墊332 100μm的寬度或直徑,導電柱346高度大約是45μm,並且凸塊344高度大約是35μm。
圖21g係展示互連結構的另一實施例,其係形成在接觸墊332之上而為具有突點(asperity)350的凸塊材料348。類似於凸塊材料334,凸塊材料348在回焊條件下是軟的且可變形的,具有低的屈伏強度(yield strength)以及高的致衰壞伸長率(elongation to failure)。突點350係以電鍍的表面處理而形成,並且為了說明之目的係在圖式中被誇大展示。突點350的等級一般是在大約1-25μm的數量級。該突點亦可形成在凸塊336、複合的凸塊338以及凸塊344上。
在圖21h中,半導體晶圓320係利用一鋸條或雷射切割工具352透過切割道326被單切為個別的半導體晶粒324。
圖22a係展示一具有導電線路356的基板或PCB 354。基板354可以是單面FR5層壓板或是雙面BT-樹脂層壓板。半導體晶粒324係被設置以使得凸塊材料334係和導電線路356上之互連位置對準,請參見圖30a-30g。或者是,凸塊材料334可和形成在基板354上的導電墊或是其它互連位置對準。凸塊材料334係比導電線路356寬。在一實施例中,對於150μm的凸塊間距,凸塊材料334具有小於100μm的寬度,並且導電線路或墊356具有35μm的寬度。導電線路356可以是圖6-20的BOL、BONL或BONP互連的部份。
一壓力或力F係被施加至半導體晶粒324的背表面328以將凸塊材料334壓到導電線路356之上。該力F可在高溫下施加。由於凸塊材料334之順應的本質,該凸塊材料係變形或突出在導電線路356的頂表面及側表面周圍,被稱為BOL。尤其,在相當於大約200克的垂直荷重之力F下,壓力的施加係使得凸塊材料334進行大於約25μm的塑性變形並且覆蓋導電線路的頂表面及側表面,即如同在圖22b中所示者。凸塊材料334亦可藉由將該凸塊材料和導電線路實體接觸並且接著在一回焊溫度下回焊該凸塊材料以冶金連接至導電線路356。
藉由使得導電線路356比凸塊材料334窄,導電線路的間距可被降低以增加繞線密度以及I/O數目。較窄的導電線路356係降低使凸塊材料334變形在導電線路的周圍所需的力F。例如,該必要的力F可以是使凸塊材料抵靠比凸塊材料寬的導電線路或墊變形所需的力之30-50%。較小的壓力F對於細間距立連及小的晶粒維持具有一指定容限之共面性以及達成均勻的z向變形及高可靠度的互連結合是有用的。此外,將凸塊材料334變形在導電線路356的周圍係將該凸塊機械地鎖到該線路以避免在回焊期間晶粒移動或是晶粒浮接。
圖22c係展示形成在半導體晶粒324的接觸墊332之上的凸塊336。半導體晶粒324係被設置以使得凸塊336和導電線路356上的互連位置對準。或者是,凸塊336可和形成在基板354上的導電墊或其它互連位置對準。凸塊336係比導電線路356寬。導電線路356可以是圖6-20的BOL、BONL或BONP互連的部份。
一壓力或力F係被施加至半導體晶粒324的背表面328以將凸塊336壓到導電線路356之上。該力F可在高溫下施加。由於凸塊336之順應的本質,該凸塊係變形或突出在導電線路356的頂表面及側表面周圍。尤其,壓力的施加係使得凸塊材料336進行塑性變形並且覆蓋導電線路356的頂表面及側表面。凸塊336亦可藉由在回焊溫度下使該凸塊和該導電線路實體接觸以冶金連接至導電線路356。
藉由使得導電線路356比凸塊336窄,導電線路的間距可被降低以增加繞線密度及I/O數目。較窄的導電線路356係降低將凸塊336變形在導電線路的周圍所需的力F。例如,該必要的力F可以是使一凸塊抵靠一比該凸塊寬的導電線路或墊變形所需的力之30-50%。較低的壓力F對於細間距互連及小的晶粒維持在一指定容限內的共面性以及達成均勻的z向變形及高可靠度的互連結合是有用的。此外,將凸塊336變形在導電線路356的周圍係將該凸塊機械地鎖到該線路以避免在回焊期間的晶粒移動或晶粒浮接。
圖22d係展示形成在半導體晶粒324的接觸墊332之上的複合的凸塊338。半導體晶粒324係被設置以使得複合的凸塊338和導電線路356上的互連位置對準。或者是,複合的凸塊338可和形成在基板354上的導電墊或其它互連位置對準。複合的凸塊338係比導電線路356寬。導電線路356可以是圖6-20的BOL、BONL或BONP互連的部份。
一壓力或力F係被施加至半導體晶粒324的背表面328以將可熔的部份342壓到導電線路356之上。該力F可在高溫下施加。由於可熔的部份342之順應的本質,該可熔的部份係變形或突出在導電線路356的頂表面及側表面周圍。尤其,壓力的施加係使得可熔的部份342進行塑性變形並且覆蓋導電線路356的頂表面及側表面。複合的凸塊338亦可藉由在回焊溫度下使可熔的部份342和該導電線路實體接觸以冶金連接至導電線路356。該不可熔的部份340在壓力或溫度的施加期間並不熔化或變形,並且保持其高度及形狀而作為在半導體晶粒324及基板354間之一垂直的間隙。該在半導體晶粒324及基板354間之額外的位移係在配接的表面之間提供較大的共面性容限。
在一回焊製程期間,半導體晶粒324上之大數目的(例如,數千個)複合的凸塊338係附接到基板354的導電線路356上之互連位置。某些凸塊338可能未能夠適當地連接到導電線路356,特別是當晶粒324被扭曲時。回想起複合的凸塊338可以比導電線路356寬。在施加一適當的力之下,該可熔的部份342係變形或突出在導電線路356的頂表面及側表面周圍,並且將複合的凸塊338機械地鎖到該導電線路。該機械地緊密連接係藉由該可熔的部份342的本質而形成,該本質是比導電線路356軟且更順應,因而變形在該導電線路的頂表面之上以及在該導電線路的側表面周圍以得到較大的接觸表面積。在複合的凸塊338以及導電線路356之間的機械地緊密連接係在回焊期間將該凸塊保持在該導電線路,亦即,該凸塊及導電線路並不失去接觸。於是,複合的凸塊338配接到導電線路356係減少凸塊互連的失敗。
圖22e係展示形成在半導體晶粒324的接觸墊332之上的導電柱346及凸塊344。半導體晶粒324係被設置以使得凸塊344和導電線路356上之互連位置對準。或者是,凸塊344可和形成在基板354上的導電墊或其它互連位置對準。凸塊344係比導電線路356寬。導電線路356可以是圖6-20的BOL、BONL或BONP互連的部份。
一壓力或力F係被施加至半導體晶粒324的背表面328以將凸塊344壓到導電線路356之上。該力F可在高溫下施加。由於凸塊344之順應的本質,該凸塊係變形或突出在導電線路356的頂表面及側表面周圍。尤其,壓力的施加係使得凸塊344進行塑性變形並且覆蓋導電線路356的頂表面及側表面。導電柱346及凸塊344亦可藉由在回焊溫度下使該凸塊和該導電線路實體接觸以冶金連接至導電線路356。導電柱346在壓力或溫度的施加期間並不熔化或變形,並且保持其高度及形狀而成為在半導體晶粒324及基板354間之一垂直的間隙。該在半導體晶粒324及基板354間之額外的位移係在配接的表面之間提供較大的共面性容限。該較寬的凸塊344及較窄的導電線路356具有類似以上針對凸塊材料334及凸塊336所述的低必要的壓力及機械地鎖住的特點及優點。
圖22f係展示形成在半導體晶粒324的接觸墊332之上的具有突點350的凸塊材料348。半導體晶粒324係被設置以使得凸塊材料348係和導電線路356上的互連位置對準。或者是,凸塊材料348可和形成在基板354上的導電墊或其它互連位置對準。凸塊材料348係比導電線路356寬。一壓力或力F係被施加至半導體晶粒324的背表面328以將凸塊材料348壓到導電線路356之上。該力F可在高溫下施加。由於凸塊材料348之順應的本質,該凸塊係變形或突出在導電線路356的頂表面及側表面周圍。尤其,壓力的施加係使得凸塊材料348進行塑性變形並且覆蓋導電線路356的頂表面及側表面。此外,突點350係冶金連接至導電線路356。突點350的尺寸係做成大約1-25μm的數量級。
圖22g係展示基板或PCB 358具有成角度或傾斜的側邊之梯形導電線路360。凸塊材料361係被形成在半導體晶粒324的接觸墊332之上。半導體晶粒324係被設置以使得凸塊材料361和導電線路360上的互連位置對準。或者是,凸塊材料361可和形成在基板358上的導電墊或其它互連位置對準。凸塊材料361係比導電線路360寬。導電線路360可以是圖6-20的BOL、BONL或BONP互連的部份。
一壓力或力F係被施加至半導體晶粒324的背表面328以將凸塊材料361壓到導電線路360之上。該力F可在高溫下施加。由於凸塊材料361之順應的本質,該凸塊材料係變形或突出在導電線路360的頂表面及側表面周圍。尤其,壓力的施加係使得凸塊材料361在力F下進行塑性變形,以覆蓋導電線路360的頂表面以及傾斜的側表面。凸塊材料361亦可藉由將該凸塊材料和導電線路實體接觸並且接著在一回焊溫度下回焊該凸塊材料以冶金連接至導電線路360。
圖23a-23d係展示半導體晶粒324以及具有一不可熔或不可分解的部份364及可熔或可分解的部份366之細長複合的凸塊362之一BOL實施例。該不可熔的部份364可以是Au、Cu、Ni、高鉛的焊料、或是鉛錫合金。該可熔的部份366可以是Sn、無鉛的合金、Sn-Ag合金、Sn-Ag-Cu合金、Sn-Ag-In合金、共晶焊料、錫和Ag、Cu或Pb的合金、或是其它相對低溫熔化的焊料。該不可熔的部份364比該可熔的部份366構成複合的凸塊362之較大的一部分。該不可熔的部份364係固定到半導體晶粒324的接觸墊332。
半導體晶粒324係被設置以使得複合的凸塊362係和形成在基板370上之導電線路368上的互連位置對準,即如同在圖23a中所示者。複合的凸塊362係沿著導電線路368漸縮,亦即,該複合的凸塊具有楔形,沿著導電線路368的長度方向上較長,而橫跨該導電線路的方向上較窄。複合的凸塊362之漸縮特點係出現在沿著導電線路368的長度方向上。圖23a中的繪圖係展示該較短的特點或變窄的漸縮是與導電線路368共線的。垂直於圖23a的圖23b中的繪圖係展示該楔形複合的凸塊362之較長的特點。複合的凸塊362之較短的特點係比導電線路368寬。該可熔的部份366在壓力施加及/或以熱回焊時分解在導電線路368的周圍,即如圖23c及23d中所示者。該不可熔的部份364在回焊期間並不熔化或變形,並且保持其外形及形狀。該不可熔的部份364的尺寸可被設為在半導體晶粒324及基板370之間提供一間隙距離。一例如是Cu OSP的處理可施加到基板370。導電線路368可以是圖6-20的BOL、BONL或BONP互連的部份。
在一回焊製程期間,半導體晶粒324上之大數目的(例如,數千個)複合的凸塊362係附接到基板370的導電線路368上之互連位置。某些凸塊362可能未能夠適當地連接到導電線路368,特別是半導體晶粒324被扭曲時。回想起複合的凸塊362係比導電線路368寬。在施加一適當的力之下,該可熔的部份366係變形或突出在導電線路368的頂表面及側表面周圍,並且將複合的凸塊362機械地鎖到該導電線路。該機械地緊密連接係藉由該可熔的部份366之本質而形成,該本質係比導電線路368軟且較順應的,因而變形在該導電線路的頂表面及側表面周圍以得到較大的接觸面積。複合的凸塊362的楔形係增加在該凸塊及導電線路間的接觸面積,例如,沿著圖23b及23d之較長的特徵方向增加,而沒有犧牲到沿著圖23a及23c之較短的特徵方向上的間距。在複合的凸塊362及導電線路368間之機械地緊密連接係在回焊期間將該凸塊保持在該導電線路,亦即,該凸塊及導電線路並不失去接觸。於是,配接到導電線路368之複合的凸塊362係減少凸塊互連的失敗。
圖24a-24d係展示半導體晶粒324的一BOL實施例,其中類似於圖21c,凸塊材料374係形成在接觸墊332之上。在圖24a中,凸塊材料374是大致順應的,並且在一相當於大約200克的垂直荷重之力下進行大於約25μm的塑性變形。凸塊材料374係比基板378上的導電線路376寬。複數個突點380係以一大約1-25μm的數量級之高度形成在導電線路376上。
半導體晶粒324係被設置以使得凸塊材料374和導電線路376上的互連位置對準。或者是,凸塊材料374可和形成在基板378上的導電墊或其它互連位置對準。一壓力或力F係被施加至半導體晶粒324的背表面328以將凸塊材料374壓到導電線路376及突點380之上,即如同在圖24b中所示者。該力F可在高溫下施加。由於凸塊材料374之順應的本質,該凸塊材料係變形或突出在導電線路376的頂表面及側表面以及突點380周圍。尤其,壓力的施加係使得凸塊材料374進行塑性變形並且覆蓋導電線路376的頂表面及側表面以及突點380。凸塊材料374的塑性流動係在該凸塊材料與導電線路376的頂表面及側表面以及突點380之間產生巨觀的機械地緊密連接點。凸塊材料374的塑性流動係發生在導電線路376的頂表面及側表面以及突點380周圍,但並不過度地延伸到基板378之上,否則可能造成電氣短路及其它缺陷。在該凸塊材料與導電線路376的頂表面及側表面以及突點380之間的機械地緊密連接係在不顯著增加連結力之下,提供一具有個別的表面間較大的接觸面積之強健的連接。在該凸塊材料與導電線路376的頂表面及側表面以及突點380之間的機械地緊密連接亦降低在例如是封裝的後續製程期間橫向的晶粒移動。
圖24c係展示其中凸塊材料374比導電線路376窄的另一BOL實施例。一壓力或力F係被施加至半導體晶粒324的背表面328以將凸塊材料374壓到導電線路376及突點380之上。該力F可在高溫下施加。由於凸塊材料374之順應的本質,該凸塊材料係變形或突出在導電線路376的頂表面及突點380之上。尤其,壓力的施加係使得凸塊材料374進行塑性變形並且覆蓋導電線路376的頂表面及突點380。凸塊材料374的塑性流動係在該凸塊材料以及導電線路376的頂表面及突點380之間產生巨觀的機械地緊密連接點。在該凸塊材料以及導電線路376的頂表面及突點380之間的機械地緊密連接係在不顯著增加連結力之下,提供一具有個別的表面間較大的接觸面積之強健的連接。在該凸塊材料以及導電線路376的頂表面及突點380之間的機械地緊密連接亦降低在例如是封裝的後續製程期間橫向的晶粒移動。
圖24d係展示另一BOL實施例,其中凸塊材料374形成在導電線路376的一邊緣之上,亦即,部份的凸塊材料在該導電線路之上,而部份的凸塊材料則不在該導電線路之上。一壓力或力F係被施加至半導體晶粒324的背表面328以將凸塊材料374壓到導電線路376及突點380之上。該力F可在高溫下施加。由於凸塊材料374之順應的本質,該凸塊材料係變形或突出在導電線路376的頂表面及側表面及突點380之上。尤其,壓力的施加係使得凸塊材料374進行塑性變形並且覆蓋導電線路376的頂表面及側表面及突點380。凸塊材料374的塑性流動係在該凸塊材料與導電線路376的頂表面及側表面以及突點380之間產生巨觀的機械地緊密連接。在該凸塊材料與導電線路376的頂表面及側表面以及突點380之間的機械地緊密連接係在不顯著增加連結力之下提供一具有個別的表面間較大的接觸面積之強健的連接。在該凸塊材料與導電線路376的頂表面及側表面以及突點380之間的機械地緊密連接亦降低在例如是封裝的後續製程期間橫向的晶粒移動。
圖25a-25c係展示半導體晶粒324的一BOL實施例,其中類似於圖21c,凸塊材料384形成在接觸墊332之上。一尖端386係從凸塊材料384的主體延伸成為一階梯形凸塊,其中尖端386比凸塊材料384的主體窄,即如同在圖25a中所示者。半導體晶粒324係被設置以使得凸塊材料384和基板390上的導電線路388上之互連位置對準。更明確地說,尖端386係被設置在導電線路388上的互連位置之中央上。或者是,凸塊材料384及尖端386可和形成在基板390上的導電墊或其它互連位置對準。凸塊材料384係比基板390上的導電線路388寬。
導電線路388是大致順應的,並且在一相當於大約200克的垂直荷重的力之下進行大於約25μm的塑性變形。一壓力或力F係被施加至半導體晶粒324的背表面328以將尖端384壓到導電線路388之上。該力F可在高溫下施加。由於導電線路388之順應的本質,該導電線路係變形在尖端386的周圍,即如同在圖25b中所示者。尤其,壓力的施加係使得導電線路388進行塑性變形並且覆蓋尖端386的頂表面及側表面。
圖25c係展示另一BOL實施例,其中圓形的凸塊材料394係形成在接觸墊332之上。一尖端396係從凸塊材料394的主體延伸以形成一柱形凸塊,其中該尖端比凸塊材料394的主體窄。半導體晶粒324係被設置以使得凸塊材料394和基板400上的導電線路398上之互連位置對準。更明確地說,尖端396係被設置在導電線路398上的互連位置之中央上。或者是,凸塊材料394及尖端396可和形成在基板400上的導電墊或其它互連位置對準。凸塊材料394係比基板400上的導電線路398寬。
導電線路398是大致順應的,並且在一相當於大約200克的垂直荷重的力之下進行大於約25μm的塑性變形。一壓力或力F係被施加至半導體晶粒324的背表面328以將尖端396壓到導電線路398之上。該力F可在高溫下施加。由於導電線路398之順應的本質,該導電線路係變形在尖端396周圍。尤其,壓力的施加係使得導電線路398進行塑性變形,並且覆蓋尖端396的頂表面及側表面。
圖22a-22g、23a-23d及24a-24d中所述的導電線路亦可以是如圖25a-25c中所述之順應的材料。
圖26a-26b係展示半導體晶粒324的一BOL實施例,其中類似於圖21c,凸塊材料404係形成在接觸墊332之上。凸塊材料404是大致順應的,並且在一相當於大約200克的垂直荷重的力之下進行大於約25μm的塑性變形。凸塊材料404係比基板408上的導電線路406寬。一具有開口412及導電的側壁414之導電貫孔410係穿過導電線路406而形成,即如同在圖26a中所示者。導電線路406可以是圖6-20的BOL、BONL或BONP互連的部份。
半導體晶粒324係被設置以使得凸塊材料404和導電線路406上的互連位置對準,請參見圖30a-30g。或者是,凸塊材料404可和形成在基板408上的導電墊或其它互連位置對準。一壓力或力F係被施加至半導體晶粒324的背表面328以將凸塊材料404壓到導電線路406之上並且壓入導電貫孔410的開口413中。該力F可在高溫下施加。由於凸塊材料404之順應的本質,該凸塊材料係變形或突出在導電線路406的頂表面及側表面周圍且進入到導電貫孔410的開口412中,即如同在圖26b中所示者。尤其,壓力的施加係使得凸塊材料404進行塑性變形並且覆蓋導電線路406的頂表面及側表面且進入到導電貫孔410的開口412中。因此,凸塊材料404係電連接至導電線路406及導電的側壁414以供穿過基板408的z向垂直的互連使用。凸塊材料404的塑性流動係在該凸塊材料與導電線路406的頂表面及側表面以及導電貫孔410的開口412之間產生機械地緊密連接。在該凸塊材料與導電線路406的頂表面及側表面以及導電貫孔410的開口412之間的機械地緊密連接係在不顯著增加連結力之下提供一具有個別的表面間較大的接觸面積之強健的連接。在該凸塊材料與導電線路406的頂表面及側表面以及導電貫孔410的開口412之間的機械地緊密連接亦降低在例如是封裝的後續製程期間橫向的晶粒移動。由於導電貫孔410係和凸塊材料404一起被形成在該互連位置之內,因此總基板互連面積係減少。
在圖22a-22g、23a-23d、24a-24d、25a-25c及26a-26b的BOL實施例中,藉由使導電線路比互連結構窄,導電線路的間距可被降低以增加繞線密度及I/O數目。較窄的導電線路係降低將互連結構變形在導電線路的周圍所需的力F。例如,該必要的力F可以是使一凸塊抵靠一比該凸塊寬的導電線路或墊變形所需的力之30-50%。該較低的壓力F對於細間距互連及小的晶粒維持在一指定容限內的共面性以及達成均勻的z向變形及高可靠度的互連結合是有用的。此外,將互連結構變形在導電線路的周圍係將該凸塊機械地鎖到該線路以避免在回焊期間的晶粒移動或晶粒浮接。
圖27a-27c係展示一種模具底膠填充(MUF)製程以將封裝材料沉積在半導體晶粒及基板間的凸塊周圍。圖27a係展示半導體晶粒324利用圖22b的凸塊材料334而安裝到基板354,並且被設置在凹槽(chase)模具420的上方模具支撐件416及下方模具支撐件418之間。圖22a-22g、23a-23d、24a-24d、25a-25c及26a-26b之其它的半導體晶粒及基板之組合亦可設置在凹槽模具420的上方模具支撐件416及下方模具支撐件418之間。該上方模具支撐件416係包含可壓縮的離型膜(releasing film)422。
在圖27b中,上方模具支撐件416及下方模具支撐件418被放在一起以封入半導體晶粒324及基板354,其具有一開放空間在該基板之上且在該半導體晶粒及基板之間。可壓縮的離型膜422係貼合半導體晶粒324的背表面328及側表面以阻擋封裝材料在這些表面上的形成。一種處於液態的封裝材料424係利用噴嘴426而被注入到凹槽模具420的一側中,而一選配的真空輔助428從相反的側邊吸壓以將該封裝材料均勻地填入基板354之上的開放空間以及在半導體晶粒324及基板354之間的開放空間。封裝材料424可以是聚合物複合材料(例如,具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯)、或是具有適合的填充劑之聚合物。封裝材料424是非導電的並且在環境上保護半導體裝置免於接觸到外部的元素及污染物。可壓縮的材料422係避免封裝材料424流到半導體晶粒324的背表面328之上及側表面的周圍。封裝材料424係被固化。半導體晶粒324的背表面328及側表面係保持露出自封裝材料424。
圖27c係展示MUF及模具過度填充(MOF),亦即,在沒有可壓縮的材料422下的一實施例。半導體晶粒324及基板354係被設置在凹槽模具420的上方模具支撐件416及下方模具支撐件418之間。該上方模具支撐件416及下方模具支撐件418係被放在一起以封入半導體晶粒324及基板354,其具有一開放空間在該基板之上、在該半導體晶粒的周圍且在該半導體晶粒及基板之間。處於液態的封裝材料424係利用噴嘴426而被注入到凹槽模具420的一側中,而一選配的真空輔助428係從相反的側邊吸壓以將該封裝材料均勻地填入在半導體晶粒324的周圍且在基板354之上的開放空間以及在半導體晶粒324及基板354之間的開放空間。封裝材料424係被固化。
圖28係展示將封裝材料沉積在半導體晶粒324的周圍且在半導體晶粒324及基板354之間的間隙中的另一實施例。半導體晶粒324及基板354係藉由屏障(dam)430圍住。封裝材料432係以液態從噴嘴434分配到屏障430中,以填入基板354之上的開放空間以及在半導體晶粒324及基板354之間的開放空間。從噴嘴434分配的封裝材料432的量係被控制在不覆蓋半導體晶粒324的背表面328或側表面下填入屏障430。封裝材料432係被固化。
圖29係展示在圖27a、27c及28的MUF製程之後的半導體晶粒324及基板354。封裝材料424係均勻地散佈在基板354之上且在半導體晶粒324及基板354之間的凸塊材料334的周圍。
圖30a-30g係展示在基板或PCB 440上之各種的導電線路佈局的俯視圖。在圖30a中,導電線路442是一形成在基板440上具有一體型(integrated)凸塊墊或互連位置444之直的導體。基板凸塊墊444的側邊可以是和導電線路442共線的。在習知技術中,一焊料對準開口(SRO)通常是形成在該互連位置之上,以在回焊期間限制凸塊材料。該SRO會增加互連間距且減少I/O數目。相對地,遮罩層446可形成在基板440的一部份之上;然而,該遮罩層並未形成在導電線路442的基板凸塊墊444的周圍。換言之,導電線路442中被設計來和凸塊材料配接的部份並沒有原本用於在回焊期間凸塊限制的遮罩層446的任何SRO。
半導體晶粒324係被設置在基板440之上,並且凸塊材料係和基板凸塊墊444對準。凸塊材料係藉由使該凸塊材料和該凸塊墊實體接觸並且接著在一回焊溫度下回焊該凸塊材料以電氣且冶金連接至基板凸塊墊444。
在另一實施例中,一導電凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落或網版印刷製程以沉積在基板凸塊墊444之上。該凸塊材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及其組合,其具有一選配的助熔溶劑。例如,該凸塊材料可以是共晶Sn/Pb、高鉛的焊料、或是無鉛的焊料。該凸塊材料係利用一合適的附著或連結製程來連結到基板凸塊墊444。在一實施例中,該凸塊材料係藉由加熱該材料超過其熔點來回焊,以形成凸塊或互連448,即如同在圖30b中所示者。在某些應用中,凸塊448係進行二次回焊以改善到基板凸塊墊444的電氣接觸。在該窄的基板凸塊墊444周圍的凸塊材料係在回焊期間維持晶粒的位置。
在高繞線密度的應用中,最小化導電線路442的逸散間距是所期望的。在導電線路442之間的逸散間距可藉由消除用於回焊限制目的之遮罩層,亦即,藉由在沒有遮罩層下回焊凸塊材料而被減少。由於沒有SRO被形成在晶粒凸塊墊332或基板凸塊墊444的周圍,所以導電線路442可用較細的間距形成,亦即,導電線路442可被設置成較靠在一起或是較靠近附近的結構。在基板凸塊墊444周圍沒有SRO之下,導電線路442間的間距係給定為P=D+PLT+W/2,其中D是凸塊448的基底直徑,PLT是晶粒設置容限,並且W是導電線路442的寬度。在一實施例中,給定100μm的凸塊基底直徑、10μm的PLT、以及30μm的線路線寬,導電線路442之最小的逸散間距是125μm。該無遮罩的凸塊形成係免去需要考量到如習知技術中可見的相鄰開口間之遮罩材料的孔帶(ligament)間隔、焊料遮罩對準容限(SRT)、以及最小可解析的SRO。
當該凸塊材料在沒有遮罩層下被回焊以將晶粒凸塊墊332冶金且電連接至基板凸塊墊444時,潤濕及表面張力係使得該凸塊材料維持自我局限(self-confinement)且被保持在晶粒凸塊墊332與基板凸塊墊444及基板440中緊鄰導電線路442且實質在該凸塊墊的覆蓋區中的部份之間的空間內。
為了達成該所要的自我局限性質,凸塊材料可在置放於晶粒凸塊墊332或基板凸塊墊444上之前被浸沒在一助熔溶劑中,以選擇性地使得該凸塊材料所接觸的區域比導電線路442周圍的區域更濕潤。該熔化的凸塊材料係由於該助熔溶劑的可濕性而維持局限在實質由凸塊墊所界定的區域內。該凸塊材料並不溢出到較不濕潤的區域。一薄的氧化層或是其它絕緣層可形成在其中不打算有凸塊材料的區域之上,以使該區域較不濕潤。因此,晶粒凸塊墊332或基板凸塊墊444周圍並不需要有遮罩層440。
圖30c係展示平行的導電線路452為直的導體之另一實施例,其中一體型矩形凸塊墊或互連位置454形成在基板450上。在此例中,基板凸塊墊454係比導電線路452寬,但是小於配接的凸塊寬度。基板凸塊墊454的側邊可以是平行於導電線路452。遮罩層456可形成在基板450的一部份之上;然而,該遮罩層並未形成在導電線路452的基板凸塊墊454的周圍。換言之,導電線路452中被設計以和凸塊材料配接的部份並沒有原本用於在回焊期間凸塊限制的遮罩層456的任何SRO。
圖30d係展示以多個列的一陣列配置的導電線路460及462的另一實施例,其中偏置的一體型凸塊墊或互連位置464形成在基板466上以得到最大的互連密度及容量。交替的導電線路460及462係包含一用於繞線到凸塊墊464的肘部。每個基板凸塊墊464的側邊係和導電線路460及462共線的。遮罩層468可形成在基板466的一部份之上;然而,遮罩層468並未形成在導電線路460及462的基板凸塊墊464的周圍。換言之,導電線路460及462中被設計以和凸塊材料配接的部份並沒有原本用於在回焊期間凸塊限制的遮罩層468的任何SRO。
圖30e係展示以多個列的一陣列配置的導電線路470及472的另一實施例,其中偏置的一體型凸塊墊或互連位置474形成在基板476上以得到最大的互連密度及容量。交替的導電線路470及472係包含一用於繞線到凸塊墊474的肘部。在此例中,基板凸塊墊474是圓形的並且比導電線路470及472寬,但是小於配接的互連凸塊材料的寬度。遮罩層478可形成在基板476的一部份之上;然而,遮罩層478並未形成在導電線路470及472的基板凸塊墊474的周圍。換言之,導電線路470及472中被設計以和凸塊材料配接的部份並沒有原本用於在回焊期間凸塊限制的遮罩層478的任何SRO。
圖30f係展示以多個列的一陣列配置的導電線路480及482的另一實施例,其中偏置的一體型凸塊墊或互連位置484形成在基板486上以得到最大的互連密度及容量。交替的導電線路480及482係包含一用於繞線到凸塊墊484的肘部。在此例中,基板凸塊墊484是矩形的並且比導電線路480及482寬,但是小於配接的互連凸塊材料的寬度。遮罩層488可形成在基板4486的一部份之上;然而,遮罩層488並未形成在導電線路480及482的基板凸塊墊484的周圍。換言之,導電線路480及482中被設計以和凸塊材料配接的部份並沒有原本用於在回焊期間凸塊限制的遮罩層488的任何SRO。
作為互連製程的一例子,半導體晶粒324係被設置在基板466之上,並且凸塊材料334係和圖30d的基板凸塊墊464對準。凸塊材料334係藉由如同圖22a-22g、23a-23d、24a-24d、25a-25c及26a-26b所述,加壓該凸塊材料或是藉由使該凸塊材料和該凸塊墊實體接觸並且接著在一回焊溫度下回焊該凸塊材料,以電氣及冶金連接至基板凸塊墊464。
在另一實施例中,一導電凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落或網版印刷的製程沉積在基板凸塊墊464之上。該凸塊材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其組合,其具有一選配的助熔溶劑。例如,該凸塊材料可以是共晶Sn/Pb、高鉛的焊料、或是無鉛的焊料。該凸塊材料係利用一合適的附著或連結製程連結到基板凸塊墊464。在一實施例中,該凸塊材料係藉由加熱該材料超過其熔點而被回焊以形成凸塊或互連490,即如同在圖30g中所示者。在某些應用中,凸塊490係進行二次回焊以改善到基板凸塊墊464的電氣接觸。該窄的基板凸塊墊464周圍的凸塊材料係維持在回焊期間晶粒的置放。凸塊材料334或凸塊490亦可形成在圖30a-30g的基板凸塊墊配置上。
在高繞線密度的應用中,最小化圖30a-30g的導電線路460及462或是其它導電線路配置的逸散間距是所期望的。在導電線路460及462之間的逸散間距可藉由消除用於回焊限制目的之遮罩層,亦即,藉由在沒有遮罩層下回焊凸塊材料而被減少。由於沒有SRO被形成在晶粒凸塊墊332或基板凸塊墊464的周圍,所以導電線路460及462可用較細的間距形成,亦即,導電線路460及462可被設置成較靠在一起或是較靠近附近的結構。在基板凸塊墊464周圍沒有SRO之下,導電線路460及462間的間距係給定為P=D/2+PLT+W/2,其中D是凸塊490的基底直徑,PLT是晶粒設置容限,並且W是導電線路460及462的寬度。在一實施例中,給定100μm的凸塊基底直徑、10μm的PLT、以及30μm的線路線寬,導電線路460及462之最小的逸散間距是125μm。該無遮罩的凸塊形成係免去需要考量到如習知技術中可見的相鄰開口間之遮罩材料的孔帶間隔、SRT、以及最小可解析的SRO。
當該凸塊材料在沒有遮罩層下被回焊以將晶粒凸塊墊332冶金且電連接至基板凸塊墊464時,潤濕及表面張力係使得該凸塊材料維持自我局限且被保持在晶粒凸塊墊332與基板凸塊墊464及基板466中緊鄰導電線路460及462且實質在該凸塊墊的覆蓋區中的部份之間的空間內。
為了達成該所要的自我局限性質,凸塊材料可在置放於晶粒凸塊墊332或基板凸塊墊464上之前被浸沒在一助熔溶劑中,以選擇性地使得該凸塊材料所接觸的區域比導電線路460及462周圍的區域更濕潤。該熔化的凸塊材料係由於該助熔溶劑的可濕性而維持局限在實質由凸塊墊所界定的區域內。該凸塊材料並不溢出到較不濕潤的區域。一薄的氧化層或是其它絕緣層可形成在其中不打算有凸塊材料的區域之上,以使該區域較不濕潤。因此,晶粒凸塊墊332或基板凸塊墊464周圍並不需要有遮罩層468。
在圖31a中,遮罩層492係沉積在導電線路494及496的一部份之上。然而,遮罩層492並未形成在一體型凸塊墊498之上。因此,在基板500上的每個凸塊墊498都沒有SRO。一非濕性遮罩補片(patch)502係被形成在基板500上且在一體型凸塊墊498的陣列內的空隙中,亦即,在相鄰的凸塊墊之間。該遮罩補片502亦可形成在半導體晶粒324上且在晶粒凸塊墊498的陣列內的空隙中。更一般而言,該遮罩補片係被形成在任何配置中的一體型凸塊墊附近,以避免溢出到較不濕潤的區域。
半導體晶粒324係被設置在基板500之上,並且凸塊材料係和基板凸塊墊498對準。該凸塊材料係藉由如同圖22a-22g、23a-23d、24a-24d、25a-25c及26a-26b所述地壓下該凸塊材料或是藉由使該凸塊材料和該凸塊墊實體接觸並且接著在一回焊溫度下回焊該凸塊材料,以電氣且冶金連接至基板凸塊墊498。
在另一實施例中,一導電凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落、或是網版印刷的製程沉積在晶粒的一體型凸塊墊498之上。該凸塊材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其組合,其具有一選配的助熔溶劑。例如,該凸塊材料可以是共晶Sn/Pb、高鉛的焊料、或是無鉛的焊料。該凸塊材料係利用一合適的附著或連結製程連結到一體型凸塊墊498。在一實施例中,該凸塊材料係藉由加熱該材料超過其熔點來進行回焊,以形成球或凸塊504。在某些應用中,凸塊504係進行二次回焊以改善至一體型凸塊墊498的電氣接觸。該凸塊亦可壓縮連結到一體型凸塊墊498。凸塊504係代表一種可形成在一體型凸塊墊498之上的互連結構的類型。該互連結構亦可以使用柱形凸塊、微凸塊、或其它電互連。
在高繞線密度的應用中,最小化逸散間距是所期望的。為了減少在導電線路494及496間的間距,該凸塊材料係在一體型凸塊墊498周圍沒有遮罩層之下進行回焊。在導電線路494及496之間的逸散間距可藉由消除用於回焊限制目的之遮罩層以及該一體型凸塊墊周圍相關的SRO,亦即,藉由在沒有遮罩層下回焊凸塊材料而被減少。遮罩層492可形成在導電線路494及496以及基板400中遠離一體型凸塊墊498的一部份之上;然而,遮罩層492並未形成在一體型凸塊墊498的周圍。換言之,導電線路494及496中被設計以和凸塊材料配接的部份並沒有原本用於在回焊期間凸塊限制的遮罩層392的任何SRO。
此外,遮罩補片502係被形成在基板500上且在一體型凸塊墊498的陣列內的空隙中。遮罩補片502是非濕性材料。遮罩補片502可以是和遮罩層492相同的材料並且在相同的處理步驟期間施加、或為不同的材料而在不同的處理步驟期間施加。遮罩補片502可藉由對於一體型凸塊墊498的陣列內之線路或墊的部份選擇性的氧化、電鍍、或其它處理來加以形成。遮罩補片502係限制凸塊材料流到一體型凸塊墊498且避免導電凸塊材料滲到相鄰的結構。
當該凸塊材料係利用設置在一體型凸塊墊498的陣列內之空隙的遮罩補片502進行回焊時,潤濕及表面張力係使得該凸塊材料局限且保持在晶粒凸塊墊332與一體型凸塊墊498及基板500中緊鄰導電線路494及496且實質在該一體型凸塊墊498的覆蓋區中的部份之間的空間內。
為了達成所要的局限性質,該凸塊材料可在置放於晶粒凸塊墊332或一體型凸塊墊498上之前被浸沒在一助熔溶劑中,以選擇性地使得該凸塊材料所接觸的區域比導電線路494及496的周圍區域更濕潤。該熔化的凸塊材料係由於該助熔溶劑的可濕性而維持局限在實質由凸塊墊所界定的區域內。該凸塊材料並不溢出到較不濕潤的區域。一薄的氧化層或是其它絕緣層可形成在其中不打算有凸塊材料的區域之上,以使該區域較不濕潤。因此,晶粒凸塊墊332或一體型凸塊墊498的周圍並不需要遮罩層492。
由於晶粒凸塊墊332或一體型凸塊墊498的周圍沒有形成SRO,所以導電線路494及496可用較細的間距形成,亦即,導電線路可較靠近相鄰的結構來設置,而不會接觸且形成電氣短路。假設相同的焊料對準設計規則,導電線路494及496之間的間距係給定為P=(1.1D+W)/2,其中D是凸塊404的基底直徑,並且W是導電線路494及496的寬度。在一實施例中,給定100μm的凸塊直徑以及20μm的線路線寬,導電線路494及496之最小的逸散間距是65μm。該凸塊形成係免去需要考量到如習知技術中可見的相鄰開口間之遮罩材料的孔帶間隔、以及最小可解析的SRO。
圖32係展示堆疊封裝(PoP)505,其中半導體晶粒506係利用晶粒附接黏著劑510而堆疊在半導體晶粒508上。半導體晶粒506及508分別具有一包含類比或數位電路的主動表面,該類比或數位電路被實施為形成在該晶粒內且根據該晶粒的電設計及功能來電互連的主動裝置、被動裝置、導電層以及介電層。例如,該電路可包含一或多個電晶體、二極體以及其它形成在該主動表面內之電路元件以實施類比電路或數位電路,例如:DSP、ASIC、記憶體或其它信號處理電路。半導體晶粒506及508亦可包含例如是電感器、電容器及電阻器的IPD,以供RF信號處理使用。
半導體晶粒506係利用圖22a-22g、23a-23d、24a-24d、25a-25c及26a-26b的實施例中之任一實施例,利用形成在接觸墊518上之凸塊材料516而被安裝到形成在基板514上的導電線路512。導電線路512可以是圖6-20的BOL或BONP互連的部份。半導體晶粒508係利用焊線522電連接至形成在基板514上之接觸墊520。焊線522之相反端係連結到半導體晶粒506上之接觸墊524。
遮罩層526係被形成在基板514之上且開口超過半導體晶粒506的覆蓋區。儘管遮罩層526在回焊期間並不限制凸塊材料516到導電線路512,該開放的遮罩可運作為一屏障以避免在MUF期間封裝材料528遷移到接觸墊520或焊線522。封裝材料528係類似於圖27a-27c地沉積在半導體晶粒508及基板514之間。遮罩層526係阻擋MUF封裝材料528到達接觸墊520及焊線522,否則可能會造成缺陷。遮罩層526係容許較大的半導體晶粒被設置在一特定的基板上,而無封裝材料528流出到接觸墊520之上的風險。
儘管本發明的一或多個實施例已詳細地解說,熟習此項技術者將會體認到可在不脫離如以下的申請專利範圍中所闡述之本發明的範疇下,對於該些實施例進行修改及調適。
1,1’...線
2,2’...線
6,6’...線
7,7’...線
8,8’...線
9,9’...線
10...一覆晶封裝的部份
11...虛線
12...基板
13...線路或導線
14...抓取墊
15...互連凸塊
16...絕緣層或焊料遮罩
17...底膠填充材料
18...半導體晶粒
19...位置
20...一覆晶封裝的部份
29...凸塊的部份
32...基板
33...線路或導線
34...抓取墊
35...凸塊
36...遮罩材料
37...底膠填充材料
38...晶粒
39...位置
50...電子裝置
52...印刷電路板
54...線路
56...打線接合封裝
58...覆晶
60...球狀柵格陣列
62...凸塊晶片載體
64...雙排型封裝
66...平台柵格陣列
68...多晶片模組
70...四邊扁平無引腳封裝
72...四邊扁平封裝
74...半導體晶粒
76...接觸墊
78...中間載體
80...導線
82...焊線
84...封裝材料
88...半導體晶粒
90...載體
92...底膠填充或環氧樹脂黏著材料
94...焊線
96...接觸墊
98...接觸墊
100...模製化合物或封裝材料
102...接觸墊
104...凸塊
106...中間載體
108...主動區域
110...凸塊
112...凸塊
114...信號線
116...模製化合物或封裝材料
120...凸塊
122...逸散線路
124...虛線
126...凸塊
128...逸散線路
130...虛線
131...互連墊
132...基板介電層
133...晶粒墊
134...半導體晶粒
136...互連墊
137...基板介電層
138...晶粒墊
140...半導體晶粒
142...逸散線路
146...虛線
147...互連墊
148...窄導線或線路
149...基板
150...焊料遮罩
151...遮罩開口
152...線路
153...基板
154...墊
155...開口
156...焊料遮罩
158...基板
159...晶粒附接表面
160...互連墊
162...載體或台
163...封裝材料樹脂
164...半導體
166...凸塊
167...凸塊
168...取放型工具
169...夾頭
170...背面
171...配接表面
172...電互連
173...導線
176...基板
178...互連墊
179...黏著劑
180...半導體晶粒
182...凸塊
183...配接凸塊
184...線路
200...力輪廓
202...部份
204...部份
206...部份
210...溫度輪廓
212...部份
214...部份
216...部份
218...部份
220...部份
222...半導體晶粒
224...複合的凸塊
226...不可分解的部份
228...可分解的部份
230...墊
232...基板
240...墊
242...線路
244...墊
246...線路
248...墊
250...線路
252...墊
254...線路
256...半導體末端部份
257...正方形或矩形部份
258...線路
260...矩形墊
262...線路
264...墊
266...線路
268...矩形墊
270...線路
272...正方形遮罩開口
273...墊
274...線路
275...遮罩開口
276...墊
278...線路
280...遮罩開口
282...焊料遮罩
284...BOL配置
286...導線或線路
288...窄墊
290...線路
292...窄墊
297...線或線路
296...墊
298...導線或線路
300...導線或線路
302...焊料遮罩開口
304...互連位置部份
306...焊料遮罩開口
308...互連位置部份
310...焊料遮罩開口
312...導線或墊
320...半導體晶圓
322...主體基板材料
324...半導體晶粒或構件
326...切割道
328...背表面
330...主動表面
332...導電層
334...凸塊材料
336...球或凸塊
338...複合的凸塊
340...不可熔的部份
342...可熔的部份
344...凸塊
346...導電柱
348...凸塊材料
350...突點
352...鋸條或雷射切割工具
354...基板
356...導電線路
358...基板或PCB
360...導電線路
361...凸塊材料
362...複合的凸塊
364...不可熔或不可分解的部份
366...可熔或可分解的部份
368...導電線路
370...基板
374...凸塊材料
376...導電線路
378...基板
380...突點
384...凸塊材料
386...尖端
388...導電線路
390...基板
394...凸塊材料
396...尖端
398...導電線路
400...基板
404...凸塊材料
406...導電線路
408...基板
410...導電貫孔
412...開口
414‧‧‧導電的側壁
416‧‧‧上方模具支撐件
418‧‧‧下方模具支撐件
420‧‧‧凹槽模具
422‧‧‧可壓縮的離型膜
424‧‧‧封裝材料
426‧‧‧噴嘴
428‧‧‧真空輔助
430‧‧‧屏障
432‧‧‧封裝材料
434‧‧‧噴嘴
440‧‧‧基板
442‧‧‧導電線路
444‧‧‧基板凸塊墊
446‧‧‧遮罩層
448‧‧‧凸塊或互連
450‧‧‧基板
452‧‧‧導電線路
454‧‧‧基板凸塊墊
456‧‧‧遮罩層
460‧‧‧導電線路
462‧‧‧導電線路
464‧‧‧基板凸塊墊
466‧‧‧基板
468‧‧‧遮罩層
470‧‧‧導電線路
472‧‧‧導電線路
474‧‧‧基板凸塊墊
476‧‧‧基板
478‧‧‧遮罩層
480‧‧‧導電線路
482‧‧‧導電線路
484‧‧‧基板凸塊墊
486‧‧‧基板
488‧‧‧遮罩層
490‧‧‧凸塊或互連
492‧‧‧遮罩層
494‧‧‧導電線路
496‧‧‧導電線路
498‧‧‧凸塊墊
500‧‧‧基板
502‧‧‧遮罩補片
504‧‧‧球或凸塊
505‧‧‧堆疊封裝
506‧‧‧半導體晶粒
508‧‧‧半導體晶粒
510‧‧‧晶粒附接黏著劑
512‧‧‧導電線路
514‧‧‧基板
516‧‧‧凸塊材料
518‧‧‧接觸墊
520‧‧‧接觸墊
522‧‧‧焊線
524‧‧‧接觸墊
526‧‧‧遮罩層
528‧‧‧封裝材料
圖1係以平行於封裝基板表面的平面描繪一習知的抓取墊上凸塊的覆晶互連;
圖2係以垂直於封裝基板表面的平面描繪一習知的抓取墊上凸塊的覆晶互連;
圖3係以垂直於封裝基板表面的平面描繪另一習知的抓取墊上凸塊的覆晶互連;
圖4係描繪一安裝到其表面之不同類型的封裝的PCB;
圖5a-5c係描繪安裝到該PCB之代表性的半導體封裝之進一步細節;
圖6係以平行於封裝基板表面的平面描繪一BONP覆晶互連;
圖7係以垂直於封裝基板表面的平面描繪圖6的BONP覆晶互連;
圖8係以平行於封裝基板表面的平面描繪一第二BONP覆晶互連;
圖9係以垂直於封裝基板表面的平面描繪圖8的BONP覆晶互連;
圖10係以平行於封裝基板表面的平面描繪一第三BONP覆晶互連;
圖11係以平行於封裝基板表面的平面描繪一第三BONP覆晶互連;
圖12a-12c係描繪一用於製造一覆晶互連的製程;
圖13a-13d係描繪該用於製造一覆晶互連的製程的進一步細節;
圖14係描繪用於製造一覆晶互連的製程之力與溫度的時程;
圖15係描繪一窄墊上凸塊的覆晶互連;
圖16a-16e係描繪各種的互連墊形狀;
圖17a-17c係描繪各種的互連墊配置;
圖18a-18b係描繪各種的焊料遮罩開口;
圖19係描繪各種有關於焊料遮罩開口的互連墊配置;
圖20係描繪各種有關於互連墊的焊料遮罩配置;
圖21a-21h係描繪形成在一半導體晶粒之上用於連結至一基板上的導電線路之各種的互連結構;
圖22a-22g係描繪該半導體晶粒以及連結到該些導電線路的互連結構;
圖23a-23d係描繪具有一連結到該些導電線路之楔形的互連結構的半導體晶粒;
圖24a-24d係描繪該半導體晶粒以及連結到該些導電線路的互連結構的另一實施例;
圖25a-25c係描繪連結到該些導電線路的階梯形凸塊以及柱形凸塊互連結構;
圖26a-26b係描繪具有導電貫孔的導電線路;
圖27a-27c係描繪在該半導體晶粒及基板之間的模具底膠填充;
圖28係描繪在該半導體晶粒及基板之間的另一模具底膠填充;
圖29係描繪在模具底膠填充後之半導體晶粒及基板;
圖30a-30g係描繪具有開放的焊料對準的導電線路之各種配置;
圖31a-31b係描繪具有在導電線路間的補片之開放的焊料對準;並且
圖32係描繪具有遮罩層屏障以在模具底膠填充期間抑制封裝材料之POP。
9,9’...線
126...凸塊
128...逸散線路
130...虛線
136...互連墊
137...基板介電層
Claims (18)
- 一種製造半導體裝置之方法,其包括:提供半導體晶粒,其具有形成在該半導體晶粒的表面上的接觸墊之上的凸塊,其中該凸塊的長度是比垂直於該凸塊的長度之該凸塊的寬度還大;提供基板;在該基板的表面之上形成具有互連位置的導電線路,該互連位置具有寬度大於該凸塊及該接觸墊之間的接觸介面的寬度的20%且小於該接觸介面的寬度的80%;以及將該凸塊連結至該互連位置,以使得該凸塊覆蓋該導電線路的頂表面及側表面,並且該凸塊的寬度延伸橫跨該導電線路且該凸塊的長度沿著該導電線路延伸。
- 如申請專利範圍第1項之方法,其中該互連位置的寬度是遠離該互連位置的該導電線路的寬度的120%。
- 如申請專利範圍第1項之方法,其中該互連位置具有大致矩形、細長或圓形的形狀。
- 如申請專利範圍第1項之方法,其進一步包含在該基板之上形成遮罩層。
- 如申請專利範圍第1項之方法,其中該凸塊包含可熔的部份以及不可熔的部份。
- 如申請專利範圍第1項之方法,其中該凸塊的寬度沿著該凸塊的長度漸縮,以成為在該半導體晶粒附近為較寬且在與該半導體晶粒相對的該凸塊的一末端為較窄。
- 一種製造半導體裝置之方法,其包括: 提供具有接觸墊的半導體晶粒;提供基板;在該基板的表面之上形成具有互連位置的導電線路;在該半導體晶粒上的該接觸墊以及該基板上的該互連位置之間設置互連結構,其中該互連位置的寬度大於該互連結構及該接觸墊之間的接觸介面的寬度的20%且小於該接觸介面的寬度的80%,並且沿著該導電線路的該互連結構的長度是比橫跨該導電線路的該互連結構的寬度大;以及將該互連結構接合到該互連位置,該互連結構覆蓋該導電線路的頂表面和側表面。
- 如申請專利範圍第7項之方法,其中該互連位置的寬度實質等於該導電線路的寬度。
- 如申請專利範圍第7項之方法,其中該互連位置具有大致矩形、細長或圓形的形狀。
- 如申請專利範圍第7項之方法,其中該互連結構包含可熔的部份以及不可熔的部份。
- 如申請專利範圍第7項之方法,其中該互連結構包含導電柱以及形成在該導電柱之上的凸塊。
- 如申請專利範圍第7項之方法,其中該互連結構的寬度沿著該互連結構的長度漸縮,以成為在該半導體晶粒附近為較寬且在該導電線路附近為較窄。
- 一種半導體裝置,其包括:具有接觸墊的半導體晶粒; 基板;形成在該基板的表面之上且具有互連位置的導電線路;以及形成在該接觸墊以及該互連位置之間的互連結構,其中該互連結構覆蓋該導電線路的頂表面及側表面,並且該互連位置的寬度大於在該互連結構及該接觸墊之間的一接觸介面的寬度的20%且小於該接觸介面的寬度的80%,並且沿著該導電線路的該互連結構的長度是比橫跨該導電線路的該互連結構的寬度大。
- 如申請專利範圍第13項之半導體裝置,其中該互連位置的寬度小於遠離該互連位置的該導電線路的寬度的120%。
- 如申請專利範圍第13項之半導體裝置,其中該互連位置具有大致矩形、細長或圓形的形狀。
- 如申請專利範圍第13項之半導體裝置,其中該互連結構包含可熔的部份以及不可熔的部份。
- 如申請專利範圍第13項之半導體裝置,其中該互連結構係包含導電柱以及形成在該導電柱之上的凸塊。
- 如申請專利範圍第13項之半導體裝置,其中該互連結構的寬度沿著該互連結構的長度漸縮,以成為在該半導體晶粒附近為較寬且在該導電線路附近為較窄。
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US20120241946A9 (en) | 2012-09-27 |
US8841779B2 (en) | 2014-09-23 |
US20140319692A1 (en) | 2014-10-30 |
KR20120062598A (ko) | 2012-06-14 |
KR101681332B1 (ko) | 2016-11-30 |
US20110248399A1 (en) | 2011-10-13 |
TW201225210A (en) | 2012-06-16 |
US10580749B2 (en) | 2020-03-03 |
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