TWI681524B - 半導體晶片 - Google Patents

半導體晶片 Download PDF

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Publication number
TWI681524B
TWI681524B TW106137523A TW106137523A TWI681524B TW I681524 B TWI681524 B TW I681524B TW 106137523 A TW106137523 A TW 106137523A TW 106137523 A TW106137523 A TW 106137523A TW I681524 B TWI681524 B TW I681524B
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TW
Taiwan
Prior art keywords
bump
bumps
transistor
main surface
semiconductor wafer
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TW106137523A
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English (en)
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TW201843791A (zh
Inventor
嶋本健一
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日商村田製作所股份有限公司
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Publication of TW201843791A publication Critical patent/TW201843791A/zh
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
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    • H01L27/0211—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique adapted for requirements of temperature
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    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/411—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising two power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Abstract

本發明提供一種能夠縮小構裝面積並且抑制由電晶體所產生之發熱之影響的半導體晶片。
半導體晶片具備：第1電晶體，其將第1訊號放大並輸出第2訊號；第2電晶體，其將第2訊號放大並輸出第3訊號；及半導體基板，其具有與由第1及第2方向規定之平面平行之主面，且形成有第1及第2電晶體；且於主面上設置有：第1凸塊，其與第1電晶體之集極或汲極連接；第2凸塊，其與第1電晶體之射極或源極連接；第3凸塊，其與第2電晶體之集極或汲極連接；及第4凸塊，其與第2電晶體之射極或源極連接；於俯視主面時，第1凸塊呈圓形，第2、第3及第4凸塊呈矩形或橢圓形，第2、第3及第4凸塊之面積大於第1凸塊之面積。

Description

半導體晶片
本發明係關於一種半導體晶片。
於將半導體晶片構裝至基板之一種方法中，存在使用凸塊之倒裝晶片技術。一般而言，倒裝晶片技術與打線接合相比具有能夠縮小構裝面積之優點。
此處，例如於行動電話等行動通訊機中使用有功率放大電路。於功率放大電路中用於放大功率之電晶體具有溫度特性。因此，若因放大動作而導致電晶體發熱，則電晶體之特性可能因溫度上升而產生變動。若對此種功率放大電路使用上述倒裝晶片技術，則雖然構裝面積縮小，但有未充分地進行散熱而對電晶體之特性造成影響之問題。
本發明係鑒於該情況而完成者，其目的在於提供一種能夠縮小構裝面積並且抑制由電晶體所產生之發熱之影響的半導體晶片。
為了達成該目的，本發明之一態樣之半導體晶片具備：第1電晶體，其將第1訊號放大並輸出第2訊號；第2電晶體，其將第2訊號放大並輸出第3 訊號；及半導體基板，其具有與由第1方向及與第1方向交叉之第2方向規定之平面平行之主面，且形成有第1電晶體及第2電晶體；且於半導體基板之主面上設置有：第1凸塊，其與第1電晶體之集極或汲極電性連接；第2凸塊，其與第1電晶體之射極或源極電性連接；第3凸塊，其與第2電晶體之集極或汲極電性連接；及第4凸塊，其與第2電晶體之射極或源極電性連接；於俯視半導體基板之主面時，第1凸塊呈圓形，第2、第3及第4凸塊呈矩形或橢圓形，且第2、第3及第4凸塊之面積分別大於第1凸塊之面積。
根據本發明，可提供一種能夠縮小構裝面積並且抑制由電晶體所產生之發熱之影響的半導體晶片。
10‧‧‧功率放大電路
20、21‧‧‧放大器
Q1、Q2‧‧‧電晶體
100A~100F、500A~500C‧‧‧半導體晶片
110、510‧‧‧半導體基板
111‧‧‧主面
120~124、222、322、400、410、420、600、610、620‧‧‧凸塊
520‧‧‧區域
S1~S4‧‧‧邊
CL‧‧‧中心線
圖1係形成於本發明之第1實施形態之半導體晶片之功率放大電路的電路圖。
圖2係本發明之第1實施形態之半導體晶片的俯視圖。
圖3係本發明之第2實施形態之半導體晶片的俯視圖。
圖4係本發明之第3實施形態之半導體晶片的俯視圖。
圖5係本發明之第4實施形態之半導體晶片的俯視圖。
圖6係本發明之第5實施形態之半導體晶片的俯視圖。
圖7係本發明之第6實施形態之半導體晶片的俯視圖。
圖8係本發明之第7實施形態之半導體晶片的俯視圖。
圖9係本發明之第8實施形態之半導體晶片的俯視圖。
圖10係本發明之第9實施形態之半導體晶片的俯視圖。
以下，一邊參照圖式，一邊對本發明之實施形態詳細地進行說明。於以下之圖式之記載中，相同或類似之構成要素以相同或類似之符號表示。圖式為例示，各部分之尺寸或形狀為示意性者，不應將本案發明之技術範圍限定於該實施形態而進行解釋。
首先，一邊參照圖1及圖2，一邊對本發明之第1實施形態之半導體晶片進行說明。此處，圖1係形成於本發明之第1實施形態之半導體晶片之功率放大電路的電路圖，圖2係本發明之第1實施形態之半導體晶片的俯視圖。
圖1所示之功率放大電路10具備例如放大器20、21。放大器20、21分別進行射頻(RF：Radio Frequency)訊號之放大。於本實施形態中，放大器20、21係作為例如由異質接面雙極電晶體(HBT：Heterojunction Bipolar Transistor)等雙極電晶體構成者而進行說明。再者，放大器20、21亦可由場效電晶體(MOSFET：Metal-oxide-semiconductor Field-Effect Transistor，金屬氧化物半導體場效電晶體)等其他電晶體構成。於此情形時，只要將基極、集極、及射極分別改稱為閘極、汲極、及源極即可。
初級(驅動級)之放大器20包含電晶體Q1(第1電晶體)。電晶體Q1將輸入訊號RF1(第1訊號)放大，並輸出放大訊號RF2(第2訊號)。後級(功率級)之放大器21包含電晶體Q2(第2電晶體)。電晶體Q2將放大訊號RF2進一步放大，並輸出放大訊號RF3(第3訊號)。具體而言，電晶體Q1中，基極被供給輸入訊號RF1，集極被供給電源電壓，且射極接地。電晶體Q1將輸入訊號RF1放大，並自集極輸出放大訊號RF2。電晶體Q2中，基極被供給放大訊號RF2，集極被供給電源電壓，且射極接地。電晶體Q2將放大訊號RF2進一步放大，並自集極輸出放大訊號RF3。再者，雖然省略圖示，但功率放大電路10亦可進而具備偏壓電路及匹配電路等其他電路。又，於本實施形態中，示出放大器之級 數為2級之例，但放大器之級數並不限定於2級，亦可為3級以上。又，於圖1中，示出雙極電晶體，但亦可使用FET(Field-Effect Transistor)代替該雙極電晶體。
其次，一邊參照圖2，一邊對形成有功率放大電路10之半導體晶片進行說明。圖2所示之半導體晶片100A例如包含半導體基板110、及設置於半導體基板110之主面上之複數個凸塊120~124g。
半導體基板110例如具有與由X軸方向(第1方向)及與X軸方向交叉(於圖2中正交)之Y軸方向(第2方向)規定之平面平行的主面111。半導體基板110之材料並無特別限定，例如以化合物半導體為主成分。圖2係半導體基板110之主面111側之俯視，主面111具有與X軸平行之邊S1(第1邊)、S2(第2邊)、及與Y軸平行之邊S3、S4。雖然於圖2中省略，但於半導體基板110形成有例如圖1所示之構成初級之放大器20之電晶體Q1及構成後級之放大器21之電晶體Q2。各電晶體Q1、Q2係分別將例如複數個指狀部於XY平面方向整齊排列配置而構成。
半導體晶片100A藉由使用凸塊之倒裝晶片技術而構裝於模組基板(未圖示)。藉此，將形成於該半導體晶片100A之各放大器20、21與形成於模組基板之路徑電性連接。
再者，供構裝半導體晶片100A之模組基板亦可為例如PCB(Print Circuit Board，印刷電路板)或低溫共燒陶瓷(LTCC：Low Temperature Co-fired Ceramics)等基板。於該模組基板，除半導體晶片100A以外，亦構裝有功率放大電路之輸出匹配電路、或將發送訊號與接收訊號分離之收發雙工器、或開關電路等其他電路。作為收發雙工器，例如亦可使用表面聲波(SAW：Surface Acoustic Wave)濾波電路、或IHP-SAW(Incredible High Performance-SAW，超高性能表面聲波)濾波電路。
圖2所示之凸塊120、121、122a、122b、123a~123d係分別將電 晶體Q1、Q2之集極及射極與半導體晶片100A之外部電性連接之凸塊。又，凸塊124a~124g並無特別限定，例如係作為用於自半導體晶片100A之外部進行電源電壓之供給、輸入訊號之供給、接地電位之供給、或控制訊號之供給等之端子而發揮功能的凸塊。再者，各凸塊120~124g並無特別限定，例如可為Cu柱凸塊，或者亦可為焊料凸塊等。以下，對凸塊120~123d具體地進行說明。
凸塊120(第1凸塊)係電性連接構成初級之電晶體Q1之各指狀部之集極之凸塊。凸塊120例如於俯視主面111時呈圓形。
凸塊121(第2凸塊)係電性連接構成初級之電晶體Q1之各指狀部之射極之凸塊。凸塊121例如於俯視主面111時，呈具有與X軸平行之短邊方向及與Y軸平行之長邊方向之矩形。又，於俯視主面111時，凸塊121之面積大於凸塊120之面積。再者，與電晶體Q1之集極及射極連接之凸塊之數量於圖2中分別為1個，但並不限定於1個，亦可為複數個。
凸塊122a(第3凸塊之第1部分)、122b(第3凸塊之第2部分)係電性連接構成後級之電晶體Q2之各指狀部之集極之凸塊。凸塊122a、122b分別個別地形成，且相對於半導體基板110之X軸方向之中心線CL大致對稱地配置。凸塊122a、122b例如於俯視主面111時，呈具有與X軸平行之長邊方向及與Y軸平行之短邊方向之矩形。又，凸塊122a、122b分別於邊S1之附近以長邊方向成為與X軸大致平行之方式配置。藉由如此將凸塊122a、122b配置於半導體基板110之外框之附近，而將自電晶體Q2輸出之放大訊號RF3輸出至半導體晶片之外部時的路徑變短。又，於俯視主面111時，凸塊122a、122b之面積均大於凸塊120之面積。再者，與電晶體Q2之集極連接之凸塊之數量於圖2中為2個，但並不特別限定於2個，亦可為1個或3個以上。
凸塊123a~123d(第4凸塊)係電性連接構成後級之電晶體Q2之各指狀部之射極之凸塊。換言之，構成電晶體Q2之複數個指狀部係於配置有凸 塊123a~123d之區域，於XY平面方向整齊排列配置。凸塊123a~123d於凸塊120與凸塊122a、122b之間之區域分別個別地形成，且以相對於半導體基板110之X軸方向之中心線CL大致對稱之方式，於X軸方向並排配置有4個。凸塊123a~123d例如於俯視主面111時，呈具有與X軸平行之短邊方向及與Y軸平行之長邊方向之矩形。即，凸塊122a、122b之長邊方向與凸塊123a~123d之長邊方向正交。又，於俯視主面111時，凸塊123a~123d之面積均大於凸塊120之面積。再者，與電晶體Q2之射極連接之凸塊之數量於圖2中為4個，但並不特別限定於4個，可為1個至3個，或者亦可為5個以上。
凸塊124a~124g之形狀並無特別限定，於本實施形態中，於俯視主面111時呈圓形。凸塊124a~124e(第5凸塊)分別於半導體基板110之外框中邊S1之對邊即邊S2之附近，沿邊S2配置。凸塊124f配置於邊S4之近旁。凸塊124g配置於相對於中心線CL與凸塊120大致對稱之位置。
其次，對凸塊121~123d呈矩形之理由進行說明。形成於半導體晶片100A之電晶體Q1、Q2於動作狀態下發熱，故而元件之溫度上升。電晶體一般地具有溫度特性，因此，放大動作之特性可能會因溫度上升而產生變動。此處，俯視主面111時之凸塊之面積越大，則與模組基板之接著面積變得越大，因此，經由凸塊散熱之熱量增大。然而，伴隨凸塊之面積之增大，晶片面積亦增大。
就該方面而言，於半導體晶片100A中，與發熱量相對較多之初級之電晶體之射極、以及發熱量更多之後級之電晶體Q2之集極及射極連接的凸塊121、122a、122b、123a~123d為矩形，與初級之電晶體Q1之集極連接之凸塊120為圓形。藉此，凸塊121、122a、122b、123a~123d之面積大於凸塊120之面積，而經由凸塊散熱之熱量較多。因此，根據半導體晶片100A，與未使用倒裝晶片技術之構成相比，能夠縮小構裝面積並且抑制由電晶體所產生之發熱之影 響。
再者，於本實施形態中，與電晶體Q1之集極連接之凸塊120為圓形，但凸塊120亦可為矩形而代替圓形。又，凸塊121、122a、122b、123a~123d亦可為橢圓形而代替矩形。
圖3係本發明之第2實施形態之半導體晶片的俯視圖。圖3所示之半導體晶片100B與圖2所示之半導體晶片100A相比，與電晶體Q2之集極連接之凸塊之形狀不同。具體而言，半導體晶片100B具備凸塊222a、222b而代替凸塊122a、122b。
凸塊222a(第3凸塊之第1部分)、222b(第3凸塊之第2部分)與凸塊122a、122b同樣地，與電晶體Q2之集極連接，而將自電晶體Q2輸出之放大訊號RF3輸出至半導體晶片100B之外部。又，凸塊222a、222b分別於邊S1之附近以長邊方向成為與X軸大致平行之方式配置。此處，凸塊222a、222b各自之長邊方向(於圖3中為X軸方向)之長度L2較與電晶體Q2之射極連接之凸塊123a~123d各自之長邊方向(於圖3中為Y軸方向)之長度L1長。藉此，半導體晶片100B與半導體晶片100A相比，散熱之效果進一步提高。
圖4係本發明之第3實施形態之半導體晶片的俯視圖。圖4所示之半導體晶片100C與圖2所示之半導體晶片100A相比，與電晶體Q2之集極連接之凸塊之形狀不同。具體而言，半導體晶片100C具備凸塊322a、322b而代替凸塊122a、122b。
凸塊322a(第3凸塊之第1部分)、322b(第3凸塊之第2部分)與凸塊122a、122b同樣地，與電晶體Q2之集極連接，而將自電晶體Q2輸出之放大訊號RF3輸出至半導體晶片100C之外部。又，凸塊322a、322b分別於邊S1之附近以長邊方向成為與X軸大致平行之方式配置。此處，凸塊322a、322b各自之長邊方向(於圖3中為X軸方向)之長度L3較與電晶體Q2之射極連接之凸塊123a~ 123d各自之長邊方向(於圖3中為Y軸方向)之長度L1短。
即，為了散熱，較佳為如上述半導體晶片100B般與集極連接之凸塊之面積較大。然而，凸塊一般有面積越大則該凸塊之厚度(即，主面111之法線方向之高度)越容易變厚之傾向。因此，若形成於邊S1之附近之凸塊之面積過度變大，則該凸塊之厚度可能會變得較形成於邊S1之對邊即邊S2之附近的凸塊124a~124e之厚度厚。於此情形時，因凸塊之厚度之不均勻而導致例如面積較小之凸塊124a~124e自模組基板浮起，從而容易引起連接不良等。
就該方面而言，根據半導體晶片100C，可避免凸塊322a、322b之面積較凸塊124a~124e之面積過度變大。因此，接觸不良得以抑制，而半導體晶片100C之構裝時之搭載性提高。
再者，於圖4中，示出凸塊322a、322b之數量為2個之例，但該凸塊之數量亦可為3個以上。凸塊之數量越多，越能夠縮小每1個凸塊之面積，因此，容易抑制與形成於對邊之附近之凸塊124a~124e之高度的不均勻。
圖5係本發明之第4實施形態之半導體晶片的俯視圖。圖5所示之半導體晶片100D與圖4所示之半導體晶片100C相比，進而具備凸塊400。
凸塊400(第6凸塊)係與作為使自電晶體Q2之集極輸出之放大訊號RF3之諧波(例如，2倍波、3倍波、或4倍波等)衰減的濾波電路之一具體例之諧波終端電路之一部分電性連接。具體而言，於例如諧波終端電路由串聯連接之電容器及電感器構成之情形時，凸塊400亦可為將形成於半導體基板110側之電容器與形成於模組基板側之電感器連接之端子。如圖5所示，凸塊400設置於半導體基板110之主面111上，且於俯視主面111時呈圓形。又，凸塊400例如於邊S1之近旁，配置於凸塊322a(第3凸塊之第1部分)與凸塊322b(第3凸塊之第2部分)之間且中心線CL之附近。藉由如此將凸塊400配置於X軸方向之中心附近，而使自構成電晶體Q2之複數個指狀部至諧波終端電路為止之路徑之距離 均勻化。藉此，因該路徑之距離之偏差引起之諧波終端電路之特性之變動得以抑制。
再者，於本實施形態中，凸塊400為圓形，但凸塊400亦可為矩形或橢圓形而代替圓形。
圖6係本發明之第5實施形態之半導體晶片的俯視圖。圖6所示之半導體晶片100E與圖5所示之半導體晶片100D相比，具備凸塊410a、410b而代替凸塊400。
凸塊410a(第6凸塊之第1部分)、410b(第6凸塊之第2部分)分別個別地形成，且與凸塊400同樣地，與使自電晶體Q2之集極輸出之放大訊號RF3之諧波衰減的諧波終端電路之一部分電性連接。即，關於半導體晶片100E，設想形成有2個諧波終端電路之構成。如圖6所示，凸塊410a、410b分別設置於半導體基板110之主面111上，且於俯視主面111時呈圓形。又，凸塊410a、410b分別於例如邊S1之近旁相對於中心線CL大致對稱地配置。藉由如此將凸塊410a、410b相對於中心線CL大致對稱地配置2個，與半導體晶片100D相比，自各指狀部至各諧波終端電路為止之路徑之距離變短，而該距離更均勻化。
再者，於本實施形態中，凸塊410a、410b為圓形，但凸塊410a、410b亦可為矩形或橢圓形而代替圓形。
又，於本實施形態中，凸塊322a與凸塊322b配置於凸塊410a與凸塊410b之間，但亦可將凸塊410a與凸塊410b配置於凸塊322a與凸塊322b之間。
又，本實施形態中之2個諧波終端電路可以均使相同頻率之諧波(例如均為2倍波等)終止之方式設計，或者亦可以使不同頻率之諧波(例如2倍波與3倍波等)終止之方式設計。
圖7係本發明之第6實施形態之半導體晶片的俯視圖。圖7所示之半導體晶片100F與圖6所示之半導體晶片100E相比，與諧波終端電路之一部分連 接之凸塊之形狀不同。具體而言，半導體晶片100F具備凸塊420a、420b而代替凸塊410a、410b。
凸塊420a(第6凸塊之第1部分)、420b(第6凸塊之第2部分)係個別地形成，且與凸塊410a、410b同樣地，與使自電晶體Q2之集極輸出之放大訊號RF3之諧波衰減的諧波終端電路之一部分電性連接。於俯視主面111時，凸塊420a、420b與凸塊322a、322b同樣地，呈具有與X軸平行之長邊方向及與Y軸平行之短邊方向之矩形。藉由如此將凸塊420a、420b之形狀與凸塊322a、322b之形狀設為相同，而容易使凸塊420a、420b之厚度與凸塊322a、322b之厚度一致。因此，根據半導體晶片100F，與半導體晶片100E相比，半導體晶片之構裝時之搭載性提高。
圖8係本發明之第7實施形態之半導體晶片的俯視圖。圖8所示之半導體晶片500A形成有2組圖1所示之功率放大電路10。再者，關於半導體晶片500A，僅對與相當於功率放大電路10所包含之電晶體Q1、Q2的電晶體之各端子連接之凸塊進行說明，而對其他凸塊(相當於圖2中之凸塊124a~124g)省略說明。
半導體晶片500A於半導體基板510上具有相對於X軸方向之中心線CL對稱之2個區域520x、520y。於一區域520x設置有凸塊120x、121x、122x、123ax~123dx。同樣地，於區域520y設置有凸塊120y、121y、122y、123ay~123dy。分別設置於該等兩區域520x、520y之各凸塊相當於圖2所示之凸塊120、121、122a、122b、123a~123d，故而省略詳細之說明。
半導體晶片500A於2個區域520x、520y之各者中形成有功率放大電路。藉由半導體晶片500A具備2個功率放大電路，而能夠根據例如輸入訊號RF1之頻帶(例如，高頻帶、中間頻帶、或低頻帶等)而對放大電路進行劃分。或者，亦可根據輸入訊號RF1之通訊標準(例如，2G(第2代移動通訊系統)、 3G(第3代移動通訊系統)、或4G(第4代移動通訊系統)等)而對放大電路進行劃分。再者，亦可為如下構成：於形成於區域520x、520y中任一區域之功率放大電路處於動作中之情形時，形成於另一區域之功率放大電路停止動作。
於上述構成中，於半導體晶片500A中，與發熱量相對較多的初級之電晶體之射極、後級之電晶體之集極、及後級之電晶體之射極連接之凸塊121x、121y、122x、122y、123ax~123dx、123ay~123dy之面積亦大於與初級之電晶體之集極連接之凸塊120x、120y之面積。藉此，與半導體晶片100A同樣地，能夠縮小構裝面積並且抑制由電晶體所產生之發熱之影響。
再者，與後級之電晶體之集極連接之凸塊可如圖8所示般，於每1個功率放大電路為1個，亦可如圖2所示般為複數個。
圖9係本發明之第8實施形態之半導體晶片的俯視圖。圖9所示之半導體晶片500B與圖8所示之半導體晶片500A相比，進而具備凸塊600x、600y。
凸塊600x、600y分別設置於半導體基板510之區域520x、520y。凸塊600x、600y分別與圖5所示之凸塊400同樣地，與使自後級之電晶體之集極輸出之放大訊號RF3之諧波衰減的諧波終端電路之一部分電性連接。
藉由上述構成，半導體晶片500B亦能夠獲得與半導體晶片500A同樣之效果。
再者，功率放大電路所具備之諧波終端電路可如圖9所示般，於每1個功率放大電路為1個，亦可如圖6所示般為複數個。
又，於本實施形態中，凸塊600x、600y為圓形，但凸塊600x、600y亦可為矩形或橢圓形而代替圓形。
圖10係本發明之第9實施形態之半導體晶片的俯視圖。圖10所示之半導體晶片500C與圖8所示之半導體晶片500A相比，進而具備凸塊610x、620x、610y、620y。
凸塊610x、620x設置於半導體基板510之區域520x。凸塊610y、620y設置於半導體基板510之區域520y。凸塊610x、620x、610y、620y均與圖5所示之凸塊400同樣地，與使自後級之電晶體之集極輸出之放大訊號RF3之諧波衰減的諧波終端電路之一部分電性連接。即，關於半導體晶片500C，與半導體晶片100E同樣地，設想於每1個功率放大電路配備2個諧波終端電路之構成。
藉由上述構成，半導體晶片500C亦能夠獲得與半導體晶片500A同樣之效果。又，如圖10所示，與諧波終端電路連接之凸塊之形狀亦可由圓形、矩形、或橢圓形等各形狀組合而成。
以上，對本發明之例示性之實施形態進行了說明。於半導體晶片100A~100F、500A~500C中，於半導體基板110、510之主面上設置有：凸塊120，其與初級之電晶體Q1之集極或汲極連接；凸塊121，其與初級之電晶體Q1之射極或源極連接；凸塊122a、122b(222a、222b、322a、322b、122x、122y)，其等與後級之電晶體Q2之集極或汲極連接；及凸塊123a~123d(123ax~123dx、123ay~123dy)，其等與後級之電晶體Q2之射極或源極連接；且於俯視半導體基板110、510之主面時，凸塊120呈圓形，凸塊121、122a、122b、123a~123d呈矩形或橢圓形，凸塊121、122a、122b、123a~123d之面積分別大於凸塊120之面積。藉此，凸塊121、122a、122b、123a~123d與凸塊120相比，經由凸塊散熱之熱量較多。因此，根據半導體晶片100A~100F、500A~500C，與未使用倒裝晶片技術之構成相比，能夠縮小構裝面積並且抑制由電晶體所產生之發熱之影響。
又，於半導體晶片100A~100F、500A~500C中，凸塊122a、122b(222a、222b、322a、322b、122x、122y)係以長邊方向與半導體基板110、510之1個邊S1大致平行之方式配置於邊S1之附近。藉此，將自電晶體Q2輸出之放大訊號RF3輸出至半導體晶片之外部時的路徑變短，從而可抑制損耗。
又，於半導體晶片100C~100F中，於邊S1之對邊即邊S2之附近 設置有凸塊124a~124e，且凸塊322a、322b之面積大於凸塊124a~124e之面積，凸塊322a、322b之長邊方向之長度短於凸塊123a~123d之長邊方向之長度。藉此，可避免凸塊322a、322b之面積較凸塊124a~124e之面積過度變大。因此，接觸不良得以抑制，而半導體晶片之構裝時之搭載性提高。
又，於半導體晶片100D中，進而設置有與諧波終端電路之一部分連接之凸塊400。凸塊322a、322b分別於邊S1之附近相對於X軸方向之中心線CL大致對稱地配置，且凸塊400於邊S1之附近，配置於凸塊322a、322b之間且中心線CL附近。藉此，使自構成電晶體Q2之複數個指狀部至諧波終端電路為止之路徑之距離均勻化。因此，因該路徑之距離之偏差引起之諧波終端電路之特性之變動得以抑制。
又，於半導體晶片100E、100F中，進而設置有與諧波終端電路之一部分連接之凸塊410a、410b(420a、420b)。凸塊410a、410b(420a、420b)分別於邊S1之附近相對於X軸方向之中心線CL大致對稱地配置，且凸塊322a、322b配置於凸塊410a、410b(420a、420b)之間。藉此，根據半導體晶片100E、100F，與半導體晶片100D相比，自各指狀部至各諧波終端電路為止之路徑之距離變短，而該距離更均勻化。
又，於半導體晶片100A~100F、500A~500C中，例如凸塊122a、122b(222a、222b、322a、322b、122x、122y)之長邊方向與凸塊123a~123d(123ax~123dx、123ay~123dy)之長邊方向亦可正交。
以上所說明之各實施形態係用以使本發明容易理解，而並非用以限定解釋本發明。本發明可於不脫離其主旨之狀態下進行變更或改良，並且本發明亦包含其等價物。即，發明所屬技術領域中具有通常知識者對各實施形態適當施加設計變更所得者只要具備本發明之特徵，則亦包含於本發明之範圍。例如，各實施形態所具備之各要素及其配置、材料、條件、形狀、大小等並不 限定於所例示者，可進行適當變更。又，各實施形態所具備之各要素可於技術上可行之範圍內進行組合，將該等組合而成者只要包含本發明之特徵，則亦包含於本發明之範圍。
100A‧‧‧半導體晶片
110‧‧‧半導體基板
111‧‧‧主面
120、121、122a、122b、123a~123d、124a~124g‧‧‧凸塊
CL‧‧‧中心線
S1~S4‧‧‧邊

Claims (8)

  1. 一種半導體晶片，其具備：第1電晶體，其將第1訊號放大並輸出第2訊號；第2電晶體，其將上述第2訊號放大並輸出第3訊號；及半導體基板，其具有與由第1方向及與上述第1方向交叉之第2方向規定之平面平行的主面，且形成有上述第1電晶體及上述第2電晶體；於上述半導體基板之上述主面上設置有：第1凸塊，其與上述第1電晶體之集極或汲極電性連接；第2凸塊，其與上述第1電晶體之射極或源極電性連接；第3凸塊，其與上述第2電晶體之集極或汲極電性連接；及第4凸塊，其與上述第2電晶體之射極或源極電性連接；於俯視上述半導體基板之上述主面時，上述第1凸塊呈圓形，上述第2、第3及第4凸塊呈矩形或橢圓形，上述第2、第3及第4凸塊之面積分別大於上述第1凸塊之面積。
  2. 如申請專利範圍第1項之半導體晶片，其中，上述半導體基板之上述主面為具有與上述第1方向平行之第1邊及第2邊之矩形；上述第3凸塊係以長邊方向與上述第1方向大致平行之方式配置於上述第1邊之附近。
  3. 如申請專利範圍第2項之半導體晶片，其中，於上述半導體基板之上述主面上且上述第2邊之附近，進而設置第5凸塊；於俯視上述半導體基板之上述主面時，上述第5凸塊呈圓形，上述第3凸塊之面積大於上述第5凸塊之面積， 上述第3凸塊之長邊方向之長度短於上述第4凸塊之長邊方向之長度。
  4. 如申請專利範圍第2或3項之半導體晶片，其中，上述第3凸塊包含個別地形成之第1部分及第2部分；於上述半導體基板之上述主面上進而設置第6凸塊，該第6凸塊與使上述第3訊號之諧波衰減的濾波電路之一部分電性連接；於俯視上述半導體基板之上述主面時，上述第3凸塊之上述第1部分及上述第2部分分別於上述第1邊之附近，相對於上述第1方向之中心線大致對稱地配置，上述第6凸塊於上述第1邊之附近，配置於上述第3凸塊之上述第1部分及上述第2部分之間且上述中心線附近。
  5. 如申請專利範圍第2或3項之半導體晶片，其中，於上述半導體基板之上述主面上進而設置第6凸塊，該第6凸塊與使上述第3訊號之諧波衰減的濾波電路之一部分電性連接；上述第6凸塊包含個別地形成之第1部分及第2部分；於俯視上述半導體基板之上述主面時，上述第6凸塊之上述第1部分及上述第2部分分別於上述第1邊之附近，相對於上述第1方向之中心線大致對稱地配置，上述第3凸塊配置於上述第6凸塊之上述第1部分及上述第2部分之間。
  6. 如申請專利範圍第1至3項中任一項之半導體晶片，其中，於俯視上述半導體基板之上述主面時，上述第3凸塊之長邊方向與上述第4凸塊之長邊方向正交。
  7. 如申請專利範圍第4項之半導體晶片，其中，於俯視上述半導體基板之上述主面時，上述第3凸塊之長邊方向與上述第4凸塊之長邊方向正交。
  8. 如申請專利範圍第5項之半導體晶片，其中，於俯視上述半導體基板之上述主面時，上述第3凸塊之長邊方向與上述第4凸塊之長邊方向正交。
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CN208062050U (zh) 2018-11-06
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