CN108364946A - 半导体芯片 - Google Patents

半导体芯片 Download PDF

Info

Publication number
CN108364946A
CN108364946A CN201810069147.4A CN201810069147A CN108364946A CN 108364946 A CN108364946 A CN 108364946A CN 201810069147 A CN201810069147 A CN 201810069147A CN 108364946 A CN108364946 A CN 108364946A
Authority
CN
China
Prior art keywords
salient point
transistor
semiconductor chip
interarea
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201810069147.4A
Other languages
English (en)
Other versions
CN108364946B (zh
Inventor
嶋本健
嶋本健一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Publication of CN108364946A publication Critical patent/CN108364946A/zh
Application granted granted Critical
Publication of CN108364946B publication Critical patent/CN108364946B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H01L27/0211—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique adapted for requirements of temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H01L2224/14051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14152—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry being non uniform, i.e. having a non uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1416—Random layout, i.e. layout with no symmetry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/14177—Combinations of arrays with different layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1451—Function
    • H01L2224/14515—Bump connectors having different functions
    • H01L2224/14519—Bump connectors having different functions including bump connectors providing primarily thermal dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13051—Heterojunction bipolar transistor [HBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13054—Darlington transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1424—Operational amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/411—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising two power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提供一种能缩小安装面积，并能抑制晶体管的发热的影响的半导体芯片。半导体芯片包括：对第1信号进行放大并输出第2信号的第1晶体管；对第2信号进行放大并输出第3信号的第2晶体管；以及具有平行于由第1方向及第2方向所规定的平面的主面，并形成有第1及第2晶体管的半导体基板，主面上设有：与第1晶体管的集电极或漏极相连接的第1凸点；与第1晶体管的发射极或源极相连接的第2凸点；与第2晶体管的集电极或漏极相连接的第3凸点、及与第2晶体管的发射极或源极相连接的第4凸点，在俯视主面时，第1凸点呈圆形，第2、第3及第4凸点呈矩形或椭圆形，第2、第3及第4凸点的面积比第1凸点的面积要大。

Description

半导体芯片
技术领域
本发明涉及半导体芯片。
背景技术
作为将半导体芯片安装于基板的方法之一，具有使用了凸点的倒装芯片技术。倒装芯片技术一般而言，具有与引线接合相比能缩小安装面积的优点。
发明内容
发明所要解决的技术问题
这里，例如在移动电话等移动通信设备中使用功率放大电路。功率放大电路中用于放大功率的晶体管具有温度特性。因此，若晶体管因放大动作而发热，则晶体管的特性会因温度的上升而产生变动。若在上述功率放大电路中使用上述倒装芯片技术，则会具有如下问题：虽然安装面积有所缩小，但未充分进行散热，对晶体管的特性产生影响。
本发明是鉴于上述情况而完成的，其目的在于，提供一种能缩小安装面积，并能抑制晶体管发热的影响的半导体芯片。
解决技术问题所采用的技术方案
为了达成上述目的，本发明的一个侧面所涉及的半导体芯片包括：对第1信号进行放大并输出第2信号的第1晶体管；对第2信号进行放大并输出第3信号的第2晶体管；以及具有平行于由第1方向及与第1方向交叉的第2方向所规定的平面的主面，并形成有第1晶体管及第2晶体管的半导体基板，半导体基板的主面上设有：与第1晶体管的集电极或漏极电连接的第1凸点；与第1晶体管的发射极或源极电连接的第2凸点；与第2晶体管的集电极或漏极电连接的第3凸点；及与第2晶体管的发射极或源极电连接的第4凸点，在俯视半导体基板的主面时，第1凸点呈圆形，第2、第3及第4凸点呈矩形或椭圆形，第2、第3及第4凸点的面积分别比第1凸点的面积要大。
发明效果
根据本发明，能提供一种能缩小安装面积，并能抑制晶体管的发热的影响的半导体芯片。
附图说明
图1是形成于本发明的实施方式1所涉及的半导体芯片的功率放大电路的电路图。
图2是本发明的实施方式1所涉及的半导体芯片的俯视图。
图3是本发明的实施方式2所涉及的半导体芯片的俯视图。
图4是本发明的实施方式3所涉及的半导体芯片的俯视图。
图5是本发明的实施方式4所涉及的半导体芯片的俯视图。
图6是本发明的实施方式5所涉及的半导体芯片的俯视图。
图7是本发明的实施方式6所涉及的半导体芯片的俯视图。
图8是本发明的实施方式7所涉及的半导体芯片的俯视图。
图9是本发明的实施方式8所涉及的半导体芯片的俯视图。
图10是本发明的实施方式9所涉及的半导体芯片的俯视图。
具体实施方式
下面，参照附图对本发明的实施方式进行详细说明。以下附图的记载中，相同或类似的结构要素以相同或类似的标号来表示。附图是例示，各部分尺寸、形状是示意性的，不应将本发明的技术范围限定于该实施方式来进行解释。
首先，参照图1及图2并对本发明的实施方式1所涉及的半导体芯片进行说明。此处，图1是形成于本发明的实施方式1所涉及的半导体芯片的功率放大电路的电路图，图2是本发明的实施方式1所涉及的半导体芯片的俯视图。
图1所示的功率放大电路10例如包括放大器20、21。放大器20、21分别进行无线频率(RF：Radio Frequency)信号的放大。本实施方式中，放大器20、21作为由例如异质结双极晶体管(HBT：Heterojunction Bipolar Transistor)等双极晶体管构成的部件来进行说明。另外，放大器20、21也可以由场效应晶体管(MOSFET：Metal-oxide-semiconductorField-effect Transistor)等其他晶体管构成。该情况下，将基极、集电极及发射极分别替换读成栅极、漏极及源极即可。
初级(驱动级)的放大器20包含晶体管Q1(第1晶体管)。晶体管Q1对输入信号RF1(第1信号)进行放大，输出放大信号RF2(第2信号)。后级(功率级)的放大器21包含晶体管Q2(第2晶体管)。晶体管Q2对放大信号RF2进一步进行放大，输出放大信号RF3(第3信号)。具体而言，晶体管Q1中，输入信号RF1被提供至基极，电源电压被提供至集电极，发射极接地。晶体管Q1对输入信号RF1进行放大，从集电极输出放大信号RF2。晶体管Q2中，放大信号RF2被提供至基极，电源电压被提供至集电极，发射极接地。晶体管Q2对放大信号RF2进一步放大，从集电极输出放大信号RF3。另外，虽省略了图示，但功率放大电路10还可以包括偏置电路及匹配电路等其他电路。此外，本实施方式中，示出了放大器的级数为两级的例，但放大器的级数不限于两级，可以是3级以上。此外，图1中示出双极晶体管，但也可以用FET(Field-Effect Transistor)来取代该双极晶体管。
接着，参照图2，对形成有功率放大电路10的半导体芯片进行说明。图2所示的半导体芯片100A例如包含半导体基板110、和设置于半导体基板110的主面上的多个凸点120～124g。
半导体基板110具有与由例如X轴方向(第1方向)及与X轴方向交叉(图2中进行正交)的Y轴方向(第2方向)所规定的平面平行的主面111。半导体基板110的材料并无特别限定，例如以化合物半导体作为主要成分。图2是半导体基板110的主面111侧的俯视图，主面111具有与X轴平行的边S1(第1边)、S2(第2边)、与Y轴平行的边S3、S4。图2中进行了省略，半导体基板110例如形成有构成图1所示的初级的放大器20的晶体管Q1、构成后级的放大器21的晶体管Q2。各晶体管Q1、Q2分别通过将例如多个叉指(finger)排列配置在XY平面方向上而构成。
半导体芯片100A通过使用了凸点的倒装技术安装于模块基板(未图示)。由此，形成于该半导体芯片100A的各放大器20、21与形成于模块基板的路径电连接。
另外，安装有半导体芯片100A的模块基板例如可以是PCB(Print Circuit Board：印刷电路板)、低温共烧陶瓷(LTCC：Low Temperature Co-fired Ceramics)等基板。该模块基板除了半导体芯片100A以外，也安装有功率放大电路的输出匹配电路、对发送信号与接收信号进行分离的双工器、开关电路等其他电路。作为双工器，例如可以使用声表面波(SAW：Surface Acoustic Wave)滤波电路、IHP-SAW(Incredible High Performance-SAW：超高性能声表面波)滤波电路。
图2所示的凸点120、121、122a、122b、123a～123d是分别将晶体管Q1、Q2的集电极及发射极、与半导体芯片100A的外部进行电连接的凸点。此外，凸点124a～124g并无特别限定，例如是起到用于从半导体芯片100A的外部进行电源电压的供给、输入信号的供给、接地电位的供给、或控制信号的供给等的端子的功能的凸点。另外，各凸点120～124g并无特别限定，例如可以是Cu柱状凸点、或者焊料凸点等。以下，对凸点120～123d进行具体说明。
凸点120(第1凸点)是与构成初级的晶体管Q1的各叉指的集电极进行电连接的凸点。凸点120例如在俯视主面111时呈圆形。
凸点121(第2凸点)是与构成初级的晶体管Q1的各叉指的发射极进行电连接的凸点。凸点121例如在俯视主面111时呈矩形，该矩形具有与X轴平行的短边方向和与Y轴平行的长边方向。此外，在俯视主面111时，凸点121的面积比凸点120的面积要大。另外，与晶体管Q1的集电极及发射极相连接的叉指数在图2中分别为一个，但并不限于一个，可以是多个。
凸点122a(第3凸点的第1部分)、122b(第3凸点的第2部分)是与构成后级的晶体管Q2的各叉指的集电极进行电连接的凸点。凸点122a、122b各自单独形成，被配置为相对于半导体基板110的X轴方向的中心线CL呈大致对称。凸点122a、122b例如在俯视主面111时呈矩形，该矩形具有与X轴平行的长边方向和与Y轴平行的短边方向。此外，凸点122a、122b分别被配置为在边S1的附近其长边方向与X轴呈大致平行。像这样，凸点122a、122b被配置在半导体基板110的外框附近，由此从晶体管Q2输出的放大信号RF3输出至半导体芯片外部时的路径变短。此外，在俯视主面111时，凸点122a、122b的面积均比凸点120的面积要大。另外，与晶体管Q2的集电极相连接的凸点个数在图2中为两个，但并不特别限定于两个，可以是一个或三个以上。
凸点123a～123d(第4凸点)是与构成后级的晶体管Q2的各叉指的发射极进行电连接的凸点。换言之，构成晶体管Q2的多个叉指在配置有凸点123a～123d的区域中，被排列配置于XY平面方向。凸点123a～123d分别单独形成于凸点120与凸点122a、122b之间的区域中，且以相对于半导体基板110的X轴方向的中心线CL呈大致对称的方式在X轴方向上并排配置四个。凸点123a～123b例如在俯视主面111时呈矩形，该矩形具有与X轴平行的短边方向和与Y轴平行的长边方向。即，凸点122a、122b的长边方向与凸点123a～123d的长边方向正交。此外，在俯视主面111时，凸点123a～123b的面积均比凸点120的面积要大。另外，与晶体管Q2的发射极相连接的凸点个数在图2中为四个，但并不特别限定于四个，可以是一个或三个，也可以是五个以上。
凸点124a～124g的形状并无特别限定，本实施方式中，在俯视主面111时呈圆形。凸点124a～124e(第5凸点)分别在半导体基板110的外框中、边S1的对边即边S2的附近沿着边S2配置。凸点124f配置于边S4的旁边。凸点124g配置在相对于中心线CL与凸点120大致对称的位置。
接着，对凸点121～123d呈矩形的理由进行说明。形成于半导体芯片100A的晶体管Q1、Q2在动作状态下发热，因此元件的温度有所上升。晶体管具有一般的温度特性，因此放大动作的特性因温度的上升而得以变动。这里，俯视主面111时的凸点的面积越大，与模块基板的粘接面积越大，因此经由凸点散热的热量增大。然而，伴随凸点面积的增大，芯片面积也增大。
这一点，在半导体芯片100A中，连接到发热量较多的初级的晶体管的发射极和发热量更多的后级的晶体管Q2的集电极及发射极的凸点121、122a、122b、123a～123d为矩形，连接到初级的晶体管Q1的集电极的凸点120为圆形。由此，凸点121、122a、122b、123a～123d的面积比凸点120的面积要大，经由凸点进行散热的热量较多。因此，与未使用倒装芯片技术的结构相比，根据半导体芯片100A，能缩小安装面积，并能抑制晶体管的发热的影响。
另外，本实施方式中，连接有晶体管Q1的集电极的凸点120为圆形，但凸点120也可以是矩形以取代圆形。此外，凸点121、122a、122b、123a～123d也可以是椭圆形以取代矩形。
图3是本发明的实施方式2所涉及的半导体芯片的俯视图。图3所示的半导体芯片100B与图2所示的半导体芯片100A相比，连接至晶体管Q2的集电极的凸点的形状不同。具体而言，半导体芯片100B具备凸点222a、222b以取代凸点122a、122b。
凸点222a(第3凸点的第1部分)、222b(第3凸点的第2部分)与凸点122a、122b同样地与晶体管Q2的集电极相连接，将从晶体管Q2输出的放大信号RF3输出至半导体芯片100B的外部。此外，凸点222a、222b分别配置为在边S1的附近其长边方向与X轴呈大致平行。这里，凸点222a、222b各自的长边方向(图3中的X轴方向)的长度L2比连接晶体管Q2的发射极的凸点123a～123d各自的长边方向(图3中的Y轴方向)的长度L1要长。由此，半导体芯片100B与半导体芯片100A相比，能进一步提高散热的效果。
图4是本发明的实施方式3所涉及的半导体芯片的俯视图。图4所示的半导体芯片100C与图2所示的半导体芯片100A相比，连接至晶体管Q2的集电极的凸点的形状不同。具体而言，半导体芯片100C具备凸点322a、322b以取代凸点122a、122b。
凸点322a(第3凸点的第1部分)、322b(第3凸点的第2部分)与凸点122a、122b同样地与晶体管Q2的集电极相连接，将从晶体管Q2输出的放大信号RF3输出至半导体芯片100C的外部。此外，凸点322a、322b分别配置为在边S1的附近其长边方向与X轴呈大致平行。这里，凸点322a、322b各自的长边方向(图3中的X轴方向)的长度L3比连接晶体管Q2的发射极的凸点123a～123d各自的长边方向(图3中的Y轴方向)的长度L1要短。
即，为了散热，优选为如上述半导体芯片100B所示那样使连接至集电极的凸点的面积较大。然而，一般而言，凸点具有面积越大，该凸点的厚度(即、主面111的法线方向的厚度)越容易变厚的趋势。因此，若假设形成于边S1附近的凸点的面积过大，则该凸点的厚度会变得比形成于边S1的对边即边S2附近的凸点124a～124e的厚度要厚。该情况下，例如面积较小的凸点124a～124e因凸点的厚度的不均匀而从模块基板浮起，容易引起连接不良等。
这一点，根据半导体芯片100C，能避免凸点322a、322b的面积与凸点124a～124e的面积相比变得过大。因此，抑制接触不良，提高半导体芯片100C安装时的搭载性。
另外，图4中，示出了凸点322a、322b的个数为两个的示例，但该凸点的个数也可以是三个以上。凸点的个数越多，能使单位凸点的面积越小，因此易于抑制与形成于对边附近的凸点124a～124e之间的高度的不均匀。
图5是本发明的实施方式4所涉及的半导体芯片的俯视图。图5所示的半导体芯片100D与图4所示的半导体芯片100C相比，还包括凸点400。
凸点400(第6凸点)与高次谐波终端电路的一部分电连接，该高次谐波终端电路是使从晶体管Q2的集电极输出的放大信号RF3的高次谐波(例如二次谐波、三次谐波、或四次谐波等)衰减的滤波电路的一个具体例。具体而言，在例如高次谐波终端电路由串联连接的电容器及电感器构成的情况下，凸点400可以是与形成于半导体基板110侧的电容器、形成于模块基板侧的电感器相连接的端子。如图5所示，凸点400设置于半导体基板110的主面111上，俯视主面111时呈圆形。此外，凸点400在例如边S1的旁边，被配置于凸点322a(第3凸点的第1部分)与凸点322b(第3凸点的第2部分)之间即中心线CL的附近。像这样，通过将凸点400配置于X轴方向的中心附近，从构成晶体管Q2的多个叉指到高次谐波终端电路为止的路径的距离被均匀化。由此，抑制因该路径的距离偏差而引起的高次谐波终端电路的特性的变动。
另外，本实施方式中，凸点400为圆形，但凸点400也可以是矩形或椭圆形以取代圆形。
图6是本发明的实施方式5所涉及的半导体芯片的俯视图。图6所示的半导体芯片100E与图5所示的半导体芯片100D相比具备凸点410a、410b以取代凸点400。
凸点410a(第6凸点的第1部分)、410b(第6凸点的第2部分)各自单独形成，且与凸点400同样地与高次谐波终端电路的一部分电连接，该高次谐波终端电路使从晶体管Q2的集电极输出的放大信号RF3的高次谐波衰减。即，半导体芯片100E中，设想形成有两个高次谐波终端电路的结构。如图6所示，凸点410a、410b分别设置于半导体基板110的主面111上，俯视主面111时呈圆形。此外，凸点410a、410b分别例如在边S1的旁边相对于中心线CL大致对称地配置。由此，通过将凸点410a、410b相对于中心线CL大致对称地配置两个，从而与半导体芯片100D相比，从各叉指到各高次谐波终端电路为止的路径的距离变短，该距离进一步被均匀化。
另外，本实施方式中，凸点410a、410b为圆形，但凸点410a、410b也可以是矩形或椭圆形以取代圆形。
此外，本实施方式中，凸点322a与凸点322b配置于凸点410a与凸点410b之间，但也可以将凸点410a与凸点410b配置于凸点322a与凸点322b之间。
此外，本实施方式中的两个高次谐波终端电路可以设计为均使相同频率的高次谐波(例如均是二次谐波等)终止，或者可以设计为使不同频率的高次谐波(例如二次谐波与三次谐波等)终止。
图7是本发明的实施方式6所涉及的半导体芯片的俯视图。图7所示的半导体芯片100F与图6所示的半导体芯片100E相比，连接至高次谐波终端电路的一部分的凸点的形状不同。具体而言，半导体芯片100F具备凸点420a、420b以取代凸点410a、410b。
凸点420a(第6凸点的第1部分)、420b(第6凸点的第2部分)单独形成，且与凸点410a、410b同样地与高次谐波终端电路的一部分电连接，该高次谐波终端电路使从晶体管Q2的集电极输出的放大信号RF3的高次谐波衰减。俯视主面111时，凸点420a、420b与凸点322a、322b同样地呈矩形，该矩形具有与X轴平行的长边方向和与Y轴平行的短边方向。由此，通过使凸点420a、420b的形状与凸点322a、322b的形状相同，从而易于统一凸点420a、420b的厚度与凸点322a、322b的厚度。因此，根据半导体芯片100F，与半导体芯片100E相比，半导体芯片安装时的搭载性有所提高。
图8是本发明的实施方式7所涉及的半导体芯片的俯视图。图8所示的半导体芯片500A中形成有两组图1所示的功率放大电路10。另外，半导体芯片500A中，仅对与相当于功率放大电路10所包含的晶体管Q1、Q2的晶体管的各端子相连接的凸点进行说明，对于其他凸点(相当于图2中的凸点124a～124g)省略说明。
半导体芯片500A在半导体基板510中具有相对于X轴方向的中心线CL对称的两个区域520x、520y。一个区域520x中设有凸点120x、121x、122x、123ax～123dx。同样，区域520y中设有凸点120y、121y、122y、123ay～123dy。分别设置于上述两区域520x、520y的各凸点相当于图2所示的凸点120、121、122a、122b、123a～123d，因此省略详细的说明。
半导体芯片500A中，分别在两个区域520x、520y中形成有功率放大电路。半导体芯片500A具备两个功率放大电路，从而能根据例如输入信号RF1的频带(例如高频、中频或低频等)区分放大的电路。或者，可以根据输入信号RF1的通信标准(例如2G(第2代移动通信系统)、3G(第3代移动通信系统)、或4G(第4代移动通信系统)等)区分放大的电路。另外，可以是如下结构：在形成于区域520x、520y中的某一个区域的功率放大电路处于动作中的情况下，使形成于另一个区域的功率放大电路停止动作。
上述结构中，在半导体芯片500A中，连接到发热量较多的初级的晶体管的发射极、后级的晶体管的集电极及后级的晶体管的发射极的凸点121x、121y、122x、122y、123ax～123dx、123ay～123dy的面积也比连接到初级的晶体管的集电极的凸点120x、120y的面积要大。由此，与半导体芯片100A同样地能缩小安装面积，并能抑制晶体管的发热的影响。
另外，连接到后级的晶体管的集电极的凸点可以如图8所示那样每个功率放大电路中有一个，也可以如图2所示那样有多个。
图9是本发明的实施方式8所涉及的半导体芯片的俯视图。图9所示的半导体芯片500B与图8所示的半导体芯片500A相比，还包括凸点600x、600y。
凸点600x、600y分别设置于半导体基板510的区域520x、520y。凸点600x、600y分别与图5所示的凸点400同样地与高次谐波终端电路的一部分电连接，该高次谐波终端电路使从后级的晶体管的集电极输出的放大信号RF3的高次谐波衰减。
根据上述结构，半导体芯片500B能获得与半导体芯片500A相同的效果。
另外，功率放大电路所具备的高次谐波终端电路可以如图9所示那样每个功率放大电路中有一个，也可以如图6所示那样有多个。
另外，本实施方式中，凸点600x、600y为圆形，但凸点600x、600y也可以是矩形或椭圆形以取代圆形。
图10是本发明的实施方式9所涉及的半导体芯片的俯视图。图10所示的半导体芯片500C与图8所示的半导体芯片500A相比，还包括凸点610x、620x、610y、620y。
凸点610x、620x被设置于半导体基板510的区域520x。凸点610y、620y被设置于半导体基板510的区域520y。凸点610x、620x、610y、620y均与图5所示的凸点400同样地与高次谐波终端电路的一部分电连接，该高次谐波终端电路使从后级的晶体管的集电极输出的放大信号RF3的高次谐波衰减。即，半导体芯片500C中与半导体芯片100E同样地设想每个功率放大电路具备两个高次谐波终端电路的结构。
根据上述结构，半导体芯片500C能获得与半导体芯片500A相同的效果。此外，如图10所示，与高次谐波终端电路相连接的凸点的形状可以是圆形、矩形、或椭圆形等各形状的组合。
以上，对本发明的例示的实施方式进行了说明。半导体芯片100A～100F、500A～500C中，在半导体基板110、510的主面上设有与初级的晶体管Q1的集电极或漏极相连接的凸点120、与初级的晶体管Q1的发射极或源极相连接的凸点121、与后级的晶体管Q2的集电极或漏极相连接的凸点122a、122b(222a、222b、322a、322b、122x、122y)、与后级的晶体管Q2的发射极或源极相连接的凸点123a～123d(123ax～123dx、123ay～123dy)，在俯视半导体基板110、510的主面时，凸点120呈圆形，凸点121、122a、122b、123a～123d呈矩形或椭圆形，凸点121、122a、122b、123a～123d的面积分别比凸点120的面积要大。由此，凸点121、122a、122b、123a～123d与凸点120相比，经由凸点进行散热的热量较多。因此，与未使用倒装芯片技术的结构相比，根据半导体芯片100A～100F、500A～500C能缩小安装面积，并能抑制晶体管的发热的影响。
此外，半导体芯片100A～100F、500A～500C中，凸点122a、122b(222a、222b、322a、322b、122x、122y)以其长边方向与半导体基板110、510的一条边S1呈大致平行的方式配置于边S1的附近。由此，将从晶体管Q2输出的放大信号RF3输出到半导体芯片的外部时的路径变短，损耗得到抑制。
此外，半导体芯片100C～100F中，在边S1的对边即边S2的附近设有凸点124a～124e，凸点322a、322b的面积比凸点124a～124e的面积要大，凸点322a、322b的长边方向的长度比凸点123a～123d的长边方向的长度要短。由此，能避免凸点322a、322b的面积与凸点124a～124e的面积相比变得过大。因此，抑制接触不良，提高半导体芯片安装时的搭载性。
此外，半导体芯片100D中，还设置有与高次谐波终端电路的一部分相连接的凸点400。凸点322a、322b分别在边S1的附近相对于X轴方向的中心线CL大致对称地配置，凸点400在边S1的附近配置于凸点322a、322b之间，即配置于中心线CL附近。由此，从构成晶体管Q2的多个叉指到高次谐波终端电路为止的路径的距离被均匀化。由此，抑制因该路径的距离偏差而引起的高次谐波终端电路的特性的变动。
此外，半导体芯片100E、100F中，还设有与高次谐波终端电路的一部分相连接的凸点410a、410b(420a、420b)。凸点410a、410b(420a、420b)分别在边S1的附近相对于X轴方向的中心线CL大致对称地配置，凸点322a、322b配置于凸点410a、410b(420a、420b)之间。由此，与半导体芯片100D相比，根据半导体芯片100E、100F从各叉指到各高次谐波终端电路为止的路径的距离变短，该距离被进一步均匀化。
此外，半导体芯片100A～100F、500A～500C中，例如凸点122a、122b(222a、222b、322a、322b、122x、122y)的长边方向与凸点123a～123d(123ax～123dx、123ay～123dy)的长边方向可以正交。
以上说明的各实施方式是用于使本发明易于理解，并不用于对本发明进行限定解释。本发明在不脱离其发明思想的前提下，可以进行变更或改良，并且本发明中也包含其等效发明。即，本领域技术人员可对各实施方式施加适当的设计变更，只要具备本发明的特征，就包含在本发明的范围内。例如，各实施方式所具备的各要素及其配置、材料、条件、形状、尺寸等并不限于例示的内容，能进行适当变更。另外，各实施方式所具备的各要素能够在技术允许的范围内进行组合，它们的组合只要具备本发明的特征，就包含在本发明的范围内。
标号说明
10…功率放大电路、20、21…放大器、Q1、Q2…晶体管、100A～100F、500A～500C…半导体芯片、110、510…半导体基板、111…主面、120～124、222、322、400、410、420、600、610、620…凸点、520…区域、S1～S4…边、CL…中心线。

Claims (6)

1.一种半导体芯片，其特征在于，包括：
对第1信号进行放大并输出第2信号的第1晶体管；
对所述第2信号进行放大并输出第3信号的第2晶体管；以及
具有平行于由第1方向及与所述第1方向交叉的第2方向所规定的平面的主面，并形成有所述第1晶体管及所述第2晶体管的半导体基板，
所述半导体基板的所述主面上设有：
与所述第1晶体管的集电极或漏极电连接的第1凸点；
与所述第1晶体管的发射极或源极电连接的第2凸点；
与所述第2晶体管的集电极或漏极电连接的第3凸点；以及
与所述第2晶体管的发射极或源极电连接的第4凸点，
俯视所述半导体基板的所述主面时，
所述第1凸点呈圆形，所述第2凸点、所述第3凸点及所述第4凸点呈矩形或椭圆形，
所述第2凸点、所述第3凸点及所述第4凸点的面积分别比所述第1凸点的面积要大。
2.如权利要求1所述的半导体芯片，其特征在于，
所述半导体基板的所述主面是具有与所述第1方向平行的第1边及第2边的矩形，
所述第3凸点以其长边方向与所述第1方向大致平行的方式配置于所述第1边的附近。
3.如权利要求2所述的半导体芯片，其特征在于，
在所述半导体基板的所述主面上的所述第2边的附近还设有第5凸点，
俯视所述半导体基板的所述主面时，
所述第5凸点呈圆形，
所述第3凸点的面积比所述第5凸点的面积要大，
所述第3凸点的长边方向的长度比所述第4凸点的长边方向的长度要短。
4.如权利要求2或3所述的半导体芯片，其特征在于，
所述第3凸点包含单独形成的第1部分及第2部分，
所述半导体基板的所述主面上还设有与滤波电路的一部分电连接的第6凸点，该滤波电路使所述第3信号的高次谐波衰减，
俯视所述半导体基板的所述主面时，
所述第3凸点的所述第1部分及所述第2部分分别在所述第1边的附近相对于所述第1方向的中心线大致对称地配置，
所述第6凸点在所述第1边的附近位于所述第3凸点的所述第1部分及所述第2部分之间，即配置于所述中心线附近。
5.如权利要求2或3所述的半导体芯片，其特征在于，
所述半导体基板的所述主面上还设有与滤波电路的一部分电连接的第6凸点，该滤波电路使所述第3信号的高次谐波衰减，
所述第6凸点包含单独形成的第1部分及第2部分，
俯视所述半导体基板的所述主面时，
所述第6凸点的所述第1部分及所述第2部分分别在所述第1边的附近相对于所述第1方向的中心线大致对称地配置，
所述第3凸点配置于所述第6凸点的所述第1部分及所述第2部分之间。
6.如权利要求1至5的任一项所述的半导体芯片，其特征在于，
俯视所述半导体基板的所述主面时，所述第3凸点的长边方向与所述第4凸点的长边方向正交。
CN201810069147.4A 2017-01-27 2018-01-24 半导体芯片 Active CN108364946B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762451163P 2017-01-27 2017-01-27
US62/451,163 2017-01-27

Publications (2)

Publication Number Publication Date
CN108364946A true CN108364946A (zh) 2018-08-03
CN108364946B CN108364946B (zh) 2022-12-16

Family

ID=62980664

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201820122680.8U Active CN208062050U (zh) 2017-01-27 2018-01-24 半导体芯片
CN201810069147.4A Active CN108364946B (zh) 2017-01-27 2018-01-24 半导体芯片

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201820122680.8U Active CN208062050U (zh) 2017-01-27 2018-01-24 半导体芯片

Country Status (3)

Country Link
US (3) US10211073B2 (zh)
CN (2) CN208062050U (zh)
TW (1) TWI681524B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112104332A (zh) * 2019-06-18 2020-12-18 株式会社村田制作所 半导体元件和功率放大装置

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI681524B (zh) * 2017-01-27 2020-01-01 日商村田製作所股份有限公司 半導體晶片
WO2018168653A1 (ja) * 2017-03-14 2018-09-20 株式会社村田製作所 高周波モジュール
US10510722B2 (en) * 2017-06-20 2019-12-17 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method for manufacturing the same
JP2020010005A (ja) 2018-07-12 2020-01-16 株式会社村田製作所 半導体装置
JP2021002581A (ja) * 2019-06-21 2021-01-07 株式会社村田製作所 半導体装置
JP2021057457A (ja) 2019-09-30 2021-04-08 株式会社村田製作所 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1606155A (zh) * 2003-10-09 2005-04-13 先进封装技术私人有限公司 柱形结构
JP2007194305A (ja) * 2006-01-18 2007-08-02 Renesas Technology Corp 半導体装置
US20120286878A1 (en) * 2011-05-10 2012-11-15 Skyworks Solutions, Inc. Apparatus and methods for electronic amplification
CN208062050U (zh) * 2017-01-27 2018-11-06 株式会社村田制作所 半导体芯片

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3250851A (en) * 1964-06-22 1966-05-10 Systems Engineering Lab Inc Universal transistor mounting pad
US3549107A (en) * 1968-03-25 1970-12-22 Honeywell Inc Control apparatus
EP0496491A1 (en) * 1991-01-22 1992-07-29 National Semiconductor Corporation Leadless chip resistor capacitor carrier for hybrid circuits and a method of making the same
JPH1064956A (ja) * 1996-08-20 1998-03-06 Fujitsu Ltd フェースダウンボンディング半導体装置
US5796169A (en) * 1996-11-19 1998-08-18 International Business Machines Corporation Structurally reinforced ball grid array semiconductor package and systems
TW498602B (en) * 2000-05-30 2002-08-11 Alps Electric Co Ltd Circuit unit
TW535352B (en) * 2000-05-30 2003-06-01 Alps Electric Co Ltd Surface-mounting type electronic circuit unit
US20040232982A1 (en) * 2002-07-19 2004-11-25 Ikuroh Ichitsubo RF front-end module for wireless communication devices
TWI373925B (en) * 2004-02-10 2012-10-01 Tridev Res L L C Tunable resonant circuit, tunable voltage controlled oscillator circuit, tunable low noise amplifier circuit and method of tuning a resonant circuit
DE102004037817B4 (de) * 2004-08-04 2014-08-07 Epcos Ag Elektrisches Bauelement in Flip-Chip-Bauweise
US8841779B2 (en) * 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
US20090008764A1 (en) * 2007-07-02 2009-01-08 Hsin-Hui Lee Ultra-Thin Wafer-Level Contact Grid Array
US7564130B1 (en) * 2007-07-06 2009-07-21 National Semiconductor Corporation Power micro surface-mount device package
US20120098120A1 (en) * 2010-10-21 2012-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Centripetal layout for low stress chip package
US8643196B2 (en) * 2011-07-27 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for bump to landing trace ratio
US8863071B2 (en) * 2011-09-13 2014-10-14 Alcatel Lucent De-pop on-device decoupling for BGA
TWI495259B (zh) 2012-07-18 2015-08-01 Realtek Semiconductor Corp 低雜訊放大器
US9418950B2 (en) * 2013-04-24 2016-08-16 Skyworks Solutions, Inc. Multiple band multiple mode transceiver front end flip-chip architecture and circuitry with integrated power amplifiers
JP6066324B2 (ja) * 2013-08-23 2017-01-25 株式会社村田製作所 電子装置
WO2017026321A1 (ja) * 2015-08-10 2017-02-16 株式会社村田製作所 多層基板、部品実装基板及び部品実装基板の製造方法
CN207458915U (zh) * 2015-11-10 2018-06-05 株式会社村田制作所 多层基板、部件安装基板
JP2019079872A (ja) * 2017-10-23 2019-05-23 株式会社村田製作所 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1606155A (zh) * 2003-10-09 2005-04-13 先进封装技术私人有限公司 柱形结构
JP2007194305A (ja) * 2006-01-18 2007-08-02 Renesas Technology Corp 半導体装置
US20120286878A1 (en) * 2011-05-10 2012-11-15 Skyworks Solutions, Inc. Apparatus and methods for electronic amplification
CN208062050U (zh) * 2017-01-27 2018-11-06 株式会社村田制作所 半导体芯片

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NXP SEMICONDUCTORS: "《NXP product data sheet for BC847QAS》", 8 July 2015 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112104332A (zh) * 2019-06-18 2020-12-18 株式会社村田制作所 半导体元件和功率放大装置

Also Published As

Publication number Publication date
TW201843791A (zh) 2018-12-16
TWI681524B (zh) 2020-01-01
US10971377B2 (en) 2021-04-06
US20210193484A1 (en) 2021-06-24
CN208062050U (zh) 2018-11-06
US20190148172A1 (en) 2019-05-16
US20180218921A1 (en) 2018-08-02
CN108364946B (zh) 2022-12-16
US11676825B2 (en) 2023-06-13
US10211073B2 (en) 2019-02-19

Similar Documents

Publication Publication Date Title
CN208062050U (zh) 半导体芯片
US11631659B2 (en) High-frequency module and communication apparatus
US7898338B2 (en) High power integrated RF amplifier
CN105281689B (zh) 包括异质结双极晶体管(hbt)及互补金属氧化物半导体(cmos)装置的混合功率放大器
US11018629B2 (en) Integrated multiple-path power amplifier
TW201622142A (zh) 化合物半導體裝置及電力增幅模組
JP2005033350A (ja) 高周波電力増幅モジュールおよび半導体集積回路装置
JP2008109227A (ja) 高周波電力増幅器
US11990384B2 (en) Amplifier modules with power transistor die and peripheral ground connections
US11108361B2 (en) Integrated multiple-path power amplifier with interdigitated transistors
US20220021404A1 (en) Radio-frequency module and communication device
US11336234B2 (en) Power amplifier circuit
US11302659B2 (en) Semiconductor device
CN210578437U (zh) 低成本高集成度的射频芯片封装结构及射频功率放大器
TW202025621A (zh) 高頻功率放大器以及功率放大模組
CN107359863A (zh) 集成放大器
KR20230110791A (ko) 전자 부품 및 전자 장치
JP2001102460A (ja) 半導体装置
CN219164528U (zh) 一种带外信号抑制电路及印刷电路板
US20120068771A1 (en) Heterogeneous integration of harmonic loads and transistor feedback for improved amplifier performance
JP3238560U (ja) 集積パッケージ電子デバイス構造
CN220653368U (zh) 射频前端模组
JP2000106386A (ja) 高周波増幅器
JP2015082514A (ja) 半導体モジュール
CN1116376A (zh) 有线电视用推挽功放模块

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant