KR100597993B1 - 반도체 패키지용 범프, 그 범프를 적용한 반도체 패키지 및 제조방법 - Google Patents
반도체 패키지용 범프, 그 범프를 적용한 반도체 패키지 및 제조방법 Download PDFInfo
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- KR100597993B1 KR100597993B1 KR1020040024217A KR20040024217A KR100597993B1 KR 100597993 B1 KR100597993 B1 KR 100597993B1 KR 1020040024217 A KR1020040024217 A KR 1020040024217A KR 20040024217 A KR20040024217 A KR 20040024217A KR 100597993 B1 KR100597993 B1 KR 100597993B1
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Abstract
Description
본 발명에서는 도4에 도시된 바와같이 금속접착층(140)을 통해 반도체 칩(120)의 전극패드(110)와 접촉되는 제1범프부(150A)를 형성하고, 그 제1범프부(150A) 상에 인쇄회로기판(170)의 전극단자(160)와 접촉되는 제2범프부(150B)를 제1범프부(150A)에 비해 폭이 좁게 형성하여 범프(150A,150B)를 구성함에 따라 제1범프부(150A)의 면적을 넓게 확보하지 않고도, 범프(150A,150B)를 설정된 높이(H) 이상 형성할 수 있으며, 또한 제2범프부(150B)의 상면에 형성된 솔더 캡(180)과 인쇄회로기판(170)의 전극단자(160)들이 접촉될 때, 솔더 캡(180)이 납작하게 주변으로 퍼져 나가더라도, 인접하는 범프와 단락되는 것을 방지할 수 있게 된다. 이때, 제1범프부(150A)와 제2범프부(150B)는 필요에 따라 동일한 높이(H/2)로 형성되거나 또는 서로 다른 높이로 형성될 수 있다.
Claims (26)
- 반도체 칩과;상기 반도체칩의 표면에 형성된 금속접착층과;상기 금속접착층의 상부에 형성된 제1범프부와, 상기 제1범프부와 일체로 형성되고 상기 제1범프부의 상부에 제1범프부에 비해 폭이 작게 형성된 제2범프부로 구성된 범프부;를 포함하여 구성되는 것을 특징으로 하는 반도체 패키지용 범프.
- 제 1 항에 있어서, 상기 반도체 칩은 보호막에 의해 전극패드가 선택적으로 노출되고, 상기 금속접착층이 반도체 칩의 전극패드 상부 및 그 전극패드의 상부로부터 전극패드 주변의 보호막 상부까지 연장되도록 형성된 것을 특징으로 하는 반도체 패키지용 범프.
- 제 1 항에 있어서, 상기 제1,제2범프부는 Au, Sn/37Pb, Sn/95Pb, Cu, Sn/Ag 및 Ni 중 선택된 하나의 재질로 형성된 것을 특징으로 하는 반도체 패키지용 범프.
- 제 1 항에 있어서, 상기 제1,제2범프부는 동일한 높이로 형성되거나 또는 서로 다른 높이로 형성된 것을 특징으로 하는 반도체 패키지용 범프.
- 제 2 항에 있어서, 상기 반도체 칩의 전극패드는 Ti, Al, Cr 및 Cu 중 선택된 하나의 금속재질로 형성되거나 또는 Ti, Al, Cr 및 Cu 중 적어도 하나를 포함하는 합금 재질로 형성된 것을 특징으로 하는 반도체 패키지용 범프.
- 제 1 항 또는 제 2 항에 있어서, 상기 금속접착층은 상기 반도체 칩의 전극패드와 젖음특성이 우수한 TiW, Ti, Cr, Ni, V, Bi 및 Au 중 적어도 하나를 포함하는 금속재질로 형성된 것을 특징으로 하는 반도체 패키지용 범프.
- 제 1 항에 있어서, 상기 금속접착층은 100Å~20000Å 정도의 두께로 형성된 것을 특징으로 하는 반도체 패키지용 범프.
- 제 1 항에 있어서, 상기 제2범프부의 상면에 형성된 솔더 캡을 더 포함하여 구성된 것을 특징으로 하는 반도체 패키지용 범프.
- 제 8 항에 있어서, 상기 솔더 캡은 Pb/Sn, Sn/(5%)Pb 및 Sn/(2.5)Ag 중에 하나의 재질, 또는 Ag, Au, Bi 및 P 중에 적어도 하나의 재질이 Sn 이나 Pb 에 포함된 합금재질인 것을 특징으로 하는 반도체 패키지용 범프.
- 제 8 항에 있어서, 상기 솔더 캡의 상면에 Ni, V 및 P 중 선택된 하나의 재질로 형성되거나 또는 Ni, V 및 P 중 적어도 하나를 포함하는 합금재질로 형성된 확산방지막을 더 포함하여 구성된 것을 특징으로 하는 반도체 패키지용 범프.
- 제 1 항에 있어서, 상기 제2범프부의 폭은 상기 제1범프부의 폭에 비해 10㎛ ∼ 150㎛ 정도 작은 것을 특징으로 하는 반도체 패키지용 범프.
- 전극패드가 형성된 반도체 칩과;상기 반도체 칩의 표면에 형성되고, 상기 전극패드를 선택적으로 노출시키는 보호막과;상기 전극패드의 상부에 형성되고, 그 전극패드의 상부로부터 전극패드 주변의 보호막 상부까지 연장되도록 형성된 금속접착층과;상기 금속접착층의 상부에 형성된 제1범프부와, 상기 제1범프부와 일체로 형성되고 상기 제1범프부의 상부에 제1범프부에 비해 폭이 작게 형성된 제2범프부로 구성된 범프부; 및상기 범프부의 제2범프부 상면과 접촉되는 전극단자가 표면에 형성된 인쇄회로기판을 구비하여 구성되는 것을 특징으로 하는 반도체 패키지.
- 제 12 항에 있어서, 상기 제2범프부의 상면과 인쇄회로기판의 전극단자는 이방 전도성 파티클이 함유된 폴리머를 매개로 열압착 및 경화되어 접촉되는 것을 특징으로 하는 반도체 패키지.
- 제 13 항에 있어서, 상기 이방 전도성 파티클이 함유된 폴리머는 액상의 이방 전도성 접착제나 준 경화되어 일정 형상을 갖는 고상의 이방 전도성 필름인 것을 특징으로 하는 반도체 패키지.
- 제 13 항에 있어서, 상기 이방 전도성 파티클이 함유된 폴리머는 열경화성 수지 또는 열경화성과 열가소성이 조합된 수지를 주성분으로 하며, 구형 또는 각형 의 도전성 금속볼들이 함유된 것을 특징으로 하는 반도체 패키지.
- 제 15 항에 있어서, 상기 도전성 금속볼들은 Au, Ni, Ag 또는 Cu 중에 선택된 하나의 재질인 것을 특징으로 하는 반도체 패키지.
- 제 15 항에 있어서, 상기 도전성 금속볼들은 0.5㎛~10㎛ 정도의 입자 크기를 갖는 것을 특징으로 하는 반도체 패키지.
- 제 12 항에 있어서, 상기 제2범프부의 상면과 인쇄회로기판의 전극단자는 제2범프부의 상면에 형성된 솔더 캡을 통해 접촉되는 것을 특징으로 하는 반도체 패키지.
- 보호막에 의해 선택적으로 노출되는 적어도 하나의 전극패드가 형성된 반도체 칩 상에 금속접착층을 형성하는 공정과; 상기 금속접착층의 상부에 제1감광성 포토레지스트를 형성하고, 전면노광을 실시하는 공정과; 상기 전면노광된 제1감광성 포토레지스트 상에 제2감광성 포토레지스트를 형성하고, 국부노광을 실시하는 공정과; 상기 제2감광성 포토레지스트와 제1감광성 포토레지스트를 현상하는 공정과; 상기 제2감광성 포토레지스트와 제1감광성 포토레지스트가 현상되어 노출되는 금속접착층 상에 제1,제2범프부로 이루어지는 범프를 형성하는 공정과; 상기 제2감광성 포토레지스트와 제1감광성 포토레지스트를 제거하는 공정과; 상기 제2감광성 포토레지스트와 제1감광성 포토레지스트가 제거됨에 따라 노출되는 금속접착층을 식각하는 공정과; 상기 제2범프부의 상면에 인쇄회로기판의 전극단자를 접촉시키는 공정을 포함하여 이루어지는 것을 특징으로 하는 반도체 패키지의 제조방법.
- 제 19 항에 있어서, 상기 제1,제2범프부로 이루어지는 범프는 전기도금 방법이나 무전해 도금 방법을 통해 형성되는 것을 특징으로 하는 반도체 패키지의 제조방법.
- 제 19 항에 있어서, 상기 금속접착층은 스퍼터링, 열증착 또는 전자-빔 증착을 통해 100Å~20000Å 정도의 두께로 형성하는 것을 특징으로 하는 반도체 패키지의 제조방법.
- 제 19 항에 있어서, 상기 금속접착층을 식각하는 공정은 화학약품에 의한 습식식각이나 물리적 방법에 의한 건식식각을 통해 이루어지는 것을 특징으로 하는 반도체 패키지의 제조방법.
- 제 19 항에 있어서, 상기 제2범프부의 상면에 인쇄회로기판의 전극단자를 접촉시키는 공정은 제2범프부와 인쇄회로기판의 전극단자 사이에 이방 전도성 파티클이 함유된 폴리머를 위치시킨 다음 열압착 및 경화시키는 것을 특징으로 하는 반도체 패키지의 제조방법.
- 제 19 항에 있어서, 상기 제1,제2범프부로 이루어지는 범프를 형성한 다음 제2범프부의 상면에 솔더 캡을 형성하는 공정을 더 포함하여 이루어지는 것을 특징으로 하는 반도체 패키지의 제조방법.
- 제 24 항에 있어서, 상기 제2범프부의 상면에 형성된 솔더 캡은 인쇄회로기판의 전극단자와 100~400℃ 정도의 온도로 압착되어 본딩되는 것을 특징으로 하는 반도체 패키지의 제조방법.
- 제 24 항에 있어서, 상기 솔더 캡을 형성한 다음 솔더 캡의 상면에 확산방지층을 형성하는 공정을 더 포함하여 이루어지는 것을 특징으로 하는 반도체 패키지의 제조방법.
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US10/976,427 US7170170B2 (en) | 2004-04-08 | 2004-10-29 | Bump for semiconductor package, semiconductor package applying the bump, and method for fabricating the semiconductor package |
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US10217712B2 (en) * | 2016-12-16 | 2019-02-26 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and semiconductor process for manufacturing the same |
WO2018182613A1 (en) * | 2017-03-30 | 2018-10-04 | Intel Corporation | Formation of tall metal pillars using multiple photoresist layers |
US12015002B2 (en) * | 2021-08-30 | 2024-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip structure and method for forming the same |
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US5508561A (en) * | 1993-11-15 | 1996-04-16 | Nec Corporation | Apparatus for forming a double-bump structure used for flip-chip mounting |
JP2000323534A (ja) * | 1999-05-13 | 2000-11-24 | Sony Corp | 半導体素子の実装構造及び実装方法 |
US6940178B2 (en) * | 2001-02-27 | 2005-09-06 | Chippac, Inc. | Self-coplanarity bumping shape for flip chip |
JP2002261111A (ja) | 2001-03-06 | 2002-09-13 | Texas Instr Japan Ltd | 半導体装置及びバンプ形成方法 |
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KR20210152217A (ko) | 2020-06-08 | 2021-12-15 | 주식회사 더스타일리시 | 항아토피성을 구현하는 속옷 |
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US20050224991A1 (en) | 2005-10-13 |
US7170170B2 (en) | 2007-01-30 |
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