TW561563B - Flip-chip packaging process and its fixture - Google Patents
Flip-chip packaging process and its fixture Download PDFInfo
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- TW561563B TW561563B TW091124483A TW91124483A TW561563B TW 561563 B TW561563 B TW 561563B TW 091124483 A TW091124483 A TW 091124483A TW 91124483 A TW91124483 A TW 91124483A TW 561563 B TW561563 B TW 561563B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
561563561563
【發明領域】 一^覆晶封裝製程及其治具,特別係 填膠材料形成於一基板上的製程及其 本發明係有關於 一種以網版印刷將一 治具。 【發明背景】 隨著高密度、高功率的電子構裝的迫切需求,覆晶 曰二乂:)裝技術漸漸成為各界注意的焦‘點。所謂覆 曰曰1裝疋將稞晶(bare dle)以表面朝下的方式與基板[Field of the Invention] A flip-chip packaging process and a fixture thereof, particularly a process in which a filler material is formed on a substrate, and the present invention relate to a fixture by screen printing. [Background of the Invention] With the urgent demand for high-density, high-power electronic packaging, flip chip technology is becoming the focus of attention from all walks of life. The so-called cover is to install the bare dle with the substrate in a surface-down manner.
進行接合的技術。當使用有機基板(〇rganic :;幻的情況了’由於有機基板之熱膨脹係數(CTE; c〇e f日 1Cient of thermal expansi〇n)約為 AH 卿/t 與石夕晶片之CTE(約為4 ppm/它)羔 ^ , ΓΤί7 ^ , PPm/ 〇差距過大,於熱脹冷縮之 際CTE不匹配所弓:發之應力很容易導致接點損壞。 門隙内:哀二L可1性的考量’通常需要在基板與晶片$ 門隙内填入底膠(underfill),以 以降低接點所受到的應力,如刀月文至膠體精 .十.广1制破裂广延伸,而延長接點之疲勞壽命。此外,上 述底膝係絕緣物質,亦可防卜垃 # - 0 + 1 T防止接點間有雜質造成漏電流# 傳遞。數據顯不,有填底膠之結Techniques for joining. When using an organic substrate (〇rganic :; the case of the magic 'due to the coefficient of thermal expansion of the organic substrate (CTE; c〇ef 1 Cient of thermal expansi) is about AH Qing / t and the CTE of Shi Xi wafer (about 4 ppm / it) Lamb ^, ΓΤί7 ^, PPm / 〇 The gap is too large, the CTE does not match during thermal expansion and contraction: the stress caused by the stress can easily cause the contact to be damaged. Inside the door gap: L2 Considerations' Usually, an underfill is required to be filled in the gap between the substrate and the wafer to reduce the stress on the contacts, such as knife-to-moon to colloidal fines. 10. The wide cracks of the 1 system can be extended to extend the contact. The fatigue life of the point. In addition, the above-mentioned bottom knee is an insulating material, which can also prevent the transmission #-0 + 1 T to prevent the leakage of current # caused by impurities between the contacts.
UeliabiHty)高5-10倍。由於底構上:填底膠者其可^ 可靠W/豫曰4 由於底膠可有效地提昇接合之 製::因此在覆阳封襄製程中,填底膠為一不可… 【先前技藝】 然而,填膠製程最為人所話病者在於其充填與硬化UeliabiHty) 5-10 times higher. Because of the bottom structure: the primer can be ^ reliable W / Yu Yue 4 Because the primer can effectively improve the bonding system :: Therefore, in the process of covering Yang Fengxiang, the primer is an indispensable ... [Previous skill] However, the most talked about sickness in the filling process lies in its filling and hardening.
561563 五、發明說明(2) (c u r i n g)時間過長,導々 壯 填膠製程。 、、且衣生產之瓶頸大部份均發生在 =前底膠大都以液態封膠材料利用點膠(μ =、入’其製程首先將低黏性液態膠體 = 孔隙所形嶋晶片與封裂基板間微細 的毛細壓力(caPiUary pressure)作為 數並Λ滿接點間的間隙。此一製程的缺點有下二 =距離的平方成正比,例如對一個7_見方m 2溫度而定充填需時數分鐘至十數分鐘;⑴因二^ 有限二充填完成後封填體内容易殘存氣泡(void),界 ΐ ΐ m:不足,該氣泡很可能在後續的熱製程造成封 裝體的爆米化效應(popcorn)使封裝體失效,或在封 在承受應力時因應力集中而加速破壞而失效,、 接影響覆晶封I良率或產品可靠度與使用壽命;)都_曰組直 底膠填充叹備一次只能對單一個封裝體做點膠,如果要同 時對二個(含)以上的封裝體做點膠,勢必要準備多組設備 ,增加成本的負擔;(4)填充底膠之前,必須先將封裝基 板作成形,分離成單顆的封裝單元基板或封裝體,對後續 的製程,例如·· Flip Chip BGA封裝體的植球(ball 、’ placement)製程的產出(throughput)有不利的影響。 【發明概述】 胃 本發明之目的係提供一種覆晶封裝製程及其治具,可 以較短的時間,完成填底膠的製程,以改善習知的^程充 0702-8683TWF;91P46;Dwwang.ptd 第6頁 561563 五、發明說明(4) 裝製程中,以網版印刷將一填膠 於-基板上,所使用的印刷網版,^由”刷區塊形成 及其他區域,其中上述印刷區 3福::刷區塊;以 數個遮罩部·,以及複數個連接線,作為孔區;複 【實施例】 x及上述遮罩部之間之連結。 第一實%^ 第1 A〜1E圖係顯示出用以說明本 種覆晶封裝製程方法之流程,本月發本 裝中填底膠的製程以增加覆晶封二:2地完成覆晶封 考下列步驟:“日 的可靠度與使用壽命;請參 r声1:2:考1^圖’覆晶封裝基板100的-表面具有-防 知層102(s〇ider mask),亦稱「綠漆」, 中,上述的内部線路因受到銲料的污 ^ 7 有複數個以一特定方式排列的開孔106(opening),以 墊l〇4(bump pad)曝露出來,其排列方式係與所要接人的于 1C晶片300之主動表面31〇上覆晶凸塊31〇(繪示於第^ ) 的具有相同的排列方式;其中銲墊1()4係與上述覆口 基板1 00的内部線路連接,在後製程與Ic晶片:^ 第1 D圓)連接之後’使覆晶封裝基板_的㈣線(路 0702~8683TWF;91P46;Dwwang.ptd 第8頁 561563 五、發明說明(5) 片300導通,各銲墊1〇4之間的間隔距離(bump pad ρΗ(^) 較好為不小於180,’·而在銲墊⑻上已完成—預上锡膏 Uolder* paste)的製程,分別有一錫膏11〇形成於其上, =錫膏HG的=要成分為-金屬粉末與一助銲劑(未繪示於 圖面),用以%助覆晶凸塊31〇(繪示於第1D圖)與銲 的接合。 請參考第1B圖,將覆晶封裝基板1〇〇與一印刷網版· 對準(或將一印刷網版200與覆晶封裝基版丨〇〇對準), 墊104上的錫膏110與印刷網版2〇〇的遮罩部23〇對準,b曰片干 接合區1 50範圍内各銲墊開口丨〇6以外的區域與印刷網版 〇〇的開孔區220對準;將一填膝材料12〇置於印刷網版 ^,再以網版印刷以一刮刀21〇(S(lueegee)以一方向將填 膠材料120經由印刷網版2〇〇的開孔區22〇形成於晶片接人 區1 5 0範圍内各銲塾開口 1 〇 6以外的區域。 請參考第ic圖,係顯示填膠材料12〇已形成於晶 = 150範圍—内各銲塾開口⑽以外的區域;接下來請參考 圖,將-1C晶片3 00的複數個覆晶凸塊31〇與覆晶封 f板1、〇〇上相對應的銲墊104對準,其中覆晶凸塊31〇的、 =:為金、銅、銅基合金(Cu based aU〇y)、錫鉛合金、 或含錫的合金。 請參考第1E圖,將已對準的IC晶片3〇()與 ,〇接合,成為一封請00。之後可⑴以一不高= 二110之金屬粉末熔點或不高於覆晶凸塊3丨〇熔點之溫戶 …、封裝體400,使填膠材料120硬化之後,再以一不低ς錫口561563 V. Description of the invention (2) (c u r i n g) The time is too long, leading to a strong filling process. Most of the bottlenecks in the production of clothing occur when = the front primer is mostly dispensed with liquid sealant material (μ =, into the process, the low viscosity liquid colloid = the shape of the pores, the wafer and the seal The fine capillary pressure (caPiUary pressure) between the substrates is used as the number and the gap between the full contacts. The disadvantage of this process is that the next two = the square of the distance is proportional, such as the filling time required for a 7_ square m 2 temperature Several minutes to ten minutes; ⑴ due to the two ^ finite two filling is easy to remain voids in the sealing body, boundary , m: insufficient, the bubbles are likely to cause popcorn of the package in the subsequent thermal process The effect (popcorn) makes the package fail, or the seal is destroyed due to stress concentration and accelerated failure when it is under stress, which affects the yield of the flip-chip package or the reliability and service life of the product;) Filling can only be used to dispense a single package at a time. If you want to dispense two or more packages at the same time, it is necessary to prepare multiple sets of equipment to increase the cost burden; (4) Fill the primer Before the package substrate must be Shaped, separated into single packaging unit or package substrate, the subsequent processes, e.g. bumping ·· Flip Chip BGA package (ball, 'placement) process output (throughput) adversely affected. [Summary of the invention] The purpose of the present invention is to provide a flip-chip packaging process and its fixture, which can complete the process of filling the primer in a short time to improve the conventional process charge 0702-8683TWF; 91P46; Dwwang. ptd page 6 561563 V. Description of the invention (4) During the assembly process, a screen is used to fill a substrate on the substrate. The printing screen used is formed by "brush blocks" and other areas, where the above printing Area 3 blessing :: brushing the block; using several masks, and a plurality of connecting lines as the hole area; complex [example] the connection between x and the above masks. The diagrams A ~ 1E show the process used to explain this kind of flip-chip packaging process. This month, the process of filling the primer in this package is added to increase the flip-chip sealing. 2: Complete the flip-chip sealing and test the following steps: "Day Reliability and service life; please refer to r sound 1: 2: test 1 ^ picture 'the surface of the flip-chip package substrate 100-has a-guard layer 102 (sodium mask), also known as "green paint", middle, The above-mentioned internal circuit is contaminated by solder. 7 There are a plurality of openings 106 (openings) arranged in a specific manner. 4 (bump pad) is exposed, and its arrangement is the same as that of the crystal bumps 31o (shown at ^) on the active surface 31o of the 1C wafer 300 to be accessed; 1 () 4 is connected to the internal circuit of the above-mentioned cover substrate 100, and after the post-process is connected to the IC chip: ^ 1st circle), the 'make-up chip package substrate' (㈣ 0702 ~ 8683TWF; 91P46; Dwwang.ptd Page 8 561563 V. Description of the invention (5) The chip 300 is turned on, and the distance between the pads 104 (bump pad ρΗ (^) is preferably not less than 180, and the pad ⑻ The above has been completed—the process of pre-applying a solder paste (Uolder * paste), a solder paste 11 is formed thereon, = solder paste HG = the main ingredients are-metal powder and a flux (not shown in the figure), It is used to assist the bonding of the flip-chip bump 3110 (shown in FIG. 1D) and soldering. Please refer to FIG. 1B to align the flip-chip package substrate 100 with a printing screen and align (or print one The screen plate 200 is aligned with the flip-chip package base plate), the solder paste 110 on the pad 104 is aligned with the mask portion 23 of the printed screen plate 200, and the dry bonding area is in the range of 150 The areas outside the pad openings in the inside are aligned with the opening area 220 of the printing screen 〇〇; a knee filling material 120 is placed on the printing screen ^, and then screen printing is performed with a scraper 21 〇 ( S (lueegee) forms the filler material 120 in one direction through the opening area 22 of the printing screen 200 in a region other than the openings 106 of each solder pad within the range 150 of the wafer access area. Please refer to section The ic diagram shows that the filler material 12 has been formed in the area other than the openings of the solder joints within the range of crystal = 150. Next, referring to the figure, the plurality of crystalline wafer bumps 31 of the -1C wafer 3 00 and The corresponding solder pads 104 on the flip-chip package f board 1 and 〇 are aligned, where the flip-chip bumps 31 〇 =: gold, copper, Cu based alloy, tin-lead alloy, Or tin-containing alloys. Please refer to FIG. 1E, and join the aligned IC chip 3〇 () with, 0 to become a letter 00. After that, a metal powder with a melting point of not higher than two 110 or a temperature higher than the melting point of the flip-chip bump 3, and the package 400 can be used to harden the filling material 120, and then one can not lower the tin. mouth
I 第9頁 〇7〇2.8683W;91P46;Dwwang.ptd 561563 五、發明說明(7) 私,亦可以同時對1或數組,共具有g個封梦罝一 板進行填底膠的方法,視製程需求而定。的封裝基 的設^本===版的設計:式可依照封襄基板 能力、梦程· I、:、印刷機台(未繪示於圖面)的 衣私而求、或疋其他條件來作變更, -或複數個封裝單元或封裝體的―或複 有 填底膠的製程,並不限於在第2A圖中所舉的基板進- - rL參Λ第2B圖’係顯示第^圖中一印刷區塊51〇中的 -,域A的放大圖。藉由第2A、㈣可知印刷區塊51〇係由 稷數個開孔區512、遮罩部514、與連接線516所組成。其 中開孔區512係用以在網版印刷時,將一填膠材料(未缘示 於圖面)形成於一覆晶封裝基板(未缘示於圖面)上;遮罩、 部514係用以在網版印刷時,將上述覆晶封裝基板上不需 形成上述填膠材料的區域(例如銲塾或其他區域)予以遮罩 ’以避免上述填膠材料形成於上述不需形成上述填膠材料 的區域;連接線5 1 6係用以個別的遮罩部5 1 4之間的連結、 或疋個別的遮罩部5 1 4與印刷網版5 0 0其他區域的連结。 請注意開孔區5 1 2、遮罩部5 1 4、與連接線5 1 6的排列 方式與尺寸係依照所對應的覆晶封裝基板(未繪示於圖面) 的設計方式不同而可以有所調整,並不限於在第2B圖中戶斤 舉的例子;且遮罩部514之間的間隔距離較佳為不小於18〇 β m 〇 而印刷網版5 0 0的材質可以是金屬或是有機聚合物包 覆金屬的複合材料;另外為了防止印刷網版5 0 0的表面點I Page 9 〇7〇2.8683W; 91P46; Dwwang.ptd 561563 V. Description of the invention (7) Privately, you can also use 1 or an array with a total of g seal nightmare to fill the bottom of the board. Depending on process requirements. The design of the package base ==== version of the design: the formula can be based on the ability of the Fengxiang substrate, the dream course · I,:, the clothing of the printing press (not shown in the drawing), or other conditions To make changes,-or a plurality of packaging units or packages-or a process with a primer, is not limited to the substrate shown in Figure 2A-rLRef Λ Figure 2B 'shows ^ In the figure,-in a printed block 51 is an enlarged view of a domain A. It can be known from the 2A and the print block 51 that the print block 51 is composed of a plurality of opening regions 512, a mask portion 514, and a connection line 516. The opening area 512 is used to form a filler material (not shown in the drawing) on a flip-chip packaging substrate (not shown in the drawing) during screen printing; the mask and the part 514 are It is used to mask the areas on the flip-chip package substrate that do not need to form the filler material (such as solder pads or other areas) during screen printing to prevent the filler material from forming on the substrate without forming the filler material. Area of adhesive material; the connecting line 5 1 6 is used to connect the individual mask portions 5 1 4 or to connect the individual mask portions 5 1 4 to other areas of the printing screen 5 0 0. Please note that the opening area 5 1 2, the mask portion 5 1 4, and the arrangement and size of the connection line 5 1 6 are different according to the design method of the corresponding flip-chip package substrate (not shown in the figure). Some adjustments are not limited to the example shown in Figure 2B; and the distance between the mask portions 514 is preferably not less than 18〇β m 〇 The material of the printing screen 5 0 0 can be metal Or organic polymer-coated metal composites; in addition to prevent surface dots on screen printing 500
0702-8683TWF;91Ρ46;Dwwang.p td0702-8683TWF; 91Ρ46; Dwwang.p td
561563561563
五、發明說明(8) 附例如填膠材料等其他物質、防止£ 到腐蝕、或是防止印刷網版5〇〇的印刷網版5 0 0的表面受 印刷網版5 0 0的使用壽命或對填底3面义到到傷而影響到 以在上述印刷網版5 〇 〇表面上[膠的方法有所妨礙,可 層。 表面塗層或一表面鍍 露如上,然其並非用以 在不脫離本發明之精神 都’因此本發明之保護 定者為準。 雖然本發明已以較佳實施例揭 限定本發明:任何熟習此技藝者, 和範圍内,當可作些許之更動與潤 範圍當視後附之申請專利範圍所界V. Description of the invention (8) It is attached with other materials such as rubber packing materials, to prevent corrosion, or to prevent the surface of the printing screen 500 printing screen 500 from being affected by the life of the printing screen printing 500 or The filling of 3 sides of the bottom cover is so bad that it affects the method of using the glue on the surface of the above-mentioned printing screen 5,000. The surface coating or a surface plating is as described above, but it is not intended to be used without departing from the spirit of the invention. Therefore, the protection of the invention shall prevail. Although the present invention has been limited to the present invention by a preferred embodiment: Any person skilled in the art, and within the scope, can make a few changes and modifications. The scope is subject to the scope of the attached patent application.
561563 圖式簡單說明 【發明詳 為讓 顯易懂, 細說明如 【圖式之 第1A 施例之覆 第2A 實施例之 【符號說 100〜 104〜 110〜 150〜 210〜 230〜 310〜 50 0〜 512〜 516〜 細說明】 本發明之上述和其他目的、特徵、和優點能更明 下文特舉出較佳實施例,並配合所附圖式,作詳 下: 簡單說明】 - 〜1 E圖為一系列剖面圖,用以說明本發明第一實 晶封裝製程方法之流程。 〜2B圖為一示意圖,用以說明本發明本發明第二 覆晶封裝治具的組成。 明】 覆晶封裝基板 銲墊 錫膏 晶片接合區 刮刀 遮罩部 覆晶凸塊 印刷網版 開子L區 連接線 1 0 2〜防銲層 1 0 6〜銲墊開口 120〜填膠材料 2 0 0〜印刷網版 2 2 0〜開孔區 3 0 0〜I C晶片 400〜封裝體 5 1 0〜印刷區塊 5 1 4〜遮罩部561563 Brief description of the drawings [The invention is detailed for easy understanding, and the detailed description is as follows: [The first embodiment of the drawing overlaps the second embodiment of the 2A] [Symbols say 100 ~ 104 ~ 110 ~ 150 ~ 210 ~ 230 ~ 310 ~ 50 0 ~ 512 ~ 516 ~ Detailed description] The above and other objects, features, and advantages of the present invention can be made clearer. The preferred embodiments will be listed below, and will be described in detail with the accompanying drawings: Brief description]-~ 1 Figure E is a series of cross-sectional views for explaining the flow of the first solid-crystal packaging process method of the present invention. ~ 2B is a schematic diagram for explaining the composition of the second flip chip packaging jig of the present invention. Ming】 Flip-chip package substrate, solder pad, solder paste, wafer bonding area, scraper cover, flip-chip bump printing screen, opener, L-zone connection line 1 0 2 ~ solder mask 1 0 6 ~ pad opening 120 ~ filler 2 0 0 to printed screen 2 2 0 to open area 3 0 0 to IC chip 400 to package 5 1 0 to printed block 5 1 4 to mask
0702 - 8683W; 91P46; Dwwang. p t d 第13頁0702-8683W; 91P46; Dwwang. P t d p. 13
Claims (1)
Priority Applications (1)
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TW091124483A TW561563B (en) | 2002-10-23 | 2002-10-23 | Flip-chip packaging process and its fixture |
Applications Claiming Priority (1)
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TW091124483A TW561563B (en) | 2002-10-23 | 2002-10-23 | Flip-chip packaging process and its fixture |
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TW561563B true TW561563B (en) | 2003-11-11 |
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TW091124483A TW561563B (en) | 2002-10-23 | 2002-10-23 | Flip-chip packaging process and its fixture |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8232192B2 (en) | 2004-05-05 | 2012-07-31 | Megica Corporation | Process of bonding circuitry components |
-
2002
- 2002-10-23 TW TW091124483A patent/TW561563B/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8232192B2 (en) | 2004-05-05 | 2012-07-31 | Megica Corporation | Process of bonding circuitry components |
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