TW557555B - Flip chip package having underfill materials with different Young's module - Google Patents

Abstract

A flip chip package having underfill materials with different Young's module comprises a chip carrier having an upper surface and an opposite lower surface, at least a chip with a plurality of bumps electrically connected to the chip carrier, a first underfill material dipped onto the outer surface of the bumps to be enclosed each bump and a second underfill material used to fill the gap between the chip and the chip carrier. According to different physical properties of the underfill material, the first underfill material having higher Young's module enclosed to the bumps is capable of enhancing mechanical strength of solder joints to avoid decomposition and the second underfill material having lower Young's module may also decrease deformation of the chip and the chip carrier effectively. Thereby, using different underfill materials at the same package brings underfill into merits and decreases the cost of equipments to follow processes as known.

Description

557555

[Field of the invention]: Feng invention is a kind of cattle conductor package, especially a filler with Young's Modulus (Young, s Module), and J ^ rn, D, & filling material for the bottom A flip-chip semiconductor package (η under the ChipPackage). p [Background of the Invention]: Flip Chip BaU & id a FCBGA is an improved ball grid array packaging technology, which is an improvement over the traditional y 'body packaging technology, which lies in the packaged semiconductor wafer system. By flipping, the majority of solder bumps are used to electrically connect the active surface of the wafer downward to the substrate, and then most of the solder balls planted on the back of the substrate are electrically connected to the external device. Connection to reduce the overall size of the packaged product. However, after using the flip-chip method to place the wafer at a specific position on the substrate, the solder bumps are separated between the crystal 5 and the substrate, so that there is a gap between the adjacent solder bumps and between the wafer and the substrate. If the bottom gap of this flip chip is not filled, thermal stress (Stress) will be generated in the temperature cycle of the subsequent process because the wafer and the substrate each have different thermal expansion coefficients (CTE). Poor 'causes a crack (Crack) or electrical disability (Electronic F ai 1 ure) to appear in the joint joint. Therefore, the FCBGA type chip packaging process has a necessary step, which is to use an epoxy resin (E p 0X y R esi η) and other insulating glue to fill the gap at the bottom of the flip-chip to achieve strengthened structural support ( Mechanical

16902.ptd Page 5 557555 V. Description of the invention (2)

Support) and reduce the purpose of short circuit. However, the above-mentioned flip-chip structure is not disclosed in US Patent No. 5, 821,456. The electrical connection between the chip and the substrate is provided by a solder bump, which is a tin-lead alloy material, so When reflowing metallic bumps to the surface of non-metallic materials (such as wafers), in order to improve the adhesion of the bumps, the pad surface of the wafer needs to be provided with a metal purification layer (such as titanium or crane compounds). Carrier or Passivation) to prevent solder joints from being damaged during high-temperature processes; on the other hand, the wafer uses metal solder bumps during the circuit formation stage. It may also be caused by semiconductor wafers, metal passivation layers, and solder bumps. And the CTE difference between the substrates is large, which causes the package to generate different thermal stresses under temperature cycling, which causes the substrate flatness to decrease, cracks at the dry junctions, and even die cracks. This phenomenon is large. The impact of wafers or large-size packages is more significant; in addition, soldering tin-lead materials are generating, for example, Electrically Conductive Flux during the melting process (Melting). ) And other unintended by-products that impair the structural strength of the solder joints. For these reasons, the industry has the idea of replacing conductive tin (Pb) alloys with conductive polymers. U.S. Patent No. 5,237,130 " Flip Chip Technology Using Electrically Conductive Polymers And

Dielectrics & No. 6, 138, 348 " Method Of Forming

"Electrically Conductive Polymer Interconnects On Electrical Substrates" unveiled a semiconductor package using conductive polymer as a fresh block material.

16902.ptd Page 6 557555 V. Description of the invention (3) The thermal stress difference between the boards reduces the above problems: The semiconductor package 2 is formed with a plurality of pads m () on the first surface of the substrate 20 (: wafer 22). 222), screen printing (Cn surface Pnntmg), stencil printing (stenciu conductive filler (Conductive FiUe g 2: f): mixed with pad 204 (222) to form a lightning guide = organic polymer layout to B S), for the substrate 20 and the wafer 22 to be electrically connected to each other. The bump 21 (P0l — the physical medium MEMS guide at electrical rfitting: For the solder bump material, the degree of polymerization can be reduced by two The expansion coefficient of the film i is adjusted to be close to the substrate. The thermal stress difference between the Japanese-Japanese film, the block and the substrate is reduced, and the structural integrity of the σ part is shown. ^ _ Ruggedness indicates that the π connection fee is higher. :: Electric filler is costly to produce soldering pads and metal materials, so using conductive polymers as the dagger force is not good. 'Electricity is mixed, and 2; lb. The packaging of ghost materials is equivalent to I-level packaging. .., Semiconductors using tin ingots [Summary of the Invention]: The main purpose of the present invention is to provide a package system The bumps are chipped and the solder joints of the wafers are reduced, and the joints of the wafers are Qiu f ^ τ · Welding of the Nissan chip carrier on the outer side]: j (Solder Jolnt) is cracked due to deformation Complete semiconductor package. [Track] Complete Si: Said: In: To provide a flip-chip semiconductor package that maintains the structural reliance of the solder joint. The sheep and the mouth. The re-objective of the present invention It is to provide a method to maintain the plane of the wafer carrier. Page 7 l69〇2.ptd 557555 V. Description of the invention (4) Degree (planarity), so as to enable subsequent processes (such as ball planting or testing) and have a better operation reliability Crystalline semiconductor package. Another object of the present invention is to provide a flip-chip semiconductor package that can use existing process technology without increasing equipment cost. In order to achieve the above objective and other objectives & The chip-on-chip semiconductor package with bump collapse includes: a wafer carrier, a pot with a ridged surface and a lower surface. The upper surface is pre-laid with a plurality of conductive patterned locations (Conductive Patterned Locations), and at least one Conductive wire Most substrate pads are formed on the area; at least one semiconductor wafer is formed with a plurality of wafer pads arranged according to conductive lines, and a plurality of solder bumps are formed on a second-grade wafer pad for wafer and wafer carrying 2 For electrical connection, a first underfill is contaminated on each solder bump. After the wafer and the wafer carrier are welded, the surface of each solder bump is completely covered by the first underfill; a second bottom Filling glue is used to fill the gap between the wafer and the wafer carrier so that the two are completely in close contact; and implanted on the lower surface of the wafer carrier for the wafer to be electrically connected to the majority of the solder balls on the outside. The flip-chip semiconductor package of the present invention uses two kinds of underfill to implement an underfill process without increasing cost. The intention is to solve the various problems caused by the difference in CTE between wafers, solder bumps and Meiyi by different physical characteristics of the first underfill and the second underfill. In more detail, the first and the last bitter filling is a non-flowing filling (No —f 1〇w Underf i / 丨), where 1 has a higher Young's modulus (Young, s Module), that is, rigid and strong (Regidity); and the Young's modulus of the second underfill is lower, which is 16902.ptd Page 8 557555 V-Description of the invention (5) ---- The material is soft. The improvement of deformation is better; therefore, filling the first bottom with glue can strengthen the solder joint bumps around the old structure to prevent the formation of solder bumps; and the B strength 'avoids the gap between the carriers Filling with the second bottom glue can also reduce the degree of deformation of the bonding joint between the small piece and the wafer, so that the wafer carrier maintains the ^^ process degree and improves the reliability of the subsequent process operations. In this way, the plane of the present hairpin 5 can use the existing glue technology to achieve enhanced bonding at the same time. It is necessary to improve the package yield, especially the large size / large Q ° $. And quality is extremely helpful. Chip + conductor seal [Detailed description of the invention]: The following is a detailed description of the first embodiment of the crystalline semiconductor package of the present invention and the application of the under-filling process (Underf i 1 1) with the help of Figures 1 to 4. In some cases, the drawings attached in the embodiments simply indicate the types and structures of the components related to this embodiment. The actual number, type, and layout of the finished products are more complicated than the drawings. 'τ 70 FIG. 1 is a perspective cross-sectional view of a semiconductor package for preventing chipping of solder bumps according to the present invention. As shown in the figure, the semiconductor package is composed of a substrate 10, a wafer 12 which is electrically connected to the substrate 10 by a plurality of solder bumps 11, and a first chip which is wrapped around each solder bump 11 A bottom filler 13, a second bottom filler that fills the gap between the wafer 12 and the substrate 10, and a majority of 15 solder balls connected to the substrate 10 to provide the wafer 12 with electrical conductivity to the outside Make up. Wherein, the substrate 10 and the wafer 12 are electrically bonded in a flip-chip manner (F 丨 i ρ C h i ρ). However, this technology is known, so it will not be repeated here. The substrate 10 is made of FR-4 resin, BT (Bismaleimide

557555 V. Description of Invention (6)

A single-layer, double-layer, or multi-layer circuit board made of Triazine resin, polyimide resin, or other materials. The circuit board has an upper surface 100 and a relatively lower surface 101. A resin core layer (core) (not shown) is pre-patterned to form a plurality of conductive traces assembled by a plurality of conductive traces (as shown in FIG. 102). (Conductive Patterned Locations) (not shown), a conductive solder mask (Solder Mask) (as shown in FIG. 2) of the conductive circuit area is coated on the outside; A part of the conductive circuit area (not shown) is provided with a plurality of exposed openings of the solder resist layer, which are used for pre-plating of nickel, lead and other alloys to form a plurality of substrate pads 104; A plurality of solder balls 15 are planted, so that the chip can be electrically connected to the outside (such as a printed circuit board). The chip 12 is made of semiconductor materials such as silicon and gallium arsenide, and has a surface 120 (that is, a crystal surface where most electronic circuits and electronic components are arranged), and an opposite non-active surface i2i. The operation 122 uses m! To arrange a plurality of wafer pads arranged in accordance with conductive lines and a spatial relationship corresponding to each other. The glue 13 and the first-pillar lame, erfl11) use the first underfill W and the first underfill 14 together. ^ ^ 4 illustrates the first underfill 13 respectively, namely the second, the third and the third. The implementation of the first underfill 14

557555 V. Description of the invention (7) The first underfill 13 is an insulating rubber material containing a high amount of epoxy resin (Eρ〇χγ Resin), which has a high Young's modulus and a high rigidity (Regidity). Large mechanical strength (Mechanical strength). As shown in FIG. 2, the first underfill 13 is pre-applied to the solder bumps 丨 丨 by means of dipping; when the wafer 丨 2 is connected to the substrate i 〇, it is re-welded ( Refl0w) The first underfill 13 will completely cover the solder bumps 11 to form a protective layer to help the solder bumps 丨 丨 enhance the stress resistance of the solder joints and avoid soldering Decomposition of the bumps 丨 丨 affects the electrical quality of the chip 12. The bottom filler 14 of this brother is an insulating rubber material with a large proportion of siiicon Particles. Its Young's modulus is low, which is outstanding for adjusting the difference in thermal expansion coefficient and controlling deformation. This rubber material flows The flexibility (ie, the softness of the glue) is very high, so the preferred method of glue application usually uses top Globing. However, in addition to the rubber materials exemplified above, the first base. The P filler 1 3 and the second bottom filler 1 4 can also use any glue with the same composition and different proportions, or glues with different compositions and ratios, as long as the glue used to cover the solder bumps can provide more Those with strong mechanical support and other parts that can improve the deformation of the material caused by the difference in thermal stress are covered by the scope of the applicable rubber material of the present invention. As shown in FIGS. 3 and 4, the second underfill 丨 4 flows out from the dispensing needle 丨 6 and is applied around the wafer 12 to fill the gap between the wafer J 2 and the substrate i 0. Since the second underfill 丨 4 has better effect on deformation control, the second underfill 1-4 is applied to the wafer 丨 2 the outer edge of the bottom can strengthen the periphery of the chip gap to avoid the outermost joint bonding The part is damaged by stress, this effect

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V. Description of the invention (8) It is particularly significant in large wafers and large-size flip-chip products. The glue of the first underfill 13 and the second underfill 14 can be implemented by using existing process equipment without causing any problems. The cost increases; and the first underfill 13 and the second underfill 14 can be developed according to the different physical characteristics of the rubber material, so the expected effect of the underfill technology can be brought into full play. The rate has increased significantly. ^ The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the substantive technical content. The substantive technical content of the present invention is defined in the following patent applications. ^ Can be completed by others—1i · Or method, if it is the same as defined in the scope of patent application below: =: 二 ΐ: or 疋, equivalent changes will be considered to be covered in this application

557555 Brief description of the drawings [Simplified description of the drawings]: The following is a more detailed description of the features and effects of the present invention with preferred specific examples and accompanying drawings: Figure 1 is a three-dimensional fracture of a flip-chip semiconductor package of the present invention Figure 2 is a schematic diagram of the operation of the flip-chip semiconductor package of the present invention. Figure 3 is a schematic top view of the semiconductor package of the present invention performing a second underfill operation. Figure 4 is FIG. 3 is a schematic cross-sectional view of the AA section line; and FIG. 5 is a schematic cross-sectional view of a conventional US Pat. No. 5, 2 37, 130 semiconductor package. [Description of component symbols]: 1,2 semiconductor packages 10, 20 substrate 100 upper surface of substrate 101 lower surface of substrate 102 conductive traces 1 04, 2 04 substrate pads 12, 22 wafer 121 non-active surface of wafer 13 first underfill Adhesive 15 Solder ball 21 Conductive adhesive layer 103 Solder resist layer 11 Solder bump (solder bump) 120 Wafer surface 122, 222 Wafer pad 14 Second underfill 16 Dispensing needle

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Claims (1)

557555 1. A flip-chip semiconductor package comprising: a relatively low-wafer wafer carrier having an upper surface and a surface; and a plurality of solder bumps electrically connected to at least one wafer wafer carrier On the bottom, a bottom filler is placed between the wafer and the wafer carrier to cover the solder bump; Μ 夕 = t bottom fill, used to fill the bottom of the wafer and the wafer carrier tooth brother The Young's modulus (Young, s Module) of the glue is lower than the Young's modulus of the first bottom glue; and 2 most solder balls for the chip to be electrically connected to the outside. For example, the flip-chip semiconductor package of item i in the scope of patent application: The wafer carrier is a printed circuit board selected from single-layer, double-layer and multi-layer. Piece, the first underfill is an insulating glue. 4. If f is a flip-chip semiconductor package according to item 1 of the patent, wherein the first underfill has high mechanical strength and strength, and the fluidity of the glue is low. 5 · As for the flip-chip semiconductor package in the scope of the patent application, the T-bottom filler has a high content of epoxy resin (EpOx, Resin 6). A crystalline semiconductor package, wherein the first underfill is firstly coated with a wafer before the wafer is connected to the wafer carrier. 16902.ptd 557555 6. Scope of patent application Dipping (D i pp i ng) The first underfill is coated on the solder bump. 7. The flip-chip semiconductor package according to item 1 of the application, wherein the second underfill is an insulating adhesive. 8. For example, the flip-chip semiconductor package according to item 1 of the patent application scope, wherein the second underfill contains a high amount of silicon particles (Si 1 icon Par t i c 1 e s), and the adhesive material has high fluidity. 9. The flip-chip semiconductor package according to item 1 of the patent application scope, wherein the second bottom-filling system is disposed on the outer edge of the bottom of the wafer by a top-glop method. 16902.ptd Page 15