TWI644409B - 封裝結構及其製造方法 - Google Patents
封裝結構及其製造方法 Download PDFInfo
- Publication number
- TWI644409B TWI644409B TW106132993A TW106132993A TWI644409B TW I644409 B TWI644409 B TW I644409B TW 106132993 A TW106132993 A TW 106132993A TW 106132993 A TW106132993 A TW 106132993A TW I644409 B TWI644409 B TW I644409B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- protective coating
- metal bump
- pad
- solder
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 48
- 229910000679 solder Inorganic materials 0.000 claims abstract description 42
- 239000011253 protective coating Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 238000004806 packaging method and process Methods 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims abstract description 8
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 88
- 238000002161 passivation Methods 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 19
- 230000008569 process Effects 0.000 claims description 12
- 230000004907 flux Effects 0.000 claims description 8
- 238000005476 soldering Methods 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 230000008020 evaporation Effects 0.000 claims description 2
- 238000001704 evaporation Methods 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000003466 welding Methods 0.000 claims 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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Abstract
一種封裝結構包含:半導體基板;焊墊設置於半導體基板之上;導電層設置該焊墊於之上;保護塗層;以及金屬凸塊設置於導電層之上,且該保護塗層覆蓋金屬凸塊,以避免金屬凸塊的氧化。
Description
本發明是有關於封裝結構及其製造方法。
回流焊接是使用焊膏(粉狀焊料和焊劑的粘性混合物)將一個或多個電氣部件附接到其接觸焊盤的過程,然後整個組件受到受控的熱,以熔化焊料,永久連接接頭。加熱可以通過將組件通過回流爐或紅外線或通過用熱氣鉛焊接各個接頭來實現。
隨著封裝結構的發展,進行了越來越多的回流工藝,從而增加了成本。相關領域莫不費盡心思來謀求解決之道,但長久以來一直未見適用的方式被發展完成。為了滿足減少回流工藝的要求,需要先進的封裝形成方法和結構。
本發明提出一種創新的封裝結構及其製造方法,以解決先前技術的困境。
在本發明的一實施例中,一種封裝結構包含:半導體基板;焊墊設置於半導體基板之上;導電層設置該焊墊
於之上;保護塗層;以及金屬凸塊設置於導電層之上,且該保護塗層覆蓋金屬凸塊,以避免金屬凸塊的氧化。
在本發明的另一實施例中,一種封裝結構的製造方法包含:提供半導體基板;形成焊墊於半導體基板之上;形成導電層於焊墊之上;形成金屬凸塊於導電層之上;以及形成保護塗層於金屬凸塊之上,使得保護塗層覆蓋金屬凸塊,以避免金屬凸塊的氧化。
在本發明的另一實施例中,一種封裝結構的製造方法包含:提供半導體基板;形成焊墊於半導體基板之上;形成鈍化層於焊墊以及半導體基板之上;形成開口於鈍化層中,以部分暴露焊墊的表面;形成導電層連接於焊墊的表面以及鈍化層;形成金屬凸塊於導電層之上;形成焊料層於保護塗層之上且於金屬凸塊之正上方;以及執行迴焊製程,將焊料層形成為焊錫凸塊,並移除保護塗層。
綜上所述,本發明之技術方案與現有技術相比具有明顯的優點和有益效果。以下將以實施方式對上述之說明作詳細的描述,並對本發明之技術方案提供更進一步的解釋。
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附符號之說明如下:
110‧‧‧半導體基板
111‧‧‧第一表面
112‧‧‧第二表面
120‧‧‧焊墊
122‧‧‧表面
130‧‧‧鈍化層
132‧‧‧開口
140‧‧‧導電層
150‧‧‧金屬凸塊
152‧‧‧平坦表面
160‧‧‧保護塗層
170‧‧‧焊料層
172‧‧‧焊料凸塊
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下:
第1~6圖是依照本發明實施例繪示之封裝結構的製造程序。
為了使本發明之敘述更加詳盡與完備,可參照所附之圖式及以下所述各種實施例,圖式中相同之號碼代表相同或相似之元件。另一方面,眾所週知的元件與步驟並未描述於實施例中,以避免對本發明造成不必要的限制。
於實施方式與申請專利範圍中,涉及『電性連接』之描述,其可泛指一元件透過其他元件而間接電氣耦合至另一元件,或是一元件無須透過其他元件而直接電氣連結至另一元件。
於實施方式與申請專利範圍中,除非內文中對於冠詞有所特別限定,否則『一』與『該』可泛指單一個或複數個。
第1~6圖是依照本發明實施例繪示之封裝結構的製造程序。應瞭解到,在本實施例中所提及的步驟,除特別敘明其順序者外,均可依實際需要調整其前後順序,甚至可同時或部分同時執行。
如第1圖所示,提供了半導體基板110。半導體基板110具有彼此相對的第一表面111和第二表面112。例如,半導體基板110是矽基板或其它合適的半導體基板。製程從半導體基板110的第一表面111開始,其中焊墊120形成在半導體基板110上。
在結構上,焊墊120設置在半導體基板110上。焊墊120電連接到半導體基板110。例如,在半導體基板110的表面上或上方形成焊墊120。焊墊120用作在半導體基板
110的表面中提供的焊料和電互連之間的界面。
在半導體基板110的表面上形成焊墊120(例如,接合焊墊或接觸焊墊)之後,通過沉積鈍化層130在焊墊120的表面上方,使焊墊120被鈍化和電絕緣。在鈍化層130沉積和圖案化之後,在鈍化層130中形成開口132並與焊墊120對齊。
在結構上,鈍化層130設置在焊墊120和半導體基板110上。換句話說,焊墊120設置在鈍化層130中,並且鈍化層130被凹入以形成用於部分暴露的焊口120的表面122的開口132。在一些實施例中,鈍化層130係由二氧化矽形成,使得該結構可以具有高的成形精度和窄間距能力。在各種實施例中,鈍化層130係由聚酰亞胺形成。
參考第2圖,導電層140形成在焊墊120和鈍化層130上,並且導電層140電連接到焊墊120。特別地,導電層140連接於焊墊120的表面122和鈍化層130。在一些實施例中,導電層140是凸塊下金屬層。例如,凸塊下金屬層(該層可以是金屬的複合層,如鉻,隨後是銅,隨後是金,以促進改善的附著力(與鉻)並形成擴散阻擋層或防止氧化(銅上的金))形成在鈍化層130上並在鈍化層130中形成的開口132內。
參考第3圖,金屬凸塊150形成在導電層140上,並且導電層140的冗餘部分從鈍化層130的表面移除。在第3圖中,金屬凸塊150設置在導電層140上,導電層140電連接到金屬凸塊150。在一些實施例中,金屬凸塊150係
由銅形成。
在結構上,金屬凸塊具有非圓形狀(例如,矩形形狀),並且金屬凸塊150具有背離半導體基板110的平坦表面152(例如,頂表面)。以這種方式,如圖5所示,金屬凸塊150的平坦表面152可以用於承載焊料層170。
參照第4圖,形成保護塗層160。在結構中,金屬凸塊150被保護塗層160覆蓋,以避免金屬凸塊150的氧化。應該注意的是,如果保護塗層160被省略,則在金屬凸塊150的表面處暴露於密封前的空氣,容易發生金屬氧化。
在一些實施例中,保護塗層160是有機保焊劑層。有機保焊劑層具有成本低,界面平整,接合強度高,污染少,易製造的優點。
參考第5圖,焊料層170設置在保護塗層160上,並且焊料層170直接位在金屬凸塊150的正上方。在一些實施例中,焊料層170係由錫形成。
在一些對照實驗中,保護塗層160被省略,焊料層170直接形成在金屬凸塊150上,導致需要附加的迴焊製程(例如,紅外迴焊)。
與上述對照實驗相比,在本實施例中,焊接層170形成在保護塗層160上,在此期間不需要額外的迴焊製程(例如,紅外迴焊)。
參考第6圖,在形成焊料層170之後,對封裝結構進行表面焊接技術。然後,保護塗層160從封裝結構中移除。焊料凸塊172由焊料層170形成,並且焊料凸塊172在
金屬凸塊150處連接。以這種方式,焊料凸塊172可用於與諸如晶片,基板,載體等的其它物體連接。
在表面焊接技術中,執行迴焊製程(例如,SMT迴焊)以將焊料層170形成為焊料凸塊172以及同時移除保護塗層160。在一些實施例中,保護塗層160是有機保焊劑層。迴焊製程後,有機保焊劑層蒸發。此外,有機保焊劑層的蒸發也可以清理封裝結構。
雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
Claims (17)
- 一種封裝結構,包含:一半導體基板;一焊墊,設置於該半導體基板之上;一導電層,設置該焊墊於之上;一保護塗層,其中該保護塗層為可蒸發移除的塗層;一金屬凸塊,設置於該導電層之上,且該保護塗層覆蓋該金屬凸塊,以避免該金屬凸塊的氧化;以及一焊料層,設置於該保護塗層之上,且位於該金屬凸塊之正上方。
- 如請求項1所述之封裝結構,更包含:一鈍化層,設置於該半導體基板之上,其中該焊墊設置於該鈍化層之中,該鈍化層具有一開口以部分暴露該焊墊的一表面,且該導電層連接於該焊墊的該表面以及該鈍化層。
- 如請求項1所述之封裝結構,其中該金屬凸塊具有一平坦表面,背離該半導體基板。
- 如請求項1所述之封裝結構,其中該金屬凸塊具有一非圓形狀。
- 如請求項1所述之封裝結構,其中該金屬凸塊係由銅形成。
- 如請求項1所述之封裝結構,其中該導電層為一凸塊下金屬層。
- 如請求項1所述之封裝結構,其中該保護塗層為一有機保焊劑層。
- 如請求項1所述之封裝結構,其中該焊料層係由錫形成。
- 如請求項1所述之封裝結構,其中該鈍化層係由二氧化矽形成。
- 一種封裝結構的製造方法,該製造方法包含:提供一半導體基板;形成一焊墊於該半導體基板之上;形成一導電層於該焊墊之上;形成一金屬凸塊於該導電層之上;形成一保護塗層於該金屬凸塊之上,使得該保護塗層覆蓋該金屬凸塊,以避免該金屬凸塊的氧化;形成一焊料層於該保護塗層之上且於該金屬凸塊之正上方;以及對該封裝結構執行一表面焊接技術,以移除該保護塗層。
- 如請求項10所述之製造方法,更包含:形成一鈍化層於該焊墊以及該半導體基板之上;以及形成一開口於該鈍化層中,以部分暴露該焊墊的一表面。
- 如請求項11所述之製造方法,其中形成該導電層於該焊墊之上,包含:形成該導電層連接於該焊墊的該表面以及該鈍化層。
- 如請求項10所述之製造方法,其中該保護塗層為一有機保焊劑層,在該表面焊接技術執行以後,該有機保焊劑層被蒸發。
- 一種封裝結構的製造方法,該製造方法包含:提供一半導體基板;形成一焊墊於該半導體基板之上;形成一鈍化層於該焊墊以及該半導體基板之上;形成一開口於該鈍化層中,以部分暴露該焊墊的一表面;形成一導電層連接於該焊墊的該表面以及該鈍化層;形成一金屬凸塊於該導電層之上;形成一保護塗層於該金屬凸塊之上,使得該保護塗層覆蓋該金屬凸塊;形成一焊料層於該保護塗層之上且於該金屬凸塊之正上方;以及執行一迴焊製程,將該焊料層形成為一焊錫凸塊,並移除該保護塗層。
- 如請求項14所述之製造方法,其中該保護塗層為一有機保焊劑層。
- 如請求項15所述之製造方法,其中在該迴焊製程執行後,該有機保焊劑層被蒸發。
- 如請求項14所述之製造方法,其中在形成該焊料層於該保護塗層之上且於該金屬凸塊之正上方的過程中,無需額外的迴焊製程。
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US8115285B2 (en) * | 2008-03-14 | 2012-02-14 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof |
US20100327419A1 (en) * | 2009-06-26 | 2010-12-30 | Sriram Muthukumar | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same |
US8431478B2 (en) * | 2011-09-16 | 2013-04-30 | Chipmos Technologies, Inc. | Solder cap bump in semiconductor package and method of manufacturing the same |
US8912651B2 (en) * | 2011-11-30 | 2014-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package (PoP) structure including stud bulbs and method |
US9362197B2 (en) * | 2012-11-02 | 2016-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Molded underfilling for package on package devices |
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US20170179058A1 (en) * | 2015-12-16 | 2017-06-22 | Lite-On Semiconductor Corporation | Bump structure having first portion of copper and second portion of pure tin covering the first portion, and interconnect structure using the same |
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