TWI690947B - 導電物質的布局方法、布局結構及包含其之ｌｅｄ顯示器 - Google Patents

導電物質的布局方法、布局結構及包含其之ｌｅｄ顯示器 Download PDF

Info

Publication number
TWI690947B
TWI690947B TW107143015A TW107143015A TWI690947B TW I690947 B TWI690947 B TW I690947B TW 107143015 A TW107143015 A TW 107143015A TW 107143015 A TW107143015 A TW 107143015A TW I690947 B TWI690947 B TW I690947B
Authority
TW
Taiwan
Prior art keywords
pad
conductive material
pad area
substrate
conductive
Prior art date
Application number
TW107143015A
Other languages
English (en)
Other versions
TW202022896A (zh
Inventor
廖建碩
Original Assignee
台灣愛司帝科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣愛司帝科技股份有限公司 filed Critical 台灣愛司帝科技股份有限公司
Priority to TW107143015A priority Critical patent/TWI690947B/zh
Priority to US16/424,883 priority patent/US20200176311A1/en
Application granted granted Critical
Publication of TWI690947B publication Critical patent/TWI690947B/zh
Publication of TW202022896A publication Critical patent/TW202022896A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H01L33/501—Wavelength conversion elements characterised by the materials, e.g. binder
    • H01L33/502—Wavelength conversion materials
    • H01L33/504—Elements with two or more wavelength conversion materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1141—Manufacturing methods by blanket deposition of the material of the bump connector in liquid form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/81424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Optics & Photonics (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本發明公開一種導電物質的布局方法、布局結構及包含其之顯示器，導電物質的布局方法包括提供一基板，其上表面具有一非焊墊區以及多個焊墊區。形成一導電材料於基板的上表面，以覆蓋非焊墊區以及焊墊區。對導電材料進行加熱而熔融。被熔融的導電材料被劃分成分別停留在多個焊墊區上的多個導電體。

Description

導電物質的布局方法、布局結構及包含其之LED顯示器
本發明涉及一種布局方法及布局結構，特別是涉及一種導電物質的布局方法、導電物質的布局結構及包含其之LED顯示器。
焊料為一種低熔點的合金，通常用於接合金屬零件。舉例來說，在覆晶技術(Flip Chip)中，會先於基板上形成焊球，以便於焊球上再設置晶片。
在現有技術中，焊球的設置方式為利用高壓放電的方式對焊料瞬間局部加熱，使暴露於鋼嘴(Capillary)尖端外的焊料熔融成液態。此時，在表面張力的作用下，熔融的焊料會形成球狀物。鋼嘴隨即將焊料下壓於焊墊上，使焊料產生變形，促進焊料與焊墊的接觸面上的原子擴散，以產生焊點，待焊料冷卻固化後即形成焊球。接著，可再使各個焊球分別與一晶片對準，經壓合接觸、重熔回焊以及填充絕緣膠後即完成晶片封裝。通過焊料的使用，可使基板上的積體電路與晶片電性連接。
然而，現有技術中設置焊球的方法，具有焊球設置數量上的限制，根據鋼嘴的數量決定一次可設置焊球的數量，無法同時且大量地設置焊球。因此，現有技術中設置焊球的方法仍有待改善。
本發明所要解決的技術問題在於，針對現有技術的不足提供一種導電物質的布局方法、導電物質的布局結構及包含其之LED顯示器。
為了解決上述的技術問題，本發明所採用的其中一技術方案是，提供一種導電物質的布局方法，其包括至少下列步驟：提供一基板，其上表面具有一非焊墊區以及多個焊墊區。形成一導電材料於基板的上表面，以覆蓋非焊墊區以及多個焊墊區。對導電材料進行加熱而熔融。被熔融的導電材料被劃分成分別停留在該些焊墊區上的多個導電體。
為了解決上述的技術問題，本發明所採用的另外一技術方案是，提供一種導電物質的布局結構，其包括一基板以及多個導電體。基板上表面具有多個焊墊區。多個導電體分別設置在該些焊墊區上。其中，導電體在熔融狀態時的內聚力，大於導電體在熔融狀態時相對於基板的一非焊墊區的附著力。
為了解決上述的技術問題，本發明所採用的另外再一技術方案是，提供一種LED顯示器，其包括一基板、多個導電體以及多個LED發光元件。基板上表面具有多個焊墊區。多個導電體分別設置在該些焊墊區上。每一該LED發光元件設置在相對應的兩個導電體上。其中，導電體在熔融狀態時的內聚力，大於導電體在熔融狀態時相對於基板的一非焊墊區的附著力。
本發明的其中一有益效果在於，本發明所提供的導電物質的布局方法、導電物質的布局結構及包含其之LED顯示器，其能通過“基板的上表面具有一非焊墊區以及多個焊墊區”、“對該導電材料進行加熱而熔融”以及“被熔融的該導電材料被劃分成分別停留在該些焊墊區上的多個導電體”的技術方案，達到可同時設置多個導電體，簡化製程步驟並縮短製程時間的效果。
為使能更進一步瞭解本發明的特徵及技術內容，請參閱以下有關本發明的詳細說明與圖式，然而所提供的圖式僅用於提供參考與說明，並非用來對本發明加以限制。
Z‧‧‧導電物質的布局結構
10‧‧‧基板
100‧‧‧上表面
11‧‧‧非焊墊區
12‧‧‧焊墊區
20‧‧‧導電材料
21‧‧‧導電體
Y‧‧‧LED顯示器
30‧‧‧LED發光元件
H‧‧‧加熱器
E‧‧‧雷射光供應器
圖1為本發明導電物質的布局方法的流程圖。
圖2為本發明導電物質的布局方法的步驟S100的立體示意圖。
圖3為本發明導電物質的布局方法的步驟S100的側視剖面示意圖。
圖4為本發明導電物質的布局方法的步驟S102的側視剖面示意圖。
圖5為本發明導電物質的布局方法的步驟S104的其中一實施例的側視剖面示意圖。
圖6為本發明導電物質的布局方法的步驟S104的另一實施例的側視剖面示意圖。
圖7為本發明導電物質的布局方法的步驟S106的側視剖面示意圖。
圖8為本發明導電物質的布局方法的步驟S108的側視剖面示意圖。
以下是通過特定的具體實施例來說明本發明所公開有關“導電物質的布局方法、導電物質的布局結構及包含其之LED顯示器”的實施方式，本領域技術人員可由本說明書所公開的內容瞭解本發明的優點與效果。本發明可通過其他不同的具體實施例加以施行或應用，本說明書中的各項細節也可基於不同觀點與應用，在不悖離本發明的構思下進行各種修改與變更。另外，本發明的附圖僅為簡單示意說明，並非依實際尺寸的描繪，事先聲明。以下的實施方式將進一步詳細說明本發明的相關技術內容，但所公開的內容並非用以限制本發明的保護範圍。
應當可以理解的是，雖然本文中可能會使用到“第一”、“第二”、“第三”等術語來描述各種元件或者信號，但這些元件或者信號不應受這些術語的限制。這些術語主要是用以區分一元件與另一元件，或者一信號與另一信號。另外，本文中所使用的術 語“或”，應視實際情況可能包括相關聯的列出項目中的任一個或者多個的組合。
[第一實施例]
參閱圖1至圖3所示，本發明第一實施例提供一種導電物質的布局方法，其至少包括下列幾個步驟：首先，提供一基板10，基板10的上表面100具有一非焊墊區11以及多個焊墊區12(步驟S100)。
基板10可以是矽(Silicon)基板、藍寶石(Sapphire)基板或者任何材料的基板。
非焊墊區11的材料可以與基板10的材料相同或不同，非焊墊區11可以是一連續式的非焊墊區或一非連續式的非焊墊區。於本實施例中，非焊墊區11的材料與基板10的材料相同，且非焊墊區11為連續式的非焊墊區，但不以此為限。於其他實施例，非焊墊區11亦可由多個非連續式的非焊墊區組合而成。於本實施例中，非焊墊區11可以是一防焊層(Solder Mask，S/M)，防焊層為覆蓋於基板10之上的一絕緣層。舉例來說，防焊層的主要材料為樹脂，可達到保護銅箔線路以及避免零件誤焊的效果，另具有防潮、絕緣、防焊、耐高溫及美觀的需求。然而，本發明並不以上述所舉的例子為限。
焊墊區12的材料可以是金屬。舉例來說，焊墊區12的材料可以是鋁、金或其它金屬及合金。如圖3所示，多個焊墊區12彼此獨立不相連，任二相鄰的焊墊區12以非焊墊區11區隔開。焊墊區12與基板10的上表面100齊平。於其他實施例中，焊墊區12亦可高於或低於基板10的上表面100。
接著，請參照圖1和圖4所示，形成一導電材料20於基板10的上表面100，以覆蓋非焊墊區11以及多個焊墊區12(步驟S102)。具體來說，導電材料20可以是錫、鉛、銀、鉍、銅、鐵、 金、鉑、銦、鎳或包括上述至少二者的合金。由於導電材料20和焊墊區12的材料都為金屬，故導電材料20在焊墊區12的附著力大於導電材料20在非焊墊區11的附著力。
具體而言，步驟S102進一步包括：通過印刷或者塗佈等方式，形成導電材料20於基板10的上表面100，以覆蓋多個焊墊區12。於其他實施例中，於基板10的上表面100形成導電材料20的步驟，可進行一次或多次的印刷或是一次或多次的塗佈來完成。
於本實施例中，導電材料20不僅覆蓋多個焊墊區12，還覆蓋非焊墊區11。也就是說，導電材料20完全覆蓋基板10的整個上表面100。於其他實施例中，導電材料20可選擇性覆蓋多個焊墊區12的全部或部分，導電材料20可選擇性覆蓋非焊墊區11的全部或部分。
請參照圖1、圖5和圖6所示，對該導電材料20進行加熱而熔融(步驟S104)。具體來說，步驟S104進一步包括：通過加熱器H對該導電材料20進行加熱而熔融(如圖5所示)。或者，通過雷射光供應器E對該導電材料20進行加熱而熔融(如圖6所示)。也就是說，使導電材料20加熱而呈熔融的方式可以是以加熱器加熱或者雷射光掃射的方式，但不限於上述。
一般來說，金屬相較於非金屬具有較大的表面能(Surface Energy)。故當導電材料20被加熱呈熔融狀態而可流動時，會傾向減少金屬裸露的表面積，以便降低金屬裸露所產生的表面能。
於本實施例中，導電材料20和多個焊墊區12皆為金屬材料，非焊墊區11的材料為非金屬。故在為了降低表面能的前提下，熔融狀態的導電材料20會傾向內縮形成表面積較小的球狀物(內聚力)，以降低導電材料20本身的表面積。並且，熔融狀態的導電材料20會傾向覆蓋焊墊區12並傾向裸露出非焊墊區11，以降低金屬裸露所產生的表面能。
簡言之，在導電材料20的內聚力、導電材料20與非焊墊區 11的附著力以及導電材料20與焊墊區12的附著力的共同作用下，熔融狀態的導電材料20會傾向由非焊墊區11移動至焊墊區12，使導電材料20完全覆蓋焊墊區12並裸露出非焊墊區11，並於焊墊區12上方形成球狀物。
然而，本發明並不以上述說明為限，當非焊墊區11的材料和該些焊墊區12的材料不同時，只要熔融狀態的導電材料20的內聚力，大於熔融狀態的導電材料20在非焊墊區11上的附著力，即可達到使熔融狀態的導電材料20由非焊墊區11移動至焊墊區12的效果。
在本實施例中，任二相鄰的焊墊區12皆被非焊墊區11所隔開。因此，當導電材料20被加熱呈熔融狀態後，會根據非焊墊區11以及多個焊墊區12的布局設置，自發地被劃分為多個分別設置於多個焊墊區12上方的導電體21。
請參閱圖5至圖7所示，當導電材料20在熔融狀態時，非焊墊區11上方的導電材料20會因內聚力的作用，而往鄰近的焊墊區12的方向移動，使得非焊墊區11上導電材料20的厚度逐漸變薄(如圖5、圖6所示)。最後，非焊墊區11上方的導電材料20會全部移動至鄰近的焊墊區12上方，而裸露出非焊墊區11，且各個焊墊區12上方的導電材料20會形成一球狀物。當導電材料20冷卻固化後，便會於每一焊墊區12上方分別形成一導電體21(如圖7所示)。
請參照圖1和圖7所示，被熔融的該導電材料20被劃分成分別停留在該些焊墊區12上的多個導電體21(步驟S106)。據此，根據上述導電物質的布局方法，可完成如圖7所示的導電物質的布局結構Z。於本實施例中，導電體21可為焊球(Solder Ball)。
值得注意的是，焊球可以是錫球，並可根據欲接合的構件選用不同的導電材料20。例如，錫球一般可被分為五大類：普通焊錫球(錫的原子百分比含量為2至100、熔點範圍為180℃至 316℃)、低溫焊錫球(含鉍或銦類、熔點範圍為95℃至135℃)、高溫焊錫球(熔點範圍為186℃至309℃)、耐疲勞高純度焊錫球(熔點範圍為178℃和183℃)和無鉛銲錫球(成分中鉛的原子百分比含量小於0.1)。
再請參照圖1和圖8所示，設置多個LED發光元件30於多個導電體21上，每一LED發光元件30設置在相對應的兩個該導電體21上(步驟S108)。具體來說，多個LED發光元件30可通過覆晶技術設置於多個導電體21上，以完成圖7所示的LED顯示器Y。然而，本發明並不以此為限。
[實施例的有益效果]
本發明的其中一有益效果在於，本發明所提供的導電物質的布局方法、布局結構及包含其之LED顯示器，其能通過“非焊墊區以及多個焊墊區的設置”、“對該導電材料進行加熱而熔融”以及“使導電材料被劃分成分別停留在該些焊墊區上的多個導電體”的技術方案，達到可同時設置多個導電體，簡化製程步驟並縮短製程時間的效果。
更進一步來說，通過“導電材料因其內聚力大於其相對於該基板的一非焊墊區的附著力，而從該非焊墊區移動到該焊墊區”或是“該導電體在熔融狀態時的內聚力，大於該導電體在熔融狀態時相對於該基板的一非焊墊區的附著力”的技術方案，可使熔融狀態的導電材料自發地被劃分成分別停留在多個焊墊區上，並形成多個導電體。克服以往一次僅能設置一個導電體，以及需移動鋼嘴至另一焊墊區上方，才可設置另一導電體的製程缺陷。
以上所公開的內容僅為本發明的優選可行實施例，並非因此侷限本發明的申請專利範圍，所以凡是運用本發明說明書及圖式內容所做的等效技術變化，均包含於本發明的申請專利範圍內。
指定代表圖為流程圖，故無符號簡單說明

Claims (10)

  1. 一種導電物質的布局方法，其包括：提供一基板，其上表面具有一非焊墊區以及多個焊墊區；形成一導電材料於該基板的上表面，以覆蓋該非焊墊區以及該些焊墊區；對該導電材料進行加熱而熔融；以及被熔融的該導電材料被劃分成分別停留在該些焊墊區上的多個導電體。
  2. 如請求項1所述的導電物質的布局方法，其中，該非焊墊區為一防焊層。
  3. 如請求項1所述的導電物質的布局方法，其中，被熔融的該導電材料因其相對於該些焊墊區的附著力大於其相對於該非焊墊區的附著力，而從該非焊墊區移動到該焊墊區。
  4. 如請求項1所述的導電物質的布局方法，其中，該導電材料是透過印刷或者塗佈方式以形成於該基板的上表面。
  5. 如請求項1所述的導電物質的布局方法，其中，該導電材料是透過加熱器加溫或者雷射光掃射方式而熔融。
  6. 一種導電物質的布局結構，其包括：一基板，其上表面具有一非焊墊區以及多個焊墊區；以及多個導電體，其分別設置在該些焊墊區上；其中，該導電體在熔融狀態時相對於該些焊墊區的附著力，大於該導電體在熔融狀態時相對於該非焊墊區的附著力。
  7. 如請求項6所述的導電物質的布局結構，其中，該導電體為焊球。
  8. 如請求項6所述的導電物質的布局結構，其中，該非焊墊區為一防焊層。
  9. 一種LED顯示器，其包括： 一基板，其上表面具有一非焊墊區以及多個焊墊區；多個導電體，其分別設置在該些焊墊區上；以及多個LED發光元件，每一該LED發光元件設置在相對應的兩個該導電體上；其中，該導電體在熔融狀態時相對於該些焊墊區的附著力，大於該導電體在熔融狀態時的相對於該非焊墊區的附著力。
  10. 如請求項9所述的LED顯示器，其中，該非焊墊區為一防焊層。
TW107143015A 2018-11-30 2018-11-30 導電物質的布局方法、布局結構及包含其之ｌｅｄ顯示器 TWI690947B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW107143015A TWI690947B (zh) 2018-11-30 2018-11-30 導電物質的布局方法、布局結構及包含其之ｌｅｄ顯示器
US16/424,883 US20200176311A1 (en) 2018-11-30 2019-05-29 Arrangement method and arrangement structure of conductive material, and led display thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW107143015A TWI690947B (zh) 2018-11-30 2018-11-30 導電物質的布局方法、布局結構及包含其之ｌｅｄ顯示器

Publications (2)

Publication Number Publication Date
TWI690947B true TWI690947B (zh) 2020-04-11
TW202022896A TW202022896A (zh) 2020-06-16

Family

ID=70850251

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107143015A TWI690947B (zh) 2018-11-30 2018-11-30 導電物質的布局方法、布局結構及包含其之ｌｅｄ顯示器

Country Status (2)

Country Link
US (1) US20200176311A1 (zh)
TW (1) TWI690947B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI760230B (zh) * 2020-06-09 2022-04-01 台灣愛司帝科技股份有限公司 晶片檢測方法、晶片檢測結構以及晶片承載結構

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004050762A1 (ja) * 2002-11-29 2004-06-17 Sekisui Chemical Co., Ltd. 加熱消滅性材料、これを用いた転写シートおよびパターン形成方法
CN1848394A (zh) * 2005-04-13 2006-10-18 邹明德 预置式导电薄膜构装及其成型方法
CN102610597A (zh) * 2011-01-18 2012-07-25 矽品精密工业股份有限公司 具有发光元件的封装件及其制法
TW201331957A (zh) * 2011-12-13 2013-08-01 Dow Corning 組成物及由其所形成之導體
TW201543502A (zh) * 2014-03-19 2015-11-16 Dexerials Corp 異向性導電接著劑
TW201738902A (zh) * 2016-04-29 2017-11-01 南茂科技股份有限公司 焊球、其製造方法以及半導體元件
JP2018140427A (ja) * 2017-02-28 2018-09-13 千住金属工業株式会社 はんだ材料、はんだペースト、フォームはんだ及びはんだ継手
TW201840724A (zh) * 2017-03-30 2018-11-16 日商田村製作所股份有限公司 預敷層用焊料組合物及印刷配線基板之製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8424748B2 (en) * 2009-12-21 2013-04-23 Intel Corporation Solder in cavity interconnection technology
US8492262B2 (en) * 2010-02-16 2013-07-23 International Business Machines Corporation Direct IMS (injection molded solder) without a mask for forming solder bumps on substrates
US8936967B2 (en) * 2011-03-23 2015-01-20 Intel Corporation Solder in cavity interconnection structures
GB2520952A (en) * 2013-12-04 2015-06-10 Ibm Flip-chip electronic device with carrier having heat dissipation elements free of solder mask
US9961770B2 (en) * 2014-07-22 2018-05-01 Cree, Inc. Solder pads, methods, and systems for circuitry components
KR20160032524A (ko) * 2014-09-16 2016-03-24 삼성전기주식회사 인쇄회로기판 및 그 제조방법
JP6559743B2 (ja) * 2017-08-08 2019-08-14 太陽誘電株式会社 半導体モジュール

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004050762A1 (ja) * 2002-11-29 2004-06-17 Sekisui Chemical Co., Ltd. 加熱消滅性材料、これを用いた転写シートおよびパターン形成方法
CN1708555A (zh) * 2002-11-29 2005-12-14 积水化学工业株式会社 热衰变材料、使用其的转印薄片及形成图案的方法
CN1848394A (zh) * 2005-04-13 2006-10-18 邹明德 预置式导电薄膜构装及其成型方法
CN102610597A (zh) * 2011-01-18 2012-07-25 矽品精密工业股份有限公司 具有发光元件的封装件及其制法
TW201331957A (zh) * 2011-12-13 2013-08-01 Dow Corning 組成物及由其所形成之導體
TW201543502A (zh) * 2014-03-19 2015-11-16 Dexerials Corp 異向性導電接著劑
TW201738902A (zh) * 2016-04-29 2017-11-01 南茂科技股份有限公司 焊球、其製造方法以及半導體元件
JP2018140427A (ja) * 2017-02-28 2018-09-13 千住金属工業株式会社 はんだ材料、はんだペースト、フォームはんだ及びはんだ継手
TW201840724A (zh) * 2017-03-30 2018-11-16 日商田村製作所股份有限公司 預敷層用焊料組合物及印刷配線基板之製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI760230B (zh) * 2020-06-09 2022-04-01 台灣愛司帝科技股份有限公司 晶片檢測方法、晶片檢測結構以及晶片承載結構

Also Published As

Publication number Publication date
TW202022896A (zh) 2020-06-16
US20200176311A1 (en) 2020-06-04

Similar Documents

Publication Publication Date Title
KR100718172B1 (ko) 전자 디바이스 및 전자 디바이스 밀봉 방법 및 전자디바이스 접속 방법
JPH065760A (ja) 表面実装型半導体装置用パッケージリード
TW499826B (en) Multilayer flexible wiring board
JP2000031204A (ja) 半導体パッケージの製造方法
JP2000114301A (ja) 半田バンプの形成方法および半田バンプの実装方法
JPH077038A (ja) 電子パッケージ
CN100534263C (zh) 电路板导电凸块结构及其制法
US9502337B2 (en) Flip-chip on leadframe semiconductor packaging structure and fabrication method thereof
TWI690947B (zh) 導電物質的布局方法、布局結構及包含其之ｌｅｄ顯示器
KR20130060361A (ko) 회로 장치 및 그 제조 방법
KR100715410B1 (ko) 혼성 집적 회로
US8174113B2 (en) Methods of fabricating robust integrated heat spreader designs and structures formed thereby
TW533556B (en) Manufacturing process of bump
JP2008198916A (ja) 半導体装置及びその製造方法
JPS6245138A (ja) 電子部品装置の製法
US20080212301A1 (en) Electronic part mounting board and method of mounting the same
TW475245B (en) Semiconductor device, external connecting terminal body structure and method for producing semiconductor devices
JPH0666355B2 (ja) 半導体装置の実装体およびその実装方法
TWI608775B (zh) 焊墊及焊墊製作方法
TWI813341B (zh) 覆晶接合方法
JPH09148693A (ja) フリップチップ実装用基板及びその製造方法
JPH1140716A (ja) 半導体装置およびその製造方法
JP2004228261A (ja) プリント回路板
JP3468876B2 (ja) プリント配線板およびその製造方法
TW478121B (en) Soft packaging structure and method for making the same

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees