CN1848394A - 预置式导电薄膜构装及其成型方法 - Google Patents

预置式导电薄膜构装及其成型方法 Download PDF

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CN1848394A
CN1848394A CNA2005100635640A CN200510063564A CN1848394A CN 1848394 A CN1848394 A CN 1848394A CN A2005100635640 A CNA2005100635640 A CN A2005100635640A CN 200510063564 A CN200510063564 A CN 200510063564A CN 1848394 A CN1848394 A CN 1848394A
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conductive film
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邹明德
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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Abstract

本发明预置式导电薄膜是由导电粒子与高分子薄膜所组合构成,其中导电粒子是以数组或既定的位置固定在高分子薄膜上或压入薄膜中,于进行构装作业时,是将本预置式导电薄膜置放于二种或二种以上的材质所构成的两个电极中间,并依照既定的压力、温度、加热时间等条件让其中的高分子材接着、凝固,以及让导电粒子在两电极间接触,并使此两电极结合,以达到电性导通的目的。

Description

预置式导电薄膜构装及其成型方法
技术领域
本发明涉及电子构装技术,旨在提供一种施作容易,而且有效提升电子构装的良率及产能的电子构装技术。
背景技术
电子产品追求高速度、外型轻、薄、短、小,其除在芯片制作技术上力求突破外,将芯片封装体积缩小及构装方式简化也是主要关键,电子构装随着时代的进化也由导线架(QFP)、球栅数组技术(BGA)、覆晶技术(FC)、晶方尺度构装(CSP)、直接粘着技术(DCA)等进化。晶圆尺寸越来越小,频率也随着增加,在次世代的电子构装诸如射频组件、数字光学与感测组件的整合构装。
这些新兴的技术需要新思维、新构想,此新构装技术诸如系统构装(SIP)、二维三维组件堆栈(2D、3D)等,使用独立的主动和被动组件,藉由组件、芯片、基版的封装或堆栈来造成较高的封装密度,此阶段已进入奈米时代,电子组件的电极网关宽度已可小于100奈米并朝向小于65奈米的方向发展,而这些奈米组件其芯片封装的焊垫间距也由0.5毫米降到0.1毫米,并且朝向0.025毫米发展,以现有的电子构装技术很难达到如此细小间距的要求。
如图1至图4所示,为业界所普遍习用以焊锡锡球进行电子构装的加工流程,其中是先如图1所示在芯片10与基板20的接面上分别预设有焊锡用的锡球11以及焊垫21,于施作时必须将芯片10上的锡球11对准基板20上的焊垫21放下,接着如图2所示进行回焊让锡球11和焊垫21均产生热熔而接合在一起,最后如图3及图4所示在芯片10与基板20两边填充底胶30,经由毛细作用将芯片10和基板20间的微小间隙完全填满胶材,最后在使以烘烤使胶材固化定型,以期增加锡球11接点抵抗热应力的能力。
另外,如图5至图8所示,为业界所习用另一种利用异方性导电胶膜(ACF)进行电子构装的加工流程,其中是先如图5所示将由导电粒子41与高分子材42(树脂)所构成的异方性导电胶膜40披覆在一承载体50上,以便透过承载体50将异方性导电胶膜40覆盖在基板20的线路的电极或焊垫22上(如图6所示),再如图7所示,将芯片10的焊垫12对准基板20线路的电极或焊垫22放置在异方性导电胶膜40上方,并且在施以热压烘烤之后让高分子材42流动,如图8所示使导电粒子41与焊垫12及基板20的线路的电极或焊垫22接触从而达到电性导通的作用。
由于,前述异方性导电胶膜(ACF)进行电子构装因为不需要另外再填充底胶,因此应该较覆晶接合构装方法更广为被业界所使用;然而,习用的异方性导电将膜由于是直接将既定比例的导电粒子分布与高分子材混合再制成薄膜,或是将导电粒子洒在高分子材薄膜上,因此其导电粒子的数量不容易控制,反而容易造成短路或断路的现象。
发明内容
有鉴于此,本发明即将导电粒子是以既定的位置固定在高分子薄膜上或压入薄膜中,以构成所谓的预置式导电薄膜,在进行构装作业时,是直接将本预置式导电薄膜置放于二种或二种以上的材质所构成的两个电极中间,并依照既定的压力、温度、加热时间等条件让其中的高分子材接着、凝固,以及让导电粒子在两电极间略为变形,并使此两电极结合,以达到电性导通的目的。
再者,本发明当中的高分子材是以液态预先披覆在一承载体上有既定的厚度,并待高分子材凝固后将结合有高分子材的承载体卷收成为圆卷状,以便在后续放置导电粒子的作业当中可以将此圆卷状的高分子材及承载体拖曳进行加工;至于,导电粒子可以利用冲压下料的作业方式自金属板上被冲压到高分子材上的既定位置,或者是经由既定的信道移植到高分子材上的既定位置,或者,高分子材是以液态预先披覆在一承载体上有既定的厚度,当高分子材未凝固时,即进行将导电粒子以既定的位置固定在高分子薄膜上或压入薄膜中的制程。
附图说明
图1至图4为习用覆晶接合构装的加工步骤示意图;
图5至图8为习用异方性导电胶膜构装的加工步骤示意图;
图9为本发明的构装流程图;
图10至13图为本发明的构装加工步骤示意图;
图14为本发明的预置式导电薄膜制造流程图;
图15为本发明中高粉分子材与承载体的结合示意图;
图16为本发明中用以放置导电粒子的上、下冲孔模具结构示意图;
图17为本发明中上、下冲孔模具的动作示意图;
图18为本发明中用以放置导电粒子的冲料机结构示意图;
图19为本发明的另一预置式导电薄膜结构示意图。
【图号说明】
10——芯片
11——锡球
12——焊垫
20——基板
21——焊垫
22——线路的电极或焊垫
30——底胶
40——异方性导电胶膜
41——导电粒子
42——高分子材
50——承载体
60——预置式导电薄膜
61——导电粒子
62——高分子材
63——金属板
64——不织布
71——上冲孔模具
72——下冲孔模具
80——冲料机
81——信道
具体实施方式
为能使贵审查员清楚本发明的组成,以及实施方式,兹配合图式
说明如下:
本发明「预置式导电薄膜构装及其成型方法」,其进行电子构装的流程如图9至图13所示,是将预置式导电薄膜60的承载体50撕除,并且置放于二种或二种以上的材质所构成的两个电极中间(如图12所示芯片10的焊垫12与基板20的线路的电极或焊垫22中间),并依照既定的压力、温度、加热时间等条件让其中的高分子材接着、凝固,如图13所示,以及让导电粒子在两电极间接触,并使此两电极结合以达到电性导通的目的。
其中,预置式导电薄膜60是将导电粒子61是以既定的位置固定在高分子薄膜62上或压入薄膜中所构成,并且如图10及图11所示,可将此预置式导电薄膜60预先披覆在一承载体50上,以在施作时,可方便将预置式导电薄膜60移植到两个电极的中间。
至于,整体预置式导电薄膜60的制造方法如图14所示,是先将高分子材与承载体结合形成半成品,再将导电粒子(或是金属导体)置入半成品的既定位置即构成所谓的预置式导电薄膜;在具体实施时,如图15所示,其承载体50是可以为呈圆卷状的PET、PVC、PE带体,至于高分子材62则是为液态状的SBR、Acrylate、Epoxy-PI、Epoxy、PAI、PEI、PI、PU,在进行半成品加工作业时,即将液态的高分子材62预先披覆在承载体50上有既定的厚度,并待高分子材62凝固后将结合有高分子材的承载体卷收成为圆卷状,以便在后续放置导电粒子的作业当中可以将此圆卷状的高分子材及承载体拖曳进行加工;当然,该预置式导电薄膜60亦可由不织布64含浸液态高分子材料,再以烘干成型,如图19所示,其不织布材料可以为PET纤维、木质纤维、植物纤维、玻璃纤维、陶瓷纤维或尼龙纤维,再将导电粒子61(或是金属导体)置入既定位置即构成所谓的预置式导电薄膜。
且该高分子材中可添加绝缘材,例如:添加无机材料、陶瓷材料或高分子材料所制的粉末,使该绝缘材于该高分子材中可提供热传导的介质,且藉由该绝缘材不仅可增加高分子材的厚度,以及可构成各导电粒子间的绝缘介质,使各导电粒子不会互相接触而短路。
另外,导电粒子可以如图16所示,利用冲压下料的作业方式置入在高分子材62中,此时导电粒子是来自一放置在上、下冲孔模具71、72中间的金属板63,而其由承载体50以及高分子材62所结合的半成品即放置在下冲孔模具72的下方,当上、下冲孔模具71、72进行冲孔下料动作时,如图17所示,导电粒子61即自金属板63上被冲压到高分子材62上的既定位置,即完成本预置式导电薄膜60的制作。
或者如图18所示,可利预先将粉粒状的导电粒子61(例如石墨、金、银、铜、镍、锌、铟、铋、铅、锡,及其合金粒子)预先放置在一冲料机80的既定信道81当中,再经由高压气体的作用下,各导电粒子61即经由既定的信道81移植到高分子材62上的既定位置,而完成本预置式导电薄膜的制作。
值得一提的是,本发明的预置式导电薄膜构装不但施作容易,而且有效提升电子构装的良率及产能;尤其,本发明当中的预置式导电薄膜,因为高分子材的厚度与导电粒子的直径大小不同,而且导电粒子的预置位置是可随实际线路的电极或焊垫布设而变动,而可以有非常广泛的应用,并且均能够有优异可靠的粘结性以及电性导通效果。
如上所述,本发明提供一种较佳可行的电子构装方法,于是,依法提呈发明专利的申请;然而,以上的实施说明及图式所示,是本发明较佳实施例之一,并非以此局限本发明,是以,举凡与本发明的构造、装置、特征等近似、雷同,均应属本发明的创作目的及申请专利范围之内。

Claims (18)

1、一种预置式导电薄膜构装方法,其特征是将预置式导电薄膜置放于二种或二种以上的材质所构成的两个电极中间,并依照既定的压力、温度、加热时间条件让其中的高分子材接着、凝固,以及让导电粒子在两电极间接触。
2、如权利要求1所述的预置式导电薄膜构装方法,其中,该预置式导电薄膜是将各导电粒子是以既定的位置固定在由高分子材构成的薄膜上或压入薄膜中。
3、如权利要求1所述的预置式导电薄膜构装方法,其中,该预置式导电薄膜是放置在芯片与基板的线路的电极或焊垫中间;或是放置在芯片的焊垫与基板的线路的电极或焊垫中间。
4、如权利要求1所述的预置式导电薄膜构装方法,其中,该预置式导电薄膜亦可由不织布含浸液态高分子材料,再以烘干成型后,并将各导电粒子是以既定的位置固定在由不织布构成的薄膜上或压入薄膜中。
5、如权利要求4所述的预置式导电薄膜构装方法,其中,该不织布材料为PET纤维、木质纤维、植物纤维、玻璃纤维、陶瓷纤维或尼龙纤维。
6、一种预置式导电薄膜,其特征是在一由高分子材所构成的薄膜上的既定位置固设有导电粒子。
7、如权利要求6所述的预置式导电薄膜,其中,各导电粒子是设在薄膜上或薄膜中。
8、如权利要求6所述的预置式导电薄膜,其中,该高分子材中可添加绝缘材。
9、如权利要求8所述的预置式导电薄膜,其中,该绝缘材可以为无机材料、陶瓷材料或高分子材料所制的粉末。
10、如权利要求6所述的预置式导电薄膜,其中,该导电粒子是可以为石墨、金、银、铜、镍、锌、铟、铋、铅、锡,或其合金粒子。
11、如权利要求6所述的预置式导电薄膜,其中,该高分子材是可以为SBR、Acrylate、Epoxy-PI、Epoxy、PAI、PEI、PI、PU。
12、一种预置式导电薄膜的制造方法,其特征是将各导电粒子是以既定的位置固定在由高分子材构成的薄膜上或压入薄膜中。
13、如权利要求12所述的预置式导电薄膜的制造方法,其中,是先将液态高分子材预先披覆在一承载体上有既定的厚度,并待高分子材凝固后将结合有高分子材的承载体卷收成为圆卷状半成品。
14、如权利要求12所述的预置式导电薄膜的制造方法,其中,该承载体是可以为PET、PVC、PC。
15、如权利要求12所述的预置式导电薄膜的制造方法,其中,导电粒子是利用冲压下料的作业方式自金属板上被冲压到高分子材上的既定位置;或是经由既定的信道移植到高分子材上的既定位置。
16、如权利要求12所述的预置式导电薄膜的制造方法,其中,导电粒子可以为石墨、金、银、铜、镍、锌、铟、铋、铅、锡,或其合金粒子。
17、一种预置式导电薄膜,其特征是由不织布含浸液态高分子材料,再以烘干成型后,并将各导电粒子是以既定的位置固定在由不织布构成的薄膜上或压入薄膜中。
18、如权利要求17所述的预置式导电薄膜,其中,该不织布材料可以为PET纤维、木质纤维、植物纤维、玻璃纤维、陶瓷纤维或尼龙纤维。
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Cited By (6)

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CN102741946A (zh) * 2010-04-28 2012-10-17 株式会社自动网络技术研究所 线束制造方法
CN103151323A (zh) * 2011-12-06 2013-06-12 北京大学深圳研究生院 一种基于各向异性导电胶的倒装封装结构
CN103151113A (zh) * 2013-01-31 2013-06-12 中国科学院化学研究所 一种压敏导电膜的制备方法
TWI559826B (zh) * 2015-12-14 2016-11-21 財團法人工業技術研究院 接合結構及可撓式裝置
CN110600163A (zh) * 2019-09-19 2019-12-20 云谷(固安)科技有限公司 导电薄膜及其制备方法、显示装置
TWI690947B (zh) * 2018-11-30 2020-04-11 台灣愛司帝科技股份有限公司 導電物質的布局方法、布局結構及包含其之led顯示器

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102741946A (zh) * 2010-04-28 2012-10-17 株式会社自动网络技术研究所 线束制造方法
CN103151323A (zh) * 2011-12-06 2013-06-12 北京大学深圳研究生院 一种基于各向异性导电胶的倒装封装结构
CN103151113A (zh) * 2013-01-31 2013-06-12 中国科学院化学研究所 一种压敏导电膜的制备方法
CN103151113B (zh) * 2013-01-31 2015-07-08 中国科学院化学研究所 一种压敏导电膜的制备方法
TWI559826B (zh) * 2015-12-14 2016-11-21 財團法人工業技術研究院 接合結構及可撓式裝置
US9607960B1 (en) 2015-12-14 2017-03-28 Industrial Technology Research Institute Bonding structure and flexible device
CN106877030A (zh) * 2015-12-14 2017-06-20 财团法人工业技术研究院 接合结构及可挠式装置
CN106877030B (zh) * 2015-12-14 2019-05-03 财团法人工业技术研究院 接合结构及可挠式装置
TWI690947B (zh) * 2018-11-30 2020-04-11 台灣愛司帝科技股份有限公司 導電物質的布局方法、布局結構及包含其之led顯示器
CN110600163A (zh) * 2019-09-19 2019-12-20 云谷(固安)科技有限公司 导电薄膜及其制备方法、显示装置

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