TWI559826B - 接合結構及可撓式裝置 - Google Patents

接合結構及可撓式裝置 Download PDF

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Publication number
TWI559826B
TWI559826B TW104141996A TW104141996A TWI559826B TW I559826 B TWI559826 B TW I559826B TW 104141996 A TW104141996 A TW 104141996A TW 104141996 A TW104141996 A TW 104141996A TW I559826 B TWI559826 B TW I559826B
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Taiwan
Prior art keywords
contact pad
conductive particles
groove
contact
insulating layer
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TW104141996A
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English (en)
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TW201722220A (zh
Inventor
彭懿正
葉明華
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財團法人工業技術研究院
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Priority to TW104141996A priority Critical patent/TWI559826B/zh
Priority to US14/983,506 priority patent/US9607960B1/en
Priority to CN201511019558.5A priority patent/CN106877030B/zh
Application granted granted Critical
Publication of TWI559826B publication Critical patent/TWI559826B/zh
Publication of TW201722220A publication Critical patent/TW201722220A/zh

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Description

接合結構及可撓式裝置
本揭露是有關於一種接合結構及可撓式裝置，且特別是有關於一種增加面板元件壓合信賴性及耐撓曲性的接合結構及可撓式裝置。
異方性導電薄膜(Anisotropic Conductive Film, ACF)是指具有單方向導電特性的薄膜，其材料一般是由導電粒子與絕緣樹脂所構成。異方性導電薄膜主要應用在無法透過高溫鉛錫焊接的製程，譬如液晶顯示面板以及驅動IC之訊號傳輸連結。在軟性面板模組的製程中，常利用異方性導電膜來進行面板元件之接合。然而，於傳統的軟性面板中，異方性導電膜的導電粒子與面板元件接觸的面積較小，因而使面板元件之間的壓合信賴度變低。於可撓式裝置中，由於面板尺寸漲縮或變形亦會造成元件之間壓合/接合不易之問題。因此，如何克服現有面板元件壓合時的信賴性及耐撓曲性為目前所欲研究的主題。
本揭露實施例提供一種接合結構，其可用以增加面板元件壓合時的可靠度及耐撓曲性。
本揭露實施例所提出的接合結構包括接觸墊、異方性導電薄膜以及接觸結構。接觸墊具有至少一凹槽，其中接觸墊的厚度為T且至少一凹槽的寬度為B。異方性導電薄膜位於接觸墊上方並具有多個導電粒子，各導電粒子位於至少一凹槽中，其中，各導電粒子的直徑為A，且A大於B以及T，並且滿足:。B≦2(AT-T 2) 1/2接觸結構位於異方性導電薄膜上方並透過各導電粒子與接觸墊電性連接。
本揭露實施例另提供一種可撓式裝置，其面板元件壓合時的可靠度及耐撓曲性較佳。
本揭露實施例所提出的可撓式裝置包括基板、圖案化絕緣層、至少一接觸墊、異方性導電薄膜以及接觸結構。基板具有接合區域以及導線區域。圖案化絕緣層位於基板上方，且位於接合區域中。至少一接觸墊順應地覆蓋於圖案化絕緣層的上方以使得至少一接觸墊的表面具有至少一凹槽。異方性導電薄膜位於至少一接觸墊上方並具有多個導電粒子，各導電粒子位於至少一凹槽中。接觸結構位於異方性導電薄膜上方並透過導電粒子與接觸墊電性連接。
基於上述，由於本揭露實施例的接合結構以及可撓式裝置的接觸墊具有至少一凹槽，而導電粒子位於所述凹槽中。因此，當面板元件透過導電粒子進行接合時，其接觸點位或接觸面積透過凹槽的立體圖案而增加，因而能夠使面板元件壓合時的可靠度及耐撓曲性較佳。
為讓本揭露能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A為本揭露一實施例接合結構的剖面示意圖。圖1B為圖1A的局部剖面放大示意圖。請同時參考圖1A及圖1B，本實施例的接合結構包括接觸墊120、異方性導電薄膜130以及接觸結構140。上述接合結構設置於基板110上，基板110之材質可為玻璃、石英、有機聚合物、或是不透光/反射材料(例如：導電材料、金屬、晶圓、陶瓷、塑膠(PI、PET)或其它可適用的材料)、或是其它可適用的材料。若使用導電材料或金屬時，則在基板110上覆蓋一層絕緣層(未繪示)，以避免短路問題。
接觸墊120位於基板110上方，且接觸墊120為導電材料並可用以輸出或接收電子訊號。接觸墊120的材料包括單層或多層導電材料或導電金屬(如鉬鋁鉬、鈦鋁鈦或導電陶瓷(ITO、 IZO)之材料)，或是上述材料之組合。接觸墊120具有至少一凹槽R，且接觸墊120的厚度為T而至少一凹槽R的寬度為B。異方性導電薄膜130位於接觸墊120的上方。異方性導電薄膜130包括絕緣體131以及位於絕緣體131內的多個導電粒子132。在此，絕緣體131可以是熱固性或熱塑性高分子材料。導電粒子132 例如包括由聚合物、鎳(Nickel)以及金(Gold)所組成的有機/無機複合材料之粒子，但不限於此。異方性導電薄膜130中的各導電粒子132位於所述至少一凹槽R中，且各導電粒子132的直徑為A。在本實施例中，導電粒子132的直徑A大於凹槽R的寬度B以及接觸墊120的厚度T，且滿足：B≦2(AT-T 2) 1/2。凹槽R的寬度B以及接觸墊120的厚度T可在滿足上述條件的狀況下，依據導電粒子132的直徑A之大小而進行調整。
接觸結構140位於異方性導電薄膜130上方並透過導電粒子132與接觸墊120電性連接。在本實施例中，接觸結構140為導電材料，且例如為與晶片連接之接觸結構140，所述晶片包括二極體(Diode)、絕緣閘雙極性電晶體(IGBT)、金氧半場效電晶體(MOSFET)或其他的半導體元件，但不限於此。
於圖1A至圖1B的實施例中，導電粒子132位於接觸墊120的至少一凹槽R中，且導電粒子132的直徑A、凹槽R的寬度B以及接觸墊120的厚度T之比例均符合上述條件。因此，本揭露的接合結構中的導電粒子132與接觸墊120的接觸點位或接觸面積可以增加。換言之，透過接觸墊120之凹槽R的立體圖案化設計，可增加異方性導電薄膜130中導電粒子132於壓合面板元件時之有效接觸切面，使其壓合時的可靠度及耐撓曲性較佳。也就是說，可透過本揭露之接合結構來增加面板元件之間的導通信賴性，並降低接觸電阻減少雜訊發生機率。
在上述的實施例中，主要是說明接觸墊120具有至少一凹槽R。在下文中，將針對上述至少一凹槽R所設置的位置及圖案類型的各種實施例進行詳細說明。
圖2A至圖2C為本揭露一實施例接觸墊的上視示意圖。參考圖2A，接觸墊120中的凹槽R為孔狀圖案，且所述孔狀圖案為一圓孔。如圖2A所示，具有孔狀圖案之凹槽R在接觸墊120上是上排列成一陣列，但本揭露不限於此。舉例來說，如圖2B所示，具有孔狀圖案之凹槽R為一圓孔，且在接觸墊120上是不規則分佈。另外，在圖2C的實施例中，觸墊120中的凹槽R為孔狀圖案，且所述孔狀圖案為一三角形孔，並且在接觸墊120上是排列成一陣列。值得注意的是，上述具有孔狀圖案之凹槽R之排列及形狀無特別限制，且可為多邊形孔，但其仍需符合上述針對寬度B之條件限制，且其比例關係可參考圖1B。據此，導電粒子132能夠與接觸墊120有理想的接觸面積。
圖3A至圖3C為本揭露另一實施例接觸墊的上視示意圖。參考圖3A至圖3C，接觸墊120中的凹槽R為條狀圖案。如圖3A所示，具有條狀圖案之凹槽R在接觸墊120上是垂直排列，但本揭露不限於此。舉例來說，如圖3B所示，具有條狀圖案之凹槽R在接觸墊120上是橫向排列。另外，如圖3C所示，具有條狀圖案之凹槽R在接觸墊120上是斜向排列。值得注意的是，於圖3A至圖3C的實施例中，多個導電粒子132可位於各條狀圖案之凹槽R中，但條狀圖案之凹槽R之寬度B仍需符合上述條件限制，且其寬度B與導電粒子132的比例關係可參考圖1B。
由上述圖2A至圖2C以及圖3A至圖3C的實施例可得知，接觸墊120的凹槽R之設置位置及圖案類型沒有特別限制，且可依據需求而進行設定。但凹槽R之設計仍需符合上述條件限制以達到增加接觸面積，並使面板元件壓合時的可靠度及耐撓曲性較佳之功效。
在上述的實施例中，所述的至少一凹槽R均為貫穿孔之結構。也就是說，凹槽R貫穿整個接觸墊120，以暴露出接觸墊120下方之層面。但本揭露不限於此。圖4為本揭露另一實施例接合結構的剖面示意圖。圖4接合結構的實施例與圖1A的實施例類似，因此，相同元件以相同標號表示。圖4與圖1A之間的差異在於，圖4的接觸墊120之至少一凹槽R並非貫穿孔結構。詳細來說，於圖4的實施例中，接觸墊120之至少一凹槽R為盲孔結構。換言之，凹槽R並未貫穿整個接觸墊120，而僅是延伸至接觸墊120中。相同地，本實施例之凹槽R之設計仍需符合上述條件限制以達到增加接觸面積，並使面板元件壓合時的可靠度及耐撓曲性較佳之功效。
圖5A至圖5B為本揭露一實施例可撓式裝置的上視示意圖。上述可撓式裝置可為可撓式電子裝置，例如可撓式顯示器。圖6A為圖5A沿剖線A-A’的剖面示意圖。圖6B為圖5B沿剖線B-B’的剖面示意圖。請同時參考圖5A、圖5B、圖6A以及圖6B。本實施例是以具有顯示面板的可撓式裝置為例，但本揭露不限於此，且可為不包括顯示面板之可撓式裝置。在本實施例中，可撓式裝置包括基板110、圖案化絕緣層115、至少一接觸墊120、異方性導電薄膜130以及接觸結構140。基板110之材質可為玻璃、石英、有機聚合物、或是不透光/反射材料(例如：導電材料、金屬、晶圓、陶瓷、或其它可適用的材料)、或是其它可適用的材料。若使用導電材料或金屬時，則在基板110上覆蓋一層絕緣層(未繪示)，以避免短路問題。
詳細來說，基板110具有接合區域110B、導線區域110L以及主動區域110D。若可撓式裝置不包括顯示面板時，則基板110不包括主動區域110D。在本實施例中，主動區域110D包括多個顯示元件112。顯示元件112可包括多個主動元件以及畫素結構等能夠於主動區域110D提供顯示畫面之元件。圖案化絕緣層115位於基板110上方，且位於接合區域110B中。圖案化絕緣層115的材料例如是光阻材料、SiOx、SiO 2等氧化物材料，但不限於此。特別是，圖案化絕緣層115可做為應力調控層，以於面板元件壓合時能夠抑制面板的漲縮或翹曲。
另外，於接合區域110B中，更包括至少一接觸墊120，其中，至少一接觸墊120順應地覆蓋於圖案化絕緣層120的上方以使得至少一接觸墊120的表面具有至少一凹槽R。所述至少一凹槽R可參考前述實施例進行定義，於此不予贅述。在本實施例中，接觸墊120為導電材料並可用以輸出或接收電子訊號。特別是，接觸墊120可以分別電性連接至位於導線區域110L中對應的傳輸導線114。並且，再透過傳輸導線114電性連接至主動區域110D的顯示元件112。
接著，參考圖5B及圖6B，異方性導電薄膜130位於接觸墊120的上方。異方性導電薄膜130包括絕緣體131以及位於絕緣體131內的多個導電粒子132。在此，絕緣體131可以是熱固性或熱塑性高分子材料。異方性導電薄膜130中的各導電粒子132位於所述至少一凹槽R中。在本實施例中，導電粒子132的直徑、凹槽R的寬度以及接觸墊120的厚度之限制條件與圖1B的實施例的限制條件相同。另外，接觸結構140位於異方性導電薄膜130上方並透過導電粒子132與接觸墊120電性連接。
在本實施例中，接觸結構140為導電材料，且例如為與二極體(Diode)、絕緣閘雙極性電晶體(IGBT)、金氧半場效電晶體(MOSFET)等功率元件之晶片連接之接觸結構140。當接觸結構140透過導電粒子132與接觸墊120電性連接時，接觸墊120用以輸出或接收上述功率元件之電性訊號，並可透過導線區域110L中的傳輸導線114來驅動主動區域110D的顯示元件112以提供畫面顯示。
於圖5A、圖5B、圖6A以及圖6B的實施例中，圖案化絕緣層115可做為應力調控層，且接觸墊120順應地覆蓋圖案化絕緣層115，而導電粒子132位於接觸墊120的至少一凹槽R中。因此，本實施例的可撓式裝置中的導電粒子132與接觸墊120的接觸點位或接觸面積可以增加。換言之，透過圖案化絕緣層115之圖案使接觸墊120之凹槽R具有立體圖案化之設計，可增加異方性導電薄膜130中導電粒子132於壓合面板元件時之有效接觸切面，並且能夠使面板元件壓合時的可靠度及耐撓曲性較佳。也就是說，於本實施例的可撓式裝置中，其面板元件之間的導通信賴性較佳，且可降低接觸電阻減少雜訊發生機率。
於上述的實施例中，主要是說明接觸墊120可順應地覆蓋圖案化絕緣層115，而圖案化絕緣層115之設計並未特別限定。圖7為本揭露一實施例圖案化絕緣層的上視示意圖。參考圖7，在一實施例中，圖案化絕緣層115是具有網狀立體圖案，且所述網狀立體圖案包括多個縱向部115V以及多個橫向部115H。特別是，多個縱向部115V以及多個橫向部115H交錯排列以構成所述網狀立體圖案。由於圖案化絕緣層115具有網狀立體圖案，因此，能夠使覆蓋於其上方之接觸墊120具有同樣的立體圖案化之設計。此種設計能夠進一步增加異方性導電薄膜130中導電粒子132於壓合面板元件時與接觸墊120之有效接觸切面，使面板元件壓合時的可靠度及耐撓曲性較佳。
圖8A為本揭露一實施例可撓式裝置的上視示意圖。在本實施例中，圖案化絕緣層115之整層可為網狀立體圖案，且圖案化絕緣層115僅位於接合區域110B中。據此，當接觸墊120覆蓋於圖案化絕緣層115的上方時，其能夠具有立體圖案化之設計，使導電粒子132位於接觸墊120的凹槽R中。然而，本揭露不限於此，在其它實施例中，可對圖案化絕緣層115之分佈位置進行改變。圖8B為本揭露另一實施例可撓式裝置的上視示意圖。在本實施例中，圖案化絕緣層115位於接合區域110B中，且圖案化絕緣層115更延伸至導線區域110L中。相同地，當接觸墊120覆蓋於圖案化絕緣層115的上方時，其能夠具有立體圖案化之設計，使導電粒子132位於接觸墊120的凹槽R中。藉由上述的實施例可以得知，圖案化絕緣層115之分佈位置並未特別限制，而其僅需位於接觸墊120下方，且可另外依據需求將圖案化絕緣層115設置於整個接合區域110B以及導線區域110L中。
綜上所述，本揭露的接合結構之導電粒子132位於接觸墊120的至少一凹槽R中，且導電粒子132的直徑A、凹槽R的寬度B以及接觸墊120的厚度T之比例均符合一定的限制條件。因此，本揭露的接合結構中的導電粒子132與接觸墊120的接觸點位或接觸面積可以增加，並且使其壓合時的可靠度及耐撓曲性較佳。相同地，本揭露的可撓式裝置之圖案化絕緣層115可做為應力調控層，且接觸墊120順應地覆蓋圖案化絕緣層115，而導電粒子132位於接觸墊120的至少一凹槽R中。因此，本揭露的可撓式裝置中的導電粒子132與接觸墊120的接觸點位或接觸面積可以增加，進而使其面板元件壓合時的可靠度及耐撓曲性較佳。
雖然本揭露已以實施例揭露如上，然其並非用以限定本揭露，任何所屬技術領域中具有通常知識者，在不脫離本揭露的精神和範圍內，當可作些許的更動與潤飾，故本揭露的保護範圍當視後附的申請專利範圍所界定者為準。
110‧‧‧基板
110B‧‧‧接合區域
110D‧‧‧主動區域
110L‧‧‧導線區域
112‧‧‧顯示元件
114‧‧‧傳輸導線
115‧‧‧圖案化絕緣層
115V‧‧‧縱向部
115H‧‧‧橫向部
120‧‧‧接觸墊
130‧‧‧異方性導電薄膜
131‧‧‧絕緣體
132‧‧‧導電粒子
140‧‧‧接觸結構
R‧‧‧凹槽
圖1A為本揭露一實施例接合結構的剖面示意圖。 圖1B為圖1A的局部剖面放大示意圖。 圖2A至圖2C為本揭露一實施例接觸墊的上視示意圖。 圖3A至圖3C為本揭露另一實施例接觸墊的上視示意圖。 圖4為本揭露另一實施例接合結構的剖面示意圖。 圖5A至圖5B為本揭露一實施例可撓式裝置的上視示意圖。 圖6A為圖5A沿剖線A-A’的剖面示意圖。 圖6B為圖5B沿剖線B-B’的剖面示意圖。 圖7為本揭露一實施例圖案化絕緣層的上視示意圖。 圖8A為本揭露一實施例可撓式裝置的上視示意圖。 圖8B為本揭露另一實施例可撓式裝置的上視示意圖。
110‧‧‧基板
120‧‧‧接觸墊
130‧‧‧異方性導電薄膜
131‧‧‧絕緣體
132‧‧‧導電粒子
140‧‧‧接觸結構
R‧‧‧凹槽

Claims (14)

  1. 一種接合結構，包括：一接觸墊，該接觸墊具有至少一凹槽，其中該接觸墊的厚度為T且該至少一凹槽的寬度為B；一異方性導電薄膜，該異方性導電薄膜位於該接觸墊上方並具有多個導電粒子，各該導電粒子位於該至少一凹槽中，其中各該導電粒子的直徑為A，且A大於B以及T，並且滿足：B≦2(AT-T2)1/2；以及一接觸結構，該接觸結構位於該異方性導電薄膜上方並透過該些導電粒子與該接觸墊電性連接。
  2. 如申請專利範圍第1項所述的接合結構，其中該異方性導電薄膜更包括一絕緣體，該多個導電粒子位於該絕緣體內。
  3. 如申請專利範圍第1項所述的接合結構，其中該至少一凹槽為一孔狀圖案。
  4. 如申請專利範圍第3項所述的接合結構，其中該孔狀圖案為一圓孔、一三角形孔或多邊形孔。
  5. 如申請專利範圍第3項所述的接合結構，其中該孔狀圖案在該接觸墊上排列成一陣列。
  6. 如申請專利範圍第3項所述的接合結構，其中該孔狀圖案在該接觸墊上不規則分佈。
  7. 如申請專利範圍第1項所述的接合結構，其中該至少一凹槽為條狀圖案。
  8. 如申請專利範圍第1項所述的接合結構，其中至少一凹槽為貫穿孔或是盲孔結構。
  9. 一種可撓式裝置，包括：一基板，該基板具有一接合區域以及一導線區域；一圖案化絕緣層，該圖案化絕緣層位於該基板上方，且位於該接合區域中；至少一接觸墊，該至少一接觸墊順應地覆蓋於該圖案化絕緣層的上方以使得該至少一接觸墊的表面具有至少一凹槽；一異方性導電薄膜，該異方性導電薄膜位於該至少一接觸墊上方並具有多個導電粒子，各該導電粒子位於該至少一凹槽中，其中該觸墊的厚度為T、該至少一凹槽的寬度為B且各該導電粒子的直徑為A，其中A大於B以及T，並且滿足：B≦2(AT-T2)1/2；一接觸結構，該接觸結構位於該異方性導電薄膜上方並透過該些導電粒子與該接觸墊連接。
  10. 如申請專利範圍第9項所述的可撓式裝置，其中該異方性導電薄膜更包括一絕緣體，該多個導電粒子位於該絕緣體內。
  11. 如申請專利範圍第9項所述的可撓式裝置，其中該圖案化絕緣層具有一網狀立體圖案。
  12. 如申請專利範圍第12項所述的可撓式裝置，其中該網狀立體圖案包括多個縱向部以及多個橫向部，該些縱向部以及該些橫向部交錯排列以構成該網狀立體圖案。
  13. 如申請專利範圍第12項所述的可撓式裝置，其中該圖案化絕緣層更延伸至該導線區域中。
  14. 如申請專利範圍第12項所述的可撓式裝置，其中該網狀立體圖案的材料包括光阻材料或氧化物材料。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3779583B1 (en) * 2018-04-05 2023-12-06 Toppan Printing Co., Ltd. Light control unit
CN109628002B (zh) * 2018-11-21 2020-06-02 武汉华星光电半导体显示技术有限公司 异方性导电胶带及其制作方法
CN110634925B (zh) * 2019-09-25 2022-05-13 京东方科技集团股份有限公司 显示面板及其制造方法、绑定方法、显示装置
CN111552129B (zh) * 2020-05-25 2023-10-13 Tcl华星光电技术有限公司 液晶显示面板

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1848394A (zh) * 2005-04-13 2006-10-18 邹明德 预置式导电薄膜构装及其成型方法
CN103491703A (zh) * 2013-07-04 2014-01-01 友达光电股份有限公司 显示装置及其电路板模块

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3883641B2 (ja) 1997-03-27 2007-02-21 株式会社半導体エネルギー研究所 コンタクト構造およびアクティブマトリクス型表示装置
US7189595B2 (en) * 2001-05-31 2007-03-13 International Business Machines Corporation Method of manufacture of silicon based package and devices manufactured thereby
US7038327B2 (en) 2003-11-11 2006-05-02 Au Optronics Corp. Anisotropic conductive film bonding pad
TWI311676B (en) 2004-01-30 2009-07-01 Au Optronics Corp Carrier and semiconductor structure incorporating teh same
US7515240B2 (en) 2004-10-05 2009-04-07 Au Optronics Corporation Flat display panel and assembly process or driver components in flat display panel
TWI351670B (en) 2006-05-18 2011-11-01 Au Optronics Corp Signal transmission assembly and display panel app
JP2008192833A (ja) * 2007-02-05 2008-08-21 Shinko Electric Ind Co Ltd 半導体装置の製造方法
CN201910415U (zh) 2010-12-25 2011-07-27 福建华映显示科技有限公司 导电垫结构、芯片封装结构及主动组件数组基板
KR101871773B1 (ko) * 2012-07-25 2018-06-27 엘지디스플레이 주식회사 플라스틱패널 및 이를 이용한 평판표시장치
KR101876234B1 (ko) 2012-07-25 2018-07-09 엘지디스플레이 주식회사 플라스틱패널 및 이를 이용한 평판표시장치
TWI492357B (zh) 2013-02-22 2015-07-11 Hanns Touch Solution Corp 觸控面板及其電路結構
US9691745B2 (en) * 2013-06-26 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding structure for forming a package on package (PoP) structure and method for forming the same
US9355927B2 (en) * 2013-11-25 2016-05-31 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor packaging and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1848394A (zh) * 2005-04-13 2006-10-18 邹明德 预置式导电薄膜构装及其成型方法
CN103491703A (zh) * 2013-07-04 2014-01-01 友达光电股份有限公司 显示装置及其电路板模块

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